^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * ths7303/53- THS7303/53 Video Amplifier driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2013 Cisco Systems, Inc. and/or its affiliates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Chaithrika U S <chaithrika@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Contributors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Hans Verkuil <hans.verkuil@cisco.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Lad, Prabhakar <prabhakar.lad@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Martin Bugge <marbugge@cisco.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This program is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * published by the Free Software Foundation version 2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * This program is distributed .as is. WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/i2c/ths7303.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define THS7303_CHANNEL_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define THS7303_CHANNEL_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define THS7303_CHANNEL_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct ths7303_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) const struct ths7303_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct v4l2_bt_timings bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int std_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) int stream_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) enum ths7303_filter_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) THS7303_FILTER_MODE_480I_576I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) THS7303_FILTER_MODE_480P_576P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) THS7303_FILTER_MODE_720P_1080I,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) THS7303_FILTER_MODE_1080P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) THS7303_FILTER_MODE_DISABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MODULE_DESCRIPTION("TI THS7303 video amplifier driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MODULE_AUTHOR("Chaithrika U S");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static inline struct ths7303_state *to_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return container_of(sd, struct ths7303_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int ths7303_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static int ths7303_write(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) ret = i2c_smbus_write_byte_data(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* following function is used to set ths7303 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static int ths7303_setval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) enum ths7303_filter_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct ths7303_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) const struct ths7303_platform_data *pdata = state->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u8 val, sel = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int err, disable = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (!client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) switch (mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) case THS7303_FILTER_MODE_1080P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) sel = 0x3; /*1080p and SXGA/UXGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) case THS7303_FILTER_MODE_720P_1080I:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) sel = 0x2; /*720p, 1080i and SVGA/XGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) case THS7303_FILTER_MODE_480P_576P:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) sel = 0x1; /* EDTV 480p/576p and VGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) case THS7303_FILTER_MODE_480I_576I:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) sel = 0x0; /* SDTV, S-Video, 480i/576i */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* disable all channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) disable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) val = (sel << 6) | (sel << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (!disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) val |= (pdata->ch_1 & 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) err = ths7303_write(sd, THS7303_CHANNEL_1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) val = (sel << 6) | (sel << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (!disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) val |= (pdata->ch_2 & 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) err = ths7303_write(sd, THS7303_CHANNEL_2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) val = (sel << 6) | (sel << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (!disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) val |= (pdata->ch_3 & 0x27);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) err = ths7303_write(sd, THS7303_CHANNEL_3, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) pr_info("write byte data failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) static int ths7303_s_std_output(struct v4l2_subdev *sd, v4l2_std_id norm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct ths7303_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (norm & (V4L2_STD_ALL & ~V4L2_STD_SECAM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) state->std_id = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) state->bt.pixelclock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return ths7303_setval(sd, THS7303_FILTER_MODE_480I_576I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) return ths7303_setval(sd, THS7303_FILTER_MODE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static int ths7303_config(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct ths7303_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (!state->stream_on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) ths7303_write(sd, THS7303_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) (ths7303_read(sd, THS7303_CHANNEL_1) & 0xf8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ths7303_write(sd, THS7303_CHANNEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) (ths7303_read(sd, THS7303_CHANNEL_2) & 0xf8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ths7303_write(sd, THS7303_CHANNEL_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) (ths7303_read(sd, THS7303_CHANNEL_3) & 0xf8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) if (state->bt.pixelclock > 120000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) res = ths7303_setval(sd, THS7303_FILTER_MODE_1080P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) else if (state->bt.pixelclock > 70000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) res = ths7303_setval(sd, THS7303_FILTER_MODE_720P_1080I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) else if (state->bt.pixelclock > 20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) res = ths7303_setval(sd, THS7303_FILTER_MODE_480P_576P);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) else if (state->std_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) res = ths7303_setval(sd, THS7303_FILTER_MODE_480I_576I);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* disable all channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) res = ths7303_setval(sd, THS7303_FILTER_MODE_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int ths7303_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct ths7303_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) state->stream_on = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return ths7303_config(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* for setting filter for HD output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static int ths7303_s_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct v4l2_dv_timings *dv_timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct ths7303_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) if (!dv_timings || dv_timings->type != V4L2_DV_BT_656_1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) state->bt = dv_timings->bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) state->std_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return ths7303_config(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct v4l2_subdev_video_ops ths7303_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .s_stream = ths7303_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .s_std_output = ths7303_s_std_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .s_dv_timings = ths7303_s_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static int ths7303_g_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) reg->size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) reg->val = ths7303_read(sd, reg->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int ths7303_s_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) ths7303_write(sd, reg->reg, reg->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static const char * const stc_lpf_sel_txt[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "500-kHz Filter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "2.5-MHz Filter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "5-MHz Filter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "5-MHz Filter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static const char * const in_mux_sel_txt[2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) "Input A Select",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "Input B Select",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static const char * const lpf_freq_sel_txt[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "9-MHz LPF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "16-MHz LPF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "35-MHz LPF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "Bypass LPF",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static const char * const in_bias_sel_dis_cont_txt[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "Disable Channel",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "Mute Function - No Output",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "DC Bias Select",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "DC Bias + 250 mV Offset Select",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "AC Bias Select",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "Sync Tip Clamp with low bias",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "Sync Tip Clamp with mid bias",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "Sync Tip Clamp with high bias",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static void ths7303_log_channel_status(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u8 val = ths7303_read(sd, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if ((val & 0x7) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) v4l2_info(sd, "Channel %d Off\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) v4l2_info(sd, "Channel %d On\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) v4l2_info(sd, " value 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) v4l2_info(sd, " %s\n", stc_lpf_sel_txt[(val >> 6) & 0x3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) v4l2_info(sd, " %s\n", in_mux_sel_txt[(val >> 5) & 0x1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) v4l2_info(sd, " %s\n", lpf_freq_sel_txt[(val >> 3) & 0x3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) v4l2_info(sd, " %s\n", in_bias_sel_dis_cont_txt[(val >> 0) & 0x7]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static int ths7303_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct ths7303_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) v4l2_info(sd, "stream %s\n", state->stream_on ? "On" : "Off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (state->bt.pixelclock) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct v4l2_bt_timings *bt = &state->bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 frame_width, frame_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) frame_width = V4L2_DV_BT_FRAME_WIDTH(bt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) frame_height = V4L2_DV_BT_FRAME_HEIGHT(bt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) v4l2_info(sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "timings: %dx%d%s%d (%dx%d). Pix freq. = %d Hz. Polarities = 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) bt->width, bt->height, bt->interlaced ? "i" : "p",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) (frame_height * frame_width) > 0 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) (int)bt->pixelclock /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) (frame_height * frame_width) : 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) frame_width, frame_height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) (int)bt->pixelclock, bt->polarities);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) v4l2_info(sd, "no timings set\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ths7303_log_channel_status(sd, THS7303_CHANNEL_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ths7303_log_channel_status(sd, THS7303_CHANNEL_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ths7303_log_channel_status(sd, THS7303_CHANNEL_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static const struct v4l2_subdev_core_ops ths7303_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .log_status = ths7303_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .g_register = ths7303_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .s_register = ths7303_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static const struct v4l2_subdev_ops ths7303_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .core = &ths7303_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .video = &ths7303_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) static int ths7303_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct ths7303_platform_data *pdata = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct ths7303_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (pdata == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dev_err(&client->dev, "No platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) v4l_info(client, "chip found @ 0x%x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) state = devm_kzalloc(&client->dev, sizeof(struct ths7303_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) state->pdata = pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) v4l2_i2c_subdev_init(sd, client, &ths7303_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* set to default 480I_576I filter mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (ths7303_setval(sd, THS7303_FILTER_MODE_480I_576I) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) v4l_err(client, "Setting to 480I_576I filter mode failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int ths7303_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static const struct i2c_device_id ths7303_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {"ths7303", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {"ths7353", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MODULE_DEVICE_TABLE(i2c, ths7303_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static struct i2c_driver ths7303_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .name = "ths73x3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .probe = ths7303_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .remove = ths7303_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .id_table = ths7303_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) module_i2c_driver(ths7303_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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