^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __INCLUDED_TEA6415C__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __INCLUDED_TEA6415C__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) /* the tea6415c's design is quite brain-dead. although there are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) 8 inputs and 6 outputs, these aren't enumerated in any way. because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) I don't want to say "connect input pin 20 to output pin 17", I define
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) a "virtual" pin-order. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* input pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define TEA6415C_OUTPUT1 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TEA6415C_OUTPUT2 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TEA6415C_OUTPUT3 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TEA6415C_OUTPUT4 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TEA6415C_OUTPUT5 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEA6415C_OUTPUT6 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* output pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEA6415C_INPUT1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEA6415C_INPUT2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEA6415C_INPUT3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEA6415C_INPUT4 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEA6415C_INPUT5 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEA6415C_INPUT6 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEA6415C_INPUT7 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEA6415C_INPUT8 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #endif