Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) 2018 Gateworks Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) /* Page 0x00 - General Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define REG_VERSION		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define REG_INPUT_SEL		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define REG_SVC_MODE		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define REG_HPD_MAN_CTRL	0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define REG_RT_MAN_CTRL		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define REG_STANDBY_SOFT_RST	0x000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define REG_HDMI_SOFT_RST	0x000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define REG_HDMI_INFO_RST	0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define REG_INT_FLG_CLR_TOP	0x000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define REG_INT_FLG_CLR_SUS	0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define REG_INT_FLG_CLR_DDC	0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define REG_INT_FLG_CLR_RATE	0x0011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define REG_INT_FLG_CLR_MODE	0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define REG_INT_FLG_CLR_INFO	0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define REG_INT_FLG_CLR_AUDIO	0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define REG_INT_FLG_CLR_HDCP	0x0015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define REG_INT_FLG_CLR_AFE	0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define REG_INT_MASK_TOP	0x0017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define REG_INT_MASK_SUS	0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define REG_INT_MASK_DDC	0x0019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define REG_INT_MASK_RATE	0x001A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define REG_INT_MASK_MODE	0x001B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define REG_INT_MASK_INFO	0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define REG_INT_MASK_AUDIO	0x001D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define REG_INT_MASK_HDCP	0x001E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define REG_INT_MASK_AFE	0x001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define REG_DETECT_5V		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define REG_SUS_STATUS		0x0021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define REG_V_PER		0x0022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define REG_H_PER		0x0025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define REG_HS_WIDTH		0x0027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define REG_FMT_H_TOT		0x0029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define REG_FMT_H_ACT		0x002b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define REG_FMT_H_FRONT		0x002d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define REG_FMT_H_SYNC		0x002f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define REG_FMT_H_BACK		0x0031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define REG_FMT_V_TOT		0x0033
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define REG_FMT_V_ACT		0x0035
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define REG_FMT_V_FRONT_F1	0x0037
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define REG_FMT_V_FRONT_F2	0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define REG_FMT_V_SYNC		0x0039
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define REG_FMT_V_BACK_F1	0x003a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define REG_FMT_V_BACK_F2	0x003b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define REG_FMT_DE_ACT		0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define REG_RATE_CTRL		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define REG_CLK_MIN_RATE	0x0043
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define REG_CLK_MAX_RATE	0x0046
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define REG_CLK_A_STATUS	0x0049
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define REG_CLK_A_RATE		0x004A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define REG_DRIFT_CLK_A_REG	0x004D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define REG_CLK_B_STATUS	0x004E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define REG_CLK_B_RATE		0x004F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define REG_DRIFT_CLK_B_REG	0x0052
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define REG_HDCP_CTRL		0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define REG_HDCP_KDS		0x0061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define REG_HDCP_BCAPS		0x0063
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define REG_HDCP_KEY_CTRL	0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define REG_INFO_CTRL		0x0076
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define REG_INFO_EXCEED		0x0077
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define REG_PIX_REPEAT		0x007B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define REG_AUDIO_PATH		0x007C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define REG_AUDCFG		0x007D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define REG_AUDIO_OUT_ENABLE	0x007E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define REG_AUDIO_OUT_HIZ	0x007F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define REG_VDP_CTRL		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define REG_VDP_MATRIX		0x0081
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define REG_VHREF_CTRL		0x00A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define REG_PXCNT_PR		0x00A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define REG_PXCNT_NPIX		0x00A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define REG_LCNT_PR		0x00A6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define REG_LCNT_NLIN		0x00A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define REG_HREF_S		0x00AA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define REG_HREF_E		0x00AC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define REG_HS_S		0x00AE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define REG_HS_E		0x00B0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define REG_VREF_F1_S		0x00B2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define REG_VREF_F1_WIDTH	0x00B4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define REG_VREF_F2_S		0x00B5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define REG_VREF_F2_WIDTH	0x00B7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define REG_VS_F1_LINE_S	0x00B8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define REG_VS_F1_LINE_WIDTH	0x00BA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define REG_VS_F2_LINE_S	0x00BB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define REG_VS_F2_LINE_WIDTH	0x00BD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define REG_VS_F1_PIX_S		0x00BE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define REG_VS_F1_PIX_E		0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define REG_VS_F2_PIX_S		0x00C2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define REG_VS_F2_PIX_E		0x00C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define REG_FREF_F1_S		0x00C6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define REG_FREF_F2_S		0x00C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define REG_FDW_S		0x00ca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define REG_FDW_E		0x00cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define REG_BLK_GY		0x00da
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define REG_BLK_BU		0x00dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define REG_BLK_RV		0x00de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define REG_FILTERS_CTRL	0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define REG_DITHERING_CTRL	0x00E9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define REG_OF			0x00EA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define REG_PCLK		0x00EB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define REG_HS_HREF		0x00EC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define REG_VS_VREF		0x00ED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define REG_DE_FREF		0x00EE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define REG_VP35_32_CTRL	0x00EF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define REG_VP31_28_CTRL	0x00F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define REG_VP27_24_CTRL	0x00F1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define REG_VP23_20_CTRL	0x00F2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define REG_VP19_16_CTRL	0x00F3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define REG_VP15_12_CTRL	0x00F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define REG_VP11_08_CTRL	0x00F5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define REG_VP07_04_CTRL	0x00F6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define REG_VP03_00_CTRL	0x00F7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define REG_CURPAGE_00H		0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MASK_VPER		0x3fffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MASK_VHREF		0x3fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MASK_HPER		0x0fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MASK_HSWIDTH		0x03ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* HPD Detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DETECT_UTIL		BIT(7)	/* utility of HDMI level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DETECT_HPD		BIT(6)	/* HPD of HDMI level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DETECT_5V_SEL		BIT(2)	/* 5V present on selected input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DETECT_5V_B		BIT(1)	/* 5V present on input B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DETECT_5V_A		BIT(0)	/* 5V present on input A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Input Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define INPUT_SEL_RST_FMT	BIT(7)	/* 1=reset format measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define INPUT_SEL_RST_VDP	BIT(2)	/* 1=reset video data path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define INPUT_SEL_OUT_MODE	BIT(1)	/* 0=loop 1=bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define INPUT_SEL_B		BIT(0)	/* 0=inputA 1=inputB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Service Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define SVC_MODE_CLK2_MASK	0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SVC_MODE_CLK2_SHIFT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SVC_MODE_CLK2_XTL	0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SVC_MODE_CLK2_XTLDIV2	1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SVC_MODE_CLK2_HDMIX2	3L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SVC_MODE_CLK1_MASK	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SVC_MODE_CLK1_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SVC_MODE_CLK1_XTAL	0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SVC_MODE_CLK1_XTLDIV2	1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SVC_MODE_CLK1_HDMI	3L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SVC_MODE_RAMP		BIT(3)	/* 0=colorbar 1=ramp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SVC_MODE_PAL		BIT(2)	/* 0=NTSC(480i/p) 1=PAL(576i/p) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SVC_MODE_INT_PROG	BIT(1)	/* 0=interlaced 1=progressive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SVC_MODE_SM_ON		BIT(0)	/* Enable color bars and tone gen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* HDP Manual Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HPD_MAN_CTRL_HPD_PULSE	BIT(7)	/* HPD Pulse low 110ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HPD_MAN_CTRL_5VEN	BIT(2)	/* Output 5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HPD_MAN_CTRL_HPD_B	BIT(1)	/* Assert HPD High for Input A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HPD_MAN_CTRL_HPD_A	BIT(0)	/* Assert HPD High for Input A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* RT_MAN_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define RT_MAN_CTRL_RT_AUTO	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define RT_MAN_CTRL_RT		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RT_MAN_CTRL_RT_B	BIT(1)	/* enable TMDS pull-up on Input B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RT_MAN_CTRL_RT_A	BIT(0)	/* enable TMDS pull-up on Input A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* VDP_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define VDP_CTRL_COMPDEL_BP	BIT(5)	/* bypass compdel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define VDP_CTRL_FORMATTER_BP	BIT(4)	/* bypass formatter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define VDP_CTRL_PREFILTER_BP	BIT(1)	/* bypass prefilter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define VDP_CTRL_MATRIX_BP	BIT(0)	/* bypass matrix conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* REG_VHREF_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define VHREF_INT_DET		BIT(7)	/* interlace detect: 1=alt 0=frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define VHREF_VSYNC_MASK	0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define VHREF_VSYNC_SHIFT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define VHREF_VSYNC_AUTO	0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define VHREF_VSYNC_FDW		1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define VHREF_VSYNC_EVEN	2L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define VHREF_VSYNC_ODD		3L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define VHREF_STD_DET_MASK	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define VHREF_STD_DET_SHIFT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define VHREF_STD_DET_PAL	0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define VHREF_STD_DET_NTSC	1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define VHREF_STD_DET_AUTO	2L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define VHREF_STD_DET_OFF	3L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define VHREF_VREF_SRC_STD	BIT(2)	/* 1=from standard 0=manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define VHREF_HREF_SRC_STD	BIT(1)	/* 1=from standard 0=manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define VHREF_HSYNC_SEL_HS	BIT(0)	/* 1=HS 0=VS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* AUDIO_OUT_ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AUDIO_OUT_ENABLE_ACLK	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AUDIO_OUT_ENABLE_WS	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define AUDIO_OUT_ENABLE_AP3	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define AUDIO_OUT_ENABLE_AP2	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define AUDIO_OUT_ENABLE_AP1	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AUDIO_OUT_ENABLE_AP0	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Prefilter Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define FILTERS_CTRL_BU_MASK	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define FILTERS_CTRL_BU_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define FILTERS_CTRL_RV_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define FILTERS_CTRL_RV_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define FILTERS_CTRL_OFF	0L	/* off */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define FILTERS_CTRL_2TAP	1L	/* 2 Taps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define FILTERS_CTRL_7TAP	2L	/* 7 Taps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define FILTERS_CTRL_2_7TAP	3L	/* 2/7 Taps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* PCLK Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define PCLK_DELAY_MASK		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PCLK_DELAY_SHIFT	4	/* Pixel delay (-8..+7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PCLK_INV_SHIFT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PCLK_SEL_MASK		0x03	/* clock scaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PCLK_SEL_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define PCLK_SEL_X1		0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define PCLK_SEL_X2		1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define PCLK_SEL_DIV2		2L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define PCLK_SEL_DIV4		3L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Pixel Repeater */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define PIX_REPEAT_MASK_UP_SEL	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define PIX_REPEAT_MASK_REP	0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define PIX_REPEAT_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define PIX_REPEAT_CHROMA	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* Page 0x01 - HDMI info and packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define REG_HDMI_FLAGS		0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define REG_DEEP_COLOR_MODE	0x0101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define REG_AUDIO_FLAGS		0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define REG_AUDIO_FREQ		0x0109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define REG_ACP_PACKET_TYPE	0x0141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define REG_ISRC1_PACKET_TYPE	0x0161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define REG_ISRC2_PACKET_TYPE	0x0181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define REG_GBD_PACKET_TYPE	0x01a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* HDMI_FLAGS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define HDMI_FLAGS_AUDIO	BIT(7)	/* Audio packet in last videoframe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define HDMI_FLAGS_HDMI		BIT(6)	/* HDMI detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define HDMI_FLAGS_EESS		BIT(5)	/* EESS detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define HDMI_FLAGS_HDCP		BIT(4)	/* HDCP detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define HDMI_FLAGS_AVMUTE	BIT(3)	/* AVMUTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define HDMI_FLAGS_AUD_LAYOUT	BIT(2)	/* Layout status Audio sample packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define HDMI_FLAGS_AUD_FIFO_OF	BIT(1)	/* FIFO read/write pointers crossed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define HDMI_FLAGS_AUD_FIFO_LOW	BIT(0)	/* FIFO read ptr within 2 of write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* Page 0x12 - HDMI Extra control and debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define REG_CLK_CFG		0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define REG_CLK_OUT_CFG		0x1201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define REG_CFG1		0x1202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define REG_CFG2		0x1203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define REG_WDL_CFG		0x1210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define REG_DELOCK_DELAY	0x1212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define REG_PON_OVR_EN		0x12A0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define REG_PON_CBIAS		0x12A1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define REG_PON_RESCAL		0x12A2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define REG_PON_RES		0x12A3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define REG_PON_CLK		0x12A4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define REG_PON_PLL		0x12A5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define REG_PON_EQ		0x12A6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define REG_PON_DES		0x12A7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define REG_PON_OUT		0x12A8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define REG_PON_MUX		0x12A9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define REG_MODE_REC_CFG1	0x12F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define REG_MODE_REC_CFG2	0x12F9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define REG_MODE_REC_STS	0x12FA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define REG_AUDIO_LAYOUT	0x12D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define PON_EN			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define PON_DIS			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* CLK CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CLK_CFG_INV_OUT_CLK	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CLK_CFG_INV_BUS_CLK	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CLK_CFG_SEL_ACLK_EN	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CLK_CFG_SEL_ACLK	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CLK_CFG_DIS		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Page 0x13 - HDMI Extra control and debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define REG_DEEP_COLOR_CTRL	0x1300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define REG_CGU_DBG_SEL		0x1305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define REG_HDCP_DDC_ADDR	0x1310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define REG_HDCP_KIDX		0x1316
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define REG_DEEP_PLL7_BYP	0x1347
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define REG_HDCP_DE_CTRL	0x1370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define REG_HDCP_EP_FILT_CTRL	0x1371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define REG_HDMI_CTRL		0x1377
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define REG_HMTP_CTRL		0x137a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define REG_TIMER_D		0x13CF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define REG_SUS_SET_RGB0	0x13E1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define REG_SUS_SET_RGB1	0x13E2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define REG_SUS_SET_RGB2	0x13E3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define REG_SUS_SET_RGB3	0x13E4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define REG_SUS_SET_RGB4	0x13E5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define REG_MAN_SUS_HDMI_SEL	0x13E8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define REG_MAN_HDMI_SET	0x13E9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define REG_SUS_CLOCK_GOOD	0x13EF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* HDCP DE Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define HDCP_DE_MODE_MASK	0xc0	/* DE Measurement mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define HDCP_DE_MODE_SHIFT	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define HDCP_DE_REGEN_EN	BIT(5)	/* enable regen mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define HDCP_DE_FILTER_MASK	0x18	/* DE filter sensitivity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define HDCP_DE_FILTER_SHIFT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define HDCP_DE_COMP_MASK	0x07	/* DE Composition mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define HDCP_DE_COMP_MIXED	6L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define HDCP_DE_COMP_OR		5L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define HDCP_DE_COMP_AND	4L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define HDCP_DE_COMP_CH3	3L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define HDCP_DE_COMP_CH2	2L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define HDCP_DE_COMP_CH1	1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define HDCP_DE_COMP_CH0	0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* HDCP EP Filter Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define HDCP_EP_FIL_CTL_MASK	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define HDCP_EP_FIL_CTL_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define HDCP_EP_FIL_VS_MASK	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define HDCP_EP_FIL_VS_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define HDCP_EP_FIL_HS_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define HDCP_EP_FIL_HS_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* HDMI_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define HDMI_CTRL_MUTE_MASK	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define HDMI_CTRL_MUTE_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define HDMI_CTRL_MUTE_AUTO	0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define HDMI_CTRL_MUTE_OFF	1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define HDMI_CTRL_MUTE_ON	2L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define HDMI_CTRL_HDCP_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define HDMI_CTRL_HDCP_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define HDMI_CTRL_HDCP_EESS	2L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define HDMI_CTRL_HDCP_OESS	1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define HDMI_CTRL_HDCP_AUTO	0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* CGU_DBG_SEL bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define CGU_DBG_CLK_SEL_MASK	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define CGU_DBG_CLK_SEL_SHIFT	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CGU_DBG_XO_FRO_SEL	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define CGU_DBG_VDP_CLK_SEL	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CGU_DBG_PIX_CLK_SEL	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* REG_MAN_SUS_HDMI_SEL / REG_MAN_HDMI_SET bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define MAN_DIS_OUT_BUF		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define MAN_DIS_ANA_PATH	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define MAN_DIS_HDCP		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define MAN_DIS_TMDS_ENC	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define MAN_DIS_TMDS_FLOW	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define MAN_RST_HDCP		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define MAN_RST_TMDS_ENC	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define MAN_RST_TMDS_FLOW	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* Page 0x14 - Audio Extra control and debug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define REG_FIFO_LATENCY_VAL	0x1403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define REG_AUDIO_CLOCK		0x1411
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define REG_TEST_NCTS_CTRL	0x1415
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define REG_TEST_AUDIO_FREQ	0x1426
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define REG_TEST_MODE		0x1437
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* Audio Clock Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define AUDIO_CLOCK_PLL_PD	BIT(7)	/* powerdown PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define AUDIO_CLOCK_SEL_MASK	0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define AUDIO_CLOCK_SEL_16FS	0L	/* 16*fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define AUDIO_CLOCK_SEL_32FS	1L	/* 32*fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define AUDIO_CLOCK_SEL_64FS	2L	/* 64*fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define AUDIO_CLOCK_SEL_128FS	3L	/* 128*fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define AUDIO_CLOCK_SEL_256FS	4L	/* 256*fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define AUDIO_CLOCK_SEL_512FS	5L	/* 512*fs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Page 0x20: EDID and Hotplug Detect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define REG_EDID_IN_BYTE0	0x2000 /* EDID base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define REG_EDID_IN_VERSION	0x2080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define REG_EDID_ENABLE		0x2081
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define REG_HPD_POWER		0x2084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define REG_HPD_AUTO_CTRL	0x2085
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define REG_HPD_DURATION	0x2086
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define REG_RX_HPD_HEAC		0x2087
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* EDID_ENABLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define EDID_ENABLE_NACK_OFF	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define EDID_ENABLE_EDID_ONLY	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define EDID_ENABLE_B_EN	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define EDID_ENABLE_A_EN	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* HPD Power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define HPD_POWER_BP_MASK	0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define HPD_POWER_BP_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define HPD_POWER_BP_LOW	0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define HPD_POWER_BP_HIGH	1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define HPD_POWER_EDID_ONLY	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* HPD Auto control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define HPD_AUTO_READ_EDID	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define HPD_AUTO_HPD_F3TECH	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define HPD_AUTO_HP_OTHER	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define HPD_AUTO_HPD_UNSEL	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define HPD_AUTO_HPD_ALL_CH	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define HPD_AUTO_HPD_PRV_CH	BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define HPD_AUTO_HPD_NEW_CH	BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Page 0x21 - EDID content */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define REG_EDID_IN_BYTE128	0x2100 /* CEA Extension block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define REG_EDID_IN_SPA_SUB	0x2180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define REG_EDID_IN_SPA_AB_A	0x2181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define REG_EDID_IN_SPA_CD_A	0x2182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define REG_EDID_IN_CKSUM_A	0x2183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define REG_EDID_IN_SPA_AB_B	0x2184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define REG_EDID_IN_SPA_CD_B	0x2185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define REG_EDID_IN_CKSUM_B	0x2186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Page 0x30 - NV Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define REG_RT_AUTO_CTRL	0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define REG_EQ_MAN_CTRL0	0x3001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define REG_EQ_MAN_CTRL1	0x3002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define REG_OUTPUT_CFG		0x3003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define REG_MUTE_CTRL		0x3004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define REG_SLAVE_ADDR		0x3005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define REG_CMTP_REG6		0x3006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define REG_CMTP_REG7		0x3007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define REG_CMTP_REG8		0x3008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define REG_CMTP_REG9		0x3009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define REG_CMTP_REGA		0x300A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define REG_CMTP_REGB		0x300B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define REG_CMTP_REGC		0x300C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define REG_CMTP_REGD		0x300D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define REG_CMTP_REGE		0x300E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define REG_CMTP_REGF		0x300F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define REG_CMTP_REG10		0x3010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define REG_CMTP_REG11		0x3011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* Page 0x80 - CEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define REG_PWR_CONTROL		0x80F4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define REG_OSC_DIVIDER		0x80F5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define REG_EN_OSC_PERIOD_LSB	0x80F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define REG_CONTROL		0x80FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* global interrupt flags (INT_FLG_CRL_TOP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define INTERRUPT_AFE		BIT(7) /* AFE module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define INTERRUPT_HDCP		BIT(6) /* HDCP module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define INTERRUPT_AUDIO		BIT(5) /* Audio module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define INTERRUPT_INFO		BIT(4) /* Infoframe module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define INTERRUPT_MODE		BIT(3) /* HDMI mode module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define INTERRUPT_RATE		BIT(2) /* rate module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define INTERRUPT_DDC		BIT(1) /* DDC module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define INTERRUPT_SUS		BIT(0) /* SUS module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* INT_FLG_CLR_HDCP bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define MASK_HDCP_MTP		BIT(7) /* HDCP MTP busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define MASK_HDCP_DLMTP		BIT(4) /* HDCP end download MTP to SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define MASK_HDCP_DLRAM		BIT(3) /* HDCP end download keys from SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define MASK_HDCP_ENC		BIT(2) /* HDCP ENC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define MASK_STATE_C5		BIT(1) /* HDCP State C5 reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define MASK_AKSV		BIT(0) /* AKSV received (start of auth) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* INT_FLG_CLR_RATE bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define MASK_RATE_B_DRIFT	BIT(7) /* Rate measurement drifted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define MASK_RATE_B_ST		BIT(6) /* Rate measurement stability change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define MASK_RATE_B_ACT		BIT(5) /* Rate measurement activity change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define MASK_RATE_B_PST		BIT(4) /* Rate measreument presence change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define MASK_RATE_A_DRIFT	BIT(3) /* Rate measurement drifted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define MASK_RATE_A_ST		BIT(2) /* Rate measurement stability change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define MASK_RATE_A_ACT		BIT(1) /* Rate measurement presence change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define MASK_RATE_A_PST		BIT(0) /* Rate measreument presence change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* INT_FLG_CLR_SUS (Start Up Sequencer) bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define MASK_MPT		BIT(7) /* Config MTP end of process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define MASK_FMT		BIT(5) /* Video format changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define MASK_RT_PULSE		BIT(4) /* End of termination resistance pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define MASK_SUS_END		BIT(3) /* SUS last state reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define MASK_SUS_ACT		BIT(2) /* Activity of selected input changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define MASK_SUS_CH		BIT(1) /* Selected input changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define MASK_SUS_ST		BIT(0) /* SUS state changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* INT_FLG_CLR_DDC bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define MASK_EDID_MTP		BIT(7) /* EDID MTP end of process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define MASK_DDC_ERR		BIT(6) /* master DDC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define MASK_DDC_CMD_DONE	BIT(5) /* master DDC cmd send correct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define MASK_READ_DONE		BIT(4) /* End of down EDID read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define MASK_RX_DDC_SW		BIT(3) /* Output DDC switching finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define MASK_HDCP_DDC_SW	BIT(2) /* HDCP DDC switching finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define MASK_HDP_PULSE_END	BIT(1) /* End of Hot Plug Detect pulse */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define MASK_DET_5V		BIT(0) /* Detection of +5V */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* INT_FLG_CLR_MODE bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define MASK_HDMI_FLG		BIT(7) /* HDMI mode/avmute/encrypt/FIFO fail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define MASK_GAMUT		BIT(6) /* Gamut packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define MASK_ISRC2		BIT(5) /* ISRC2 packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define MASK_ISRC1		BIT(4) /* ISRC1 packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define MASK_ACP		BIT(3) /* Audio Content Protection packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define MASK_DC_NO_GCP		BIT(2) /* GCP not received in 5 frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define MASK_DC_PHASE		BIT(1) /* deepcolor pixel phase needs update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define MASK_DC_MODE		BIT(0) /* deepcolor color depth changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* INT_FLG_CLR_INFO bits (Infoframe Change Status) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define MASK_MPS_IF		BIT(6) /* MPEG Source Product */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define MASK_AUD_IF		BIT(5) /* Audio */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define MASK_SPD_IF		BIT(4) /* Source Product Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define MASK_AVI_IF		BIT(3) /* Auxiliary Video IF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define MASK_VS_IF_OTHER_BK2	BIT(2) /* Vendor Specific (bank2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define MASK_VS_IF_OTHER_BK1	BIT(1) /* Vendor Specific (bank1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define MASK_VS_IF_HDMI		BIT(0) /* Vendor Specific (w/ HDMI LLC code) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* INT_FLG_CLR_AUDIO bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define MASK_AUDIO_FREQ_FLG	BIT(5) /* Audio freq change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define MASK_AUDIO_FLG		BIT(4) /* DST, OBA, HBR, ASP change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define MASK_MUTE_FLG		BIT(3) /* Audio Mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define MASK_CH_STATE		BIT(2) /* Channel status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define MASK_UNMUTE_FIFO	BIT(1) /* Audio Unmute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define MASK_ERROR_FIFO_PT	BIT(0) /* Audio FIFO pointer error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* INT_FLG_CLR_AFE bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define MASK_AFE_WDL_UNLOCKED	BIT(7) /* Wordlocker was unlocked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define MASK_AFE_GAIN_DONE	BIT(6) /* Gain calibration done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define MASK_AFE_OFFSET_DONE	BIT(5) /* Offset calibration done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define MASK_AFE_ACTIVITY_DET	BIT(4) /* Activity detected on data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define MASK_AFE_PLL_LOCK	BIT(3) /* TMDS PLL is locked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define MASK_AFE_TRMCAL_DONE	BIT(2) /* Termination calibration done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define MASK_AFE_ASU_STATE	BIT(1) /* ASU state is reached */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define MASK_AFE_ASU_READY	BIT(0) /* AFE calibration done: TMDS ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Audio Output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define AUDCFG_CLK_INVERT	BIT(7)	/* invert A_CLK polarity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define AUDCFG_TEST_TONE	BIT(6)	/* enable test tone generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define AUDCFG_BUS_SHIFT	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define AUDCFG_BUS_I2S		0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define AUDCFG_BUS_SPDIF	1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define AUDCFG_I2SW_SHIFT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define AUDCFG_I2SW_16		0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define AUDCFG_I2SW_32		1L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define AUDCFG_AUTO_MUTE_EN	BIT(3)	/* Enable Automatic audio mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define AUDCFG_HBR_SHIFT	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define AUDCFG_HBR_STRAIGHT	0L	/* straight via AP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define AUDCFG_HBR_DEMUX	1L	/* demuxed via AP0:AP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define AUDCFG_TYPE_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define AUDCFG_TYPE_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define AUDCFG_TYPE_DST		3L	/* Direct Stream Transfer (DST) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define AUDCFG_TYPE_OBA		2L	/* One Bit Audio (OBA) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define AUDCFG_TYPE_HBR		1L	/* High Bit Rate (HBR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define AUDCFG_TYPE_PCM		0L	/* Audio samples */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* Video Formatter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define OF_VP_ENABLE		BIT(7)	/* VP[35:0]/HS/VS/DE/CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define OF_BLK			BIT(4)	/* blanking codes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define OF_TRC			BIT(3)	/* timing codes (SAV/EAV) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define OF_FMT_MASK		0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define OF_FMT_444		0L	/* RGB444/YUV444 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define OF_FMT_422_SMPT		1L	/* YUV422 semi-planar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define OF_FMT_422_CCIR		2L	/* YUV422 CCIR656 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* HS/HREF output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define HS_HREF_DELAY_MASK	0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define HS_HREF_DELAY_SHIFT	4	/* Pixel delay (-8..+7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define HS_HREF_PXQ_SHIFT	3	/* Timing codes from HREF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define HS_HREF_INV_SHIFT	2	/* polarity (1=invert) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define HS_HREF_SEL_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define HS_HREF_SEL_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define HS_HREF_SEL_HS_VHREF	0L	/* HS from VHREF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define HS_HREF_SEL_HREF_VHREF	1L	/* HREF from VHREF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define HS_HREF_SEL_HREF_HDMI	2L	/* HREF from HDMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define HS_HREF_SEL_NONE	3L	/* not generated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* VS output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define VS_VREF_DELAY_MASK	0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define VS_VREF_DELAY_SHIFT	4	/* Pixel delay (-8..+7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define VS_VREF_INV_SHIFT	2	/* polarity (1=invert) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define VS_VREF_SEL_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define VS_VREF_SEL_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define VS_VREF_SEL_VS_VHREF	0L	/* VS from VHREF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define VS_VREF_SEL_VREF_VHREF	1L	/* VREF from VHREF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define VS_VREF_SEL_VREF_HDMI	2L	/* VREF from HDMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define VS_VREF_SEL_NONE	3L	/* not generated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* DE/FREF output control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define DE_FREF_DELAY_MASK	0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define DE_FREF_DELAY_SHIFT	4	/* Pixel delay (-8..+7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define DE_FREF_DE_PXQ_SHIFT	3	/* Timing codes from DE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define DE_FREF_INV_SHIFT	2	/* polarity (1=invert) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define DE_FREF_SEL_MASK	0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define DE_FREF_SEL_SHIFT	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define DE_FREF_SEL_DE_VHREF	0L	/* DE from VHREF (HREF and not(VREF) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define DE_FREF_SEL_FREF_VHREF	1L	/* FREF from VHREF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define DE_FREF_SEL_FREF_HDMI	2L	/* FREF from HDMI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define DE_FREF_SEL_NONE	3L	/* not generated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* HDMI_SOFT_RST bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define RESET_DC		BIT(7)	/* Reset deep color module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define RESET_HDCP		BIT(6)	/* Reset HDCP module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define RESET_KSV		BIT(5)	/* Reset KSV-FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define RESET_SCFG		BIT(4)	/* Reset HDCP and repeater function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define RESET_HCFG		BIT(3)	/* Reset HDCP DDC part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define RESET_PA		BIT(2)	/* Reset polarity adjust */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define RESET_EP		BIT(1)	/* Reset Error protection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define RESET_TMDS		BIT(0)	/* Reset TMDS (calib, encoding, flow) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* HDMI_INFO_RST bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define NACK_HDCP		BIT(7)	/* No ACK on HDCP request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define RESET_FIFO		BIT(4)	/* Reset Audio FIFO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define RESET_GAMUT		BIT(3)	/* Clear Gamut packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define RESET_AI		BIT(2)	/* Clear ACP and ISRC packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define RESET_IF		BIT(1)	/* Clear all Audio infoframe packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define RESET_AUDIO		BIT(0)	/* Reset Audio FIFO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* HDCP_BCAPS bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define HDCP_HDMI		BIT(7)	/* HDCP supports HDMI (vs DVI only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define HDCP_REPEATER		BIT(6)	/* HDCP supports repeater function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define HDCP_READY		BIT(5)	/* set by repeater function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define HDCP_FAST		BIT(4)	/* Up to 400kHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define HDCP_11			BIT(1)	/* HDCP 1.1 supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define HDCP_FAST_REAUTH	BIT(0)	/* fast reauthentication supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Audio output formatter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define AUDIO_LAYOUT_SP_FLAG	BIT(2)	/* sp flag used by FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define AUDIO_LAYOUT_MANUAL	BIT(1)	/* manual layout (vs per pkt) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define AUDIO_LAYOUT_LAYOUT1	BIT(0)  /* Layout1: AP0-3 vs Layout0:AP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* masks for interrupt status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define MASK_SUS_STATUS		0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define LAST_STATE_REACHED	0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define MASK_CLK_STABLE		0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define MASK_CLK_ACTIVE		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define MASK_SUS_STATE		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define MASK_SR_FIFO_FIFO_CTRL	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define MASK_AUDIO_FLAG		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Rate measurement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define RATE_REFTIM_ENABLE	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define CLK_MIN_RATE		0x0057e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define CLK_MAX_RATE		0x0395f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define WDL_CFG_VAL		0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define DC_FILTER_VAL		0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* Infoframe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define VS_HDMI_IF_UPDATE	0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define VS_HDMI_IF		0x0201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define VS_BK1_IF_UPDATE	0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define VS_BK1_IF		0x0221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define VS_BK2_IF_UPDATE	0x0240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define VS_BK2_IF		0x0241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define AVI_IF_UPDATE		0x0260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define AVI_IF			0x0261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define SPD_IF_UPDATE		0x0280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define SPD_IF			0x0281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define AUD_IF_UPDATE		0x02a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define AUD_IF			0x02a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define MPS_IF_UPDATE		0x02c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define MPS_IF			0x02c1