^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * tc35874x - Toshiba HDMI to CSI-2 bridge - register names and bit masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you may redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * the Free Software Foundation; version 2 of the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * References (c = chapter, p = page):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * REF_02 - Toshiba, TC358749XBG (H2C+), Functional Specification, Rev 0.74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Bit masks has prefix 'MASK_' and options after '_'. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifndef __TC35874X_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define __TC35874X_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CHIPID 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MASK_CHIPID 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MASK_REVID 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SYSCTL 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MASK_IRRST 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MASK_CECRST 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MASK_CTXRST 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MASK_HDMIRST 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MASK_I2SDIS 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MASK_SLEEP 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CONFCTL 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MASK_PWRISO 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MASK_ACLKOPT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MASK_AUDCHNUM 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MASK_AUDCHNUM_8 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MASK_AUDCHNUM_6 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MASK_AUDCHNUM_4 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MASK_AUDCHNUM_2 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MASK_AUDCHSEL 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MASK_I2SDLYOPT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MASK_YCBCRFMT 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MASK_YCBCRFMT_444 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MASK_YCBCRFMT_422_12_BIT 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MASK_YCBCRFMT_COLORBAR 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MASK_YCBCRFMT_422_8_BIT 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MASK_INFRMEN 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MASK_AUDOUTSEL 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MASK_AUDOUTSEL_CSI 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MASK_AUDOUTSEL_I2S 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MASK_AUDOUTSEL_TDM 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MASK_AUTOINDEX 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MASK_ABUFEN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MASK_VBUFEN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define FIFOCTL 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PACKETID1 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define FCCTL 0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define INTSTATUS 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MASK_AMUTE_INT 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MASK_HDMI_INT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MASK_CSI_INT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MASK_SYS_INT 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MASK_CEC_EINT 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MASK_CEC_TINT 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MASK_CEC_RINT 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MASK_IR_EINT 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MASK_IR_DINT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define INTMASK 0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MASK_AMUTE_MSK 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MASK_HDMI_MSK 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MASK_CSI_MSK 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MASK_SYS_MSK 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MASK_CEC_EMSK 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MASK_CEC_TMSK 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MASK_CEC_RMSK 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MASK_IR_EMSK 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MASK_IR_DMSK 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define INTFLAG 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define INTSYSSTATUS 0x001A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PLLCTL0 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MASK_PLL_PRD 0xf000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SET_PLL_PRD(prd) ((((prd) - 1) << 12) &\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) MASK_PLL_PRD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MASK_PLL_FBD 0x01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SET_PLL_FBD(fbd) (((fbd) - 1) & MASK_PLL_FBD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PLLCTL1 0x0022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MASK_PLL_FRS 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SET_PLL_FRS(frs) (((frs) << 10) & MASK_PLL_FRS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MASK_PLL_LBWS 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MASK_LFBREN 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MASK_BYPCKEN 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MASK_CKEN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MASK_RESETB 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MASK_PLL_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLW_CNTRL 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MASK_CLW_LANEDISABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define D0W_CNTRL 0x0144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MASK_D0W_LANEDISABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define D1W_CNTRL 0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MASK_D1W_LANEDISABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define D2W_CNTRL 0x014C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MASK_D2W_LANEDISABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define D3W_CNTRL 0x0150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MASK_D3W_LANEDISABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define STARTCNTRL 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MASK_START 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LINEINITCNT 0x0210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define LPTXTIMECNT 0x0214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TCLK_HEADERCNT 0x0218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TCLK_TRAILCNT 0x021C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define THS_HEADERCNT 0x0220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TWAKEUP 0x0224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TCLK_POSTCNT 0x0228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define THS_TRAILCNT 0x022C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HSTXVREGCNT 0x0230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HSTXVREGEN 0x0234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MASK_D3M_HSTXVREGEN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MASK_D2M_HSTXVREGEN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MASK_D1M_HSTXVREGEN 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MASK_D0M_HSTXVREGEN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MASK_CLM_HSTXVREGEN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TXOPTIONCNTRL 0x0238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MASK_CONTCLKMODE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CSI_CONTROL 0x040C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MASK_CSI_MODE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MASK_HTXTOEN 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MASK_TXHSMD 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MASK_HSCKMD 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MASK_NOL 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MASK_NOL_1 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MASK_NOL_2 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MASK_NOL_3 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MASK_NOL_4 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MASK_EOTDIS 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CSI_INT 0x0414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MASK_INTHLT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MASK_INTER 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CSI_INT_ENA 0x0418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MASK_IENHLT 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MASK_IENER 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CSI_ERR 0x044C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MASK_INER 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MASK_WCER 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MASK_QUNK 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MASK_TXBRK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CSI_ERR_INTENA 0x0450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CSI_ERR_HALT 0x0454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CSI_CONFW 0x0500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MASK_MODE 0xe0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MASK_MODE_SET 0xa0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MASK_MODE_CLEAR 0xc0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MASK_ADDRESS 0x1f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MASK_ADDRESS_CSI_CONTROL 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MASK_ADDRESS_CSI_INT_ENA 0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MASK_ADDRESS_CSI_ERR_INTENA 0x14000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MASK_ADDRESS_CSI_ERR_HALT 0x15000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MASK_DATA 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CSI_INT_CLR 0x050C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define MASK_ICRER 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CSI_START 0x0518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MASK_STRT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CECEN 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MASK_CECEN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define HDMI_INT0 0x8500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MASK_I_KEY 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MASK_I_MISC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MASK_I_PHYERR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define HDMI_INT1 0x8501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MASK_I_GBD 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MASK_I_HDCP 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MASK_I_ERR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MASK_I_AUD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MASK_I_CBIT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MASK_I_PACKET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MASK_I_CLK 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MASK_I_SYS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SYS_INT 0x8502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MASK_I_ACR_CTS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MASK_I_ACRN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MASK_I_DVI 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MASK_I_HDMI 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MASK_I_NOPMBDET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MASK_I_DPMBDET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MASK_I_TMDS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MASK_I_DDC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CLK_INT 0x8503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MASK_I_OUT_H_CHG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MASK_I_IN_DE_CHG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MASK_I_IN_HV_CHG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MASK_I_DC_CHG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MASK_I_PXCLK_CHG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MASK_I_PHYCLK_CHG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MASK_I_TMDSCLK_CHG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CBIT_INT 0x8505
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MASK_I_AF_LOCK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MASK_I_AF_UNLOCK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MASK_I_CBIT_FS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AUDIO_INT 0x8506
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ERR_INT 0x8507
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MASK_I_EESS_ERR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define HDCP_INT 0x8508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MASK_I_AVM_SET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MASK_I_AVM_CLR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MASK_I_LINKERR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MASK_I_SHA_END 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MASK_I_R0_END 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MASK_I_KM_END 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MASK_I_AKSV_END 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MASK_I_AN_END 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MISC_INT 0x850B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MASK_I_AS_LAYOUT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MASK_I_NO_SPD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MASK_I_NO_VS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MASK_I_SYNC_CHG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define MASK_I_AUDIO_MUTE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define KEY_INT 0x850F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SYS_INTM 0x8512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define MASK_M_ACR_CTS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MASK_M_ACR_N 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define MASK_M_DVI_DET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define MASK_M_HDMI_DET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define MASK_M_NOPMBDET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define MASK_M_BPMBDET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define MASK_M_TMDS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define MASK_M_DDC 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CLK_INTM 0x8513
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define MASK_M_OUT_H_CHG 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define MASK_M_IN_DE_CHG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define MASK_M_IN_HV_CHG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define MASK_M_DC_CHG 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define MASK_M_PXCLK_CHG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define MASK_M_PHYCLK_CHG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define MASK_M_TMDS_CHG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define PACKET_INTM 0x8514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CBIT_INTM 0x8515
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MASK_M_AF_LOCK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define MASK_M_AF_UNLOCK 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define MASK_M_CBIT_FS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define AUDIO_INTM 0x8516
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define MASK_M_BUFINIT_END 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ERR_INTM 0x8517
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define MASK_M_EESS_ERR 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define HDCP_INTM 0x8518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define MASK_M_AVM_SET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define MASK_M_AVM_CLR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define MASK_M_LINKERR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define MASK_M_SHA_END 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define MASK_M_R0_END 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define MASK_M_KM_END 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define MASK_M_AKSV_END 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define MASK_M_AN_END 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define MISC_INTM 0x851B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define MASK_M_AS_LAYOUT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MASK_M_NO_SPD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define MASK_M_NO_VS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define MASK_M_SYNC_CHG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define MASK_M_AUDIO_MUTE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define KEY_INTM 0x851F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define SYS_STATUS 0x8520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define MASK_S_SYNC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define MASK_S_AVMUTE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define MASK_S_HDCP 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define MASK_S_HDMI 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define MASK_S_PHY_SCDT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define MASK_S_PHY_PLL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define MASK_S_TMDS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define MASK_S_DDC5V 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CSI_STATUS 0x0410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define MASK_S_WSYNC 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define MASK_S_TXACT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define MASK_S_RXACT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define MASK_S_HLT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define VI_STATUS1 0x8522
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define MASK_S_V_GBD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define MASK_S_DEEPCOLOR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define MASK_S_V_422 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define MASK_S_V_INTERLACE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define AU_STATUS0 0x8523
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define MASK_S_A_SAMPLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define VI_STATUS3 0x8528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define MASK_S_V_COLOR 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define MASK_LIMITED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define PHY_CTL0 0x8531
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define MASK_PHY_SYSCLK_IND 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define MASK_PHY_CTL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define PHY_CTL1 0x8532 /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define MASK_PHY_AUTO_RST1 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define MASK_PHY_AUTO_RST1_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SET_PHY_AUTO_RST1_US(us) ((((us) / 200) << 4) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) MASK_PHY_AUTO_RST1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define MASK_FREQ_RANGE_MODE 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define SET_FREQ_RANGE_MODE_CYCLES(cycles) (((cycles) - 1) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MASK_FREQ_RANGE_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define PHY_CTL2 0x8533 /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define MASK_PHY_AUTO_RST4 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define MASK_PHY_AUTO_RST3 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define MASK_PHY_AUTO_RST2 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define MASK_PHY_AUTO_RSTn (MASK_PHY_AUTO_RST4 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) MASK_PHY_AUTO_RST3 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) MASK_PHY_AUTO_RST2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define PHY_EN 0x8534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define MASK_ENABLE_PHY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define PHY_RST 0x8535
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define MASK_RESET_CTRL 0x01 /* Reset active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define PHY_BIAS 0x8536 /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define PHY_CSQ 0x853F /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define MASK_CSQ_CNT 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SET_CSQ_CNT_LEVEL(n) (n & MASK_CSQ_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SYS_FREQ0 0x8540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SYS_FREQ1 0x8541
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SYS_CLK 0x8542 /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define MASK_CLK_DIFF 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define MASK_CLK_DIV 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define DDC_CTL 0x8543
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define MASK_DDC_ACK_POL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define MASK_DDC_ACTION 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define MASK_DDC5V_MODE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define MASK_DDC5V_MODE_0MS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define MASK_DDC5V_MODE_50MS 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define MASK_DDC5V_MODE_100MS 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define MASK_DDC5V_MODE_200MS 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define HPD_CTL 0x8544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define MASK_HPD_CTL0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define MASK_HPD_OUT0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define ANA_CTL 0x8545
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define MASK_APPL_PCSX 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define MASK_APPL_PCSX_HIZ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define MASK_APPL_PCSX_L_FIX 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define MASK_APPL_PCSX_H_FIX 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define MASK_APPL_PCSX_NORMAL 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define MASK_ANALOG_ON 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define AVM_CTL 0x8546
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define INIT_END 0x854A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define MASK_INIT_END 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define HDMI_DET 0x8552 /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define MASK_HDMI_DET_MOD1 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define MASK_HDMI_DET_MOD0 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define MASK_HDMI_DET_V 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define MASK_HDMI_DET_V_SYNC 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define MASK_HDMI_DET_V_ASYNC_25MS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define MASK_HDMI_DET_V_ASYNC_50MS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define MASK_HDMI_DET_V_ASYNC_100MS 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define MASK_HDMI_DET_NUM 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define HDCP_MODE 0x8560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define MASK_MODE_RST_TN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define MASK_LINE_REKEY 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define MASK_AUTO_CLR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define MASK_MANUAL_AUTHENTICATION 0x02 /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define HDCP_REG1 0x8563 /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define MASK_AUTH_UNAUTH_SEL 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define MASK_AUTH_UNAUTH_SEL_12_FRAMES 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define MASK_AUTH_UNAUTH_SEL_8_FRAMES 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define MASK_AUTH_UNAUTH_SEL_4_FRAMES 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define MASK_AUTH_UNAUTH_SEL_2_FRAMES 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define MASK_AUTH_UNAUTH_SEL_64_FRAMES 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define MASK_AUTH_UNAUTH_SEL_32_FRAMES 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define MASK_AUTH_UNAUTH_SEL_16_FRAMES 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define MASK_AUTH_UNAUTH_SEL_ONCE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define MASK_AUTH_UNAUTH 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define MASK_AUTH_UNAUTH_AUTO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define HDCP_REG2 0x8564 /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define MASK_AUTO_P3_RESET 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define SET_AUTO_P3_RESET_FRAMES(n) (n & MASK_AUTO_P3_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define MASK_AUTO_P3_RESET_OFF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define VI_MODE 0x8570
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define MASK_RGB_DVI 0x08 /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define VOUT_SET2 0x8573
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define MASK_SEL422 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define MASK_VOUT_422FIL_100 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define MASK_VOUTCOLORMODE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define MASK_VOUTCOLORMODE_THROUGH 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define MASK_VOUTCOLORMODE_AUTO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define MASK_VOUTCOLORMODE_MANUAL 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define VOUT_SET3 0x8574
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define MASK_VOUT_EXTCNT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define VI_REP 0x8576
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define MASK_VOUT_COLOR_SEL 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define MASK_VOUT_COLOR_RGB_FULL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define MASK_VOUT_COLOR_RGB_LIMITED 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define MASK_VOUT_COLOR_601_YCBCR_FULL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define MASK_VOUT_COLOR_601_YCBCR_LIMITED 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define MASK_VOUT_COLOR_709_YCBCR_FULL 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define MASK_VOUT_COLOR_709_YCBCR_LIMITED 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define MASK_VOUT_COLOR_FULL_TO_LIMITED 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define MASK_VOUT_COLOR_LIMITED_TO_FULL 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define MASK_IN_REP_HEN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define MASK_IN_REP 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define VI_MUTE 0x857F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define MASK_AUTO_MUTE 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define MASK_VI_MUTE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define DE_WIDTH_H_LO 0x8582 /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define DE_WIDTH_H_HI 0x8583 /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define DE_WIDTH_V_LO 0x8588 /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define DE_WIDTH_V_HI 0x8589 /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define H_SIZE_LO 0x858A /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define H_SIZE_HI 0x858B /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define V_SIZE_LO 0x858C /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define V_SIZE_HI 0x858D /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define FV_CNT_LO 0x85A1 /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define FV_CNT_HI 0x85A2 /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define FH_MIN0 0x85AA /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define FH_MIN1 0x85AB /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define FH_MAX0 0x85AC /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define FH_MAX1 0x85AD /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define HV_RST 0x85AF /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define MASK_H_PI_RST 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define MASK_V_PI_RST 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define EDID_MODE 0x85C7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define MASK_EDID_SPEED 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define MASK_EDID_MODE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define MASK_EDID_MODE_DISABLE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define MASK_EDID_MODE_DDC2B 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define MASK_EDID_MODE_E_DDC 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define EDID_LEN1 0x85CA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define EDID_LEN2 0x85CB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define HDCP_REG3 0x85D1 /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define KEY_RD_CMD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define FORCE_MUTE 0x8600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define MASK_FORCE_AMUTE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define MASK_FORCE_DMUTE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define CMD_AUD 0x8601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define MASK_CMD_BUFINIT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define MASK_CMD_LOCKDET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define MASK_CMD_MUTE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define AUTO_CMD0 0x8602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define MASK_AUTO_MUTE7 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define MASK_AUTO_MUTE6 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define MASK_AUTO_MUTE5 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define MASK_AUTO_MUTE4 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define MASK_AUTO_MUTE3 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define MASK_AUTO_MUTE2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define MASK_AUTO_MUTE1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define MASK_AUTO_MUTE0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define AUTO_CMD1 0x8603
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define MASK_AUTO_MUTE10 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define MASK_AUTO_MUTE9 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define MASK_AUTO_MUTE8 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define AUTO_CMD2 0x8604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define MASK_AUTO_PLAY3 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define MASK_AUTO_PLAY2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define BUFINIT_START 0x8606
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define SET_BUFINIT_START_MS(milliseconds) ((milliseconds) / 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define FS_MUTE 0x8607
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define MASK_FS_ELSE_MUTE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define MASK_FS22_MUTE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define MASK_FS24_MUTE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define MASK_FS88_MUTE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define MASK_FS96_MUTE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define MASK_FS176_MUTE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define MASK_FS192_MUTE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define MASK_FS_NO_MUTE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define FS_IMODE 0x8620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define MASK_NLPCM_HMODE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define MASK_NLPCM_SMODE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define MASK_NLPCM_IMODE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define MASK_FS_HMODE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define MASK_FS_AMODE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define MASK_FS_SMODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define MASK_FS_IMODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define FS_SET 0x8621
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define MASK_FS 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define LOCKDET_REF0 0x8630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define LOCKDET_REF1 0x8631
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define LOCKDET_REF2 0x8632
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define ACR_MODE 0x8640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define MASK_ACR_LOAD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define MASK_N_MODE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define MASK_CTS_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define ACR_MDF0 0x8641
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define MASK_ACR_L2MDF 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define MASK_ACR_L2MDF_0_PPM 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define MASK_ACR_L2MDF_61_PPM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define MASK_ACR_L2MDF_122_PPM 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define MASK_ACR_L2MDF_244_PPM 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define MASK_ACR_L2MDF_488_PPM 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define MASK_ACR_L2MDF_976_PPM 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define MASK_ACR_L2MDF_1976_PPM 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define MASK_ACR_L2MDF_3906_PPM 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define MASK_ACR_L1MDF 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define MASK_ACR_L1MDF_0_PPM 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define MASK_ACR_L1MDF_61_PPM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define MASK_ACR_L1MDF_122_PPM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define MASK_ACR_L1MDF_244_PPM 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define MASK_ACR_L1MDF_488_PPM 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define MASK_ACR_L1MDF_976_PPM 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define MASK_ACR_L1MDF_1976_PPM 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define MASK_ACR_L1MDF_3906_PPM 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define ACR_MDF1 0x8642
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define MASK_ACR_L3MDF 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define MASK_ACR_L3MDF_0_PPM 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define MASK_ACR_L3MDF_61_PPM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define MASK_ACR_L3MDF_122_PPM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define MASK_ACR_L3MDF_244_PPM 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define MASK_ACR_L3MDF_488_PPM 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define MASK_ACR_L3MDF_976_PPM 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define MASK_ACR_L3MDF_1976_PPM 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define MASK_ACR_L3MDF_3906_PPM 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define SDO_MODE1 0x8652
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define MASK_SDO_BIT_LENG 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define MASK_SDO_FMT 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define MASK_SDO_FMT_RIGHT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define MASK_SDO_FMT_LEFT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define MASK_SDO_FMT_I2S 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define DIV_MODE 0x8665 /* Not in REF_01 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define MASK_DIV_DLY 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define SET_DIV_DLY_MS(milliseconds) ((((milliseconds) / 100) << 4) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) MASK_DIV_DLY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define MASK_DIV_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define NCO_F0_MOD 0x8670
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define MASK_NCO_F0_MOD 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define MASK_NCO_F0_MOD_42MHZ 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define MASK_NCO_F0_MOD_27MHZ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define PK_INT_MODE 0x8709
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define MASK_ISRC2_INT_MODE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define MASK_ISRC_INT_MODE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define MASK_ACP_INT_MODE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define MASK_VS_INT_MODE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define MASK_SPD_INT_MODE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define MASK_MS_INT_MODE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define MASK_AUD_INT_MODE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define MASK_AVI_INT_MODE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define NO_PKT_LIMIT 0x870B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define MASK_NO_ACP_LIMIT 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define SET_NO_ACP_LIMIT_MS(milliseconds) ((((milliseconds) / 80) << 4) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) MASK_NO_ACP_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define MASK_NO_AVI_LIMIT 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define SET_NO_AVI_LIMIT_MS(milliseconds) (((milliseconds) / 80) & \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MASK_NO_AVI_LIMIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define NO_PKT_CLR 0x870C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define MASK_NO_VS_CLR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define MASK_NO_SPD_CLR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define MASK_NO_ACP_CLR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define MASK_NO_AVI_CLR1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define MASK_NO_AVI_CLR0 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define ERR_PK_LIMIT 0x870D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define NO_PKT_LIMIT2 0x870E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define PK_AVI_0HEAD 0x8710
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define PK_AVI_1HEAD 0x8711
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define PK_AVI_2HEAD 0x8712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define PK_AVI_0BYTE 0x8713
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define PK_AVI_1BYTE 0x8714
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define PK_AVI_2BYTE 0x8715
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define PK_AVI_3BYTE 0x8716
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define PK_AVI_4BYTE 0x8717
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define PK_AVI_5BYTE 0x8718
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define PK_AVI_6BYTE 0x8719
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define PK_AVI_7BYTE 0x871A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define PK_AVI_8BYTE 0x871B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define PK_AVI_9BYTE 0x871C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define PK_AVI_10BYTE 0x871D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define PK_AVI_11BYTE 0x871E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define PK_AVI_12BYTE 0x871F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define PK_AVI_13BYTE 0x8720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define PK_AVI_14BYTE 0x8721
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define PK_AVI_15BYTE 0x8722
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define PK_AVI_16BYTE 0x8723
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define BKSV 0x8800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define BCAPS 0x8840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define MASK_HDMI_RSVD 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define MASK_REPEATER 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define MASK_READY 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define MASK_FASTI2C 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define MASK_1_1_FEA 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define MASK_FAST_REAU 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define BSTATUS1 0x8842
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define MASK_MAX_EXCED 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define EDID_RAM 0x8C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define EDID_EXT_RAM 0x8c80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define NO_GDB_LIMIT 0x9007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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