^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * tc35874x - Toshiba HDMI to CSI-2 bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This program is free software; you may redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * the Free Software Foundation; version 2 of the License.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * References (c = chapter, p = page):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * REF_02 - Toshiba, TC358749XBG (H2C+), Functional Specification, Rev 0.74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/hdmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/compat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #include <media/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #include <media/tc35874x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include "tc35874x_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MODULE_PARM_DESC(debug, "debug level (0-3)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MODULE_DESCRIPTION("Toshiba TC35874X HDMI to CSI-2 bridge driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define EDID_NUM_BLOCKS_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define EDID_BLOCK_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define I2C_MAX_XFER_SIZE (EDID_BLOCK_SIZE + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define POLL_INTERVAL_CEC_MS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define POLL_INTERVAL_MS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* PIXEL_RATE = MIPI_FREQ * 2 * lane / 8bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TC35874X_LINK_FREQ_310MHZ 310000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TC35874X_PIXEL_RATE_310M TC35874X_LINK_FREQ_310MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TC35874X_NAME "tc35874x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) TC35874X_LINK_FREQ_310MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static const struct v4l2_dv_timings_cap tc35874x_timings_cap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .type = V4L2_DV_BT_656_1120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* keep this initialization for compatibility with GCC < 4.4.6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) .reserved = { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) V4L2_INIT_BT_TIMINGS(1, 10000, 1, 10000, 0, 310000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) V4L2_DV_BT_CAP_PROGRESSIVE | V4L2_DV_BT_CAP_INTERLACED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) V4L2_DV_BT_CAP_REDUCED_BLANKING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) V4L2_DV_BT_CAP_CUSTOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) static u8 EDID_1920x1080_60[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 0x52, 0x62, 0x01, 0x88, 0x00, 0x88, 0x88, 0x88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 0x1C, 0x15, 0x01, 0x03, 0x80, 0x00, 0x00, 0x78,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 0x0A, 0x0D, 0xC9, 0xA0, 0x57, 0x47, 0x98, 0x27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 0x12, 0x48, 0x4C, 0x00, 0x00, 0x00, 0x01, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x02, 0x3A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40, 0x58, 0x2C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 0x45, 0x00, 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x1E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 0x01, 0x1D, 0x00, 0x72, 0x51, 0xD0, 0x1E, 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 0x6E, 0x28, 0x55, 0x00, 0xC4, 0x8E, 0x21, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 0x00, 0x1E, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x54,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 0x37, 0x34, 0x39, 0x2D, 0x66, 0x48, 0x44, 0x37,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 0x32, 0x30, 0x0A, 0x20, 0x00, 0x00, 0x00, 0xFD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 0x00, 0x14, 0x78, 0x01, 0xFF, 0x1D, 0x00, 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x01, 0x7B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static u8 EDID_extend[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 0x02, 0x03, 0x1A, 0x71, 0x47, 0x90, 0x04, 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 0x01, 0x11, 0x22, 0x05, 0x23, 0x09, 0x07, 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 0x83, 0x01, 0x00, 0x00, 0x65, 0x03, 0x0C, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 0x10, 0x00, 0x8C, 0x0A, 0xD0, 0x8A, 0x20, 0xE0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 0x2D, 0x10, 0x10, 0x3E, 0x96, 0x00, 0x13, 0x8E,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 0x21, 0x00, 0x00, 0x1E, 0xD8, 0x09, 0x80, 0xA0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 0x20, 0xE0, 0x2D, 0x10, 0x10, 0x60, 0xA2, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 0xC4, 0x8E, 0x21, 0x00, 0x00, 0x18, 0x8C, 0x0A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 0xD0, 0x90, 0x20, 0x40, 0x31, 0x20, 0x0C, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 0x55, 0x00, 0x48, 0x39, 0x00, 0x00, 0x00, 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 0x01, 0x1D, 0x80, 0x18, 0x71, 0x38, 0x2D, 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 0x58, 0x2C, 0x45, 0x00, 0xC0, 0x6C, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 0x00, 0x18, 0x01, 0x1D, 0x80, 0x18, 0x71, 0x1C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 0x16, 0x20, 0x58, 0x2C, 0x25, 0x00, 0xC0, 0x6C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct tc35874x_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct tc35874x_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .exp_def = 0x470,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .hts_def = 0x898,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .vts_def = 0x465,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .height = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .exp_def = 0x2f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .hts_def = 0x672,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .vts_def = 0x2ee,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .width = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .height = 576,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .denominator = 500000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) .exp_def = 0x275,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) .hts_def = 0x360,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .vts_def = 0x271,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .width = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .exp_def = 0x210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .hts_def = 0x35a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .vts_def = 0x20d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct tc35874x_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct tc35874x_platform_data pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct v4l2_fwnode_bus_mipi_csi2 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct i2c_client *i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* CONFCTL is modified in ops and tc35874x_hdmi_sys_int_handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct mutex confctl_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct v4l2_ctrl *detect_tx_5v_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct v4l2_ctrl *audio_sampling_rate_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct v4l2_ctrl *audio_present_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct delayed_work delayed_work_enable_hotplug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct work_struct work_i2c_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* edid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u8 edid_blocks_written;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 mbus_fmt_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u8 csi_lanes_in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct cec_adapter *cec_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) const struct tc35874x_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static void tc35874x_enable_interrupts(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) bool cable_connected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int tc35874x_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static int tc35874x_s_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct v4l2_dv_timings *timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static inline struct tc35874x_state *to_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return container_of(sd, struct tc35874x_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* --------------- I2C --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct i2c_client *client = state->i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u8 buf[2] = { reg >> 8, reg & 0xff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct i2c_msg msgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .buf = buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .len = n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) .buf = values,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (err != ARRAY_SIZE(msgs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) __func__, reg, client->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct i2c_client *client = state->i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u8 data[I2C_MAX_XFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if ((2 + n) > I2C_MAX_XFER_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) n = I2C_MAX_XFER_SIZE - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) reg, 2 + n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) msg.buf = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) msg.len = 2 + n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) msg.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) data[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) data[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) for (i = 0; i < n; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) data[2 + i] = values[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) err = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (err != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) __func__, reg, client->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (debug < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) switch (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) v4l2_info(sd, "I2C write 0x%04x = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) reg, data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) reg, data[3], data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) reg, data[5], data[4], data[3], data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) n, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) __le32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) i2c_rd(sd, reg, (u8 __force *)&val, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return le32_to_cpu(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) __le32 raw = cpu_to_le32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) i2c_wr(sd, reg, (u8 __force *)&raw, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return i2c_rdreg(sd, reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) i2c_wrreg(sd, reg, val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return i2c_rdreg(sd, reg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) i2c_wrreg(sd, reg, val, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) return i2c_rdreg(sd, reg, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) i2c_wrreg(sd, reg, val, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* --------------- STATUS --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static inline bool is_hdmi(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static inline bool no_signal(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static inline bool no_sync(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static inline bool audio_present(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int get_audio_sampling_rate(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static const int code_to_rate[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Register FS_SET is not cleared when the cable is disconnected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (no_signal(sd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* --------------- TIMINGS --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static inline unsigned fps(const struct v4l2_bt_timings *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int tc35874x_get_detected_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct v4l2_bt_timings *bt = &timings->bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned width, height, frame_width, frame_height, frame_interval, fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u16 fifo_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) memset(timings, 0, sizeof(struct v4l2_dv_timings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (no_signal(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return -ENOLINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (no_sync(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return -ENOLCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) timings->type = V4L2_DV_BT_656_1120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) i2c_rd8(sd, DE_WIDTH_H_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) i2c_rd8(sd, DE_WIDTH_V_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) i2c_rd8(sd, H_SIZE_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) i2c_rd8(sd, V_SIZE_LO)) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* frame interval in milliseconds * 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) i2c_rd8(sd, FV_CNT_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) fps = (frame_interval > 0) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) bt->width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) bt->height = height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) bt->vsync = frame_height - height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) bt->hsync = frame_width - width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) bt->pixelclock = frame_width * frame_height * fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (bt->interlaced == V4L2_DV_INTERLACED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) bt->height *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) bt->il_vsync = bt->vsync + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) bt->pixelclock /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* frame count number: FS = FE 1,2,1,2... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) i2c_wr16(sd, FCCTL, 0x0002);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* packet id for interlace mode only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) i2c_wr16(sd, PACKETID1, 0x1e1e);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) i2c_wr16(sd, FCCTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) if (state->csi_lanes_in_use == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if ((width == 1920 && height == 1080) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) (width == 1280 && height == 720)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) fifo_level = 370;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) } else if ((width == 720 && height == 576) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) (width == 720 && height == 480)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) fifo_level = 350;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) fifo_level = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if ((bt->interlaced == V4L2_DV_INTERLACED) || (fps <= 33))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) fifo_level = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) v4l2_dbg(2, debug, sd, "%s interlaced:%d, fifo_level:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) __func__, bt->interlaced, fifo_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) i2c_wr16(sd, FIFOCTL, fifo_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* --------------- HOTPLUG / HDCP / EDID --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static void tc35874x_delayed_work_enable_hotplug(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) struct delayed_work *dwork = to_delayed_work(work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct tc35874x_state *state = container_of(dwork,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct tc35874x_state, delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct v4l2_subdev *sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) v4l2_dbg(2, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static void tc35874x_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) "enable" : "disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, KEY_RD_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) i2c_wr8_and_or(sd, HDCP_REG1, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) MASK_AUTH_UNAUTH_SEL_16_FRAMES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) MASK_AUTH_UNAUTH_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) SET_AUTO_P3_RESET_FRAMES(0x0f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) MASK_MANUAL_AUTHENTICATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static void tc35874x_disable_edid(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) v4l2_dbg(2, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* DDC access to EDID is also disabled when hotplug is disabled. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * register DDC_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static void tc35874x_enable_edid(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (state->edid_blocks_written == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) tc35874x_s_ctrl_detect_tx_5v(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) v4l2_dbg(2, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * hotplug is enabled. See register DDC_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) tc35874x_enable_interrupts(sd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) tc35874x_s_ctrl_detect_tx_5v(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static void tc35874x_erase_bksv(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) for (i = 0; i < 5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) i2c_wr8(sd, BKSV + i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* --------------- AVI infoframe --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static void print_avi_infoframe(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) union hdmi_infoframe frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!is_hdmi(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) hdmi_infoframe_log(KERN_INFO, dev, &frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* --------------- CTRLS --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static int tc35874x_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) tx_5v_power_present(sd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static int tc35874x_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) get_audio_sampling_rate(sd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int tc35874x_s_ctrl_audio_present(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) audio_present(sd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int tc35874x_update_controls(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ret |= tc35874x_s_ctrl_detect_tx_5v(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ret |= tc35874x_s_ctrl_audio_sampling_rate(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ret |= tc35874x_s_ctrl_audio_present(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* --------------- INIT --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static void tc35874x_reset_phy(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) v4l2_dbg(1, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static void tc35874x_reset(struct v4l2_subdev *sd, uint16_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u16 sysctl = i2c_rd16(sd, SYSCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) i2c_wr16(sd, SYSCTL, sysctl | mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) i2c_wr16(sd, SYSCTL, sysctl & ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static inline void tc35874x_sleep_mode(struct v4l2_subdev *sd, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) enable ? MASK_SLEEP : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) v4l2_dbg(3, debug, sd, "%s: %sable\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) __func__, enable ? "en" : "dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* It is critical for CSI receiver to see lane transition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * LP11->HS. Set to non-continuous mode to enable clock lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) * LP11 state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) i2c_wr32(sd, TXOPTIONCNTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* Set to continuous mode to trigger LP11->HS transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Unmute video */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /* Mute video so that all data lanes go to LSP11 state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * No data is output to CSI Tx block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /* Set to non-continuous mode to enable clock lane LP11 state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) i2c_wr32(sd, TXOPTIONCNTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) mutex_lock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) mutex_unlock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static void tc35874x_set_pll(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct tc35874x_platform_data *pdata = &state->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u16 pllctl1 = i2c_rd16(sd, PLLCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) u16 pllctl0_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) u32 hsck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) u16 pll_frs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (state->csi_lanes_in_use == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if ((state->timings.bt.interlaced) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) (fps(&(state->timings.bt)) <= 33)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) pdata->pll_prd = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) pdata->pll_fbd = 65;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) pll_frs = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) pdata->pll_prd = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) pdata->pll_fbd = 138;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) pll_frs = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (state->timings.bt.interlaced)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) hsck /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (hsck > 500000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) pll_frs = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) else if (hsck > 250000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) pll_frs = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) else if (hsck > 125000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) pll_frs = 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) pll_frs = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) pllctl0_new = SET_PLL_PRD(pdata->pll_prd) | SET_PLL_FBD(pdata->pll_fbd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "%s: prd:%d, fbd:%d, frs:%d, interlaced:%d, fps:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) __func__, pdata->pll_prd, pdata->pll_fbd, pll_frs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) state->timings.bt.interlaced, fps(&(state->timings.bt)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) /* Only rewrite when needed (new value or disabled), since rewriting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * triggers another format change event. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (pllctl0 != pllctl0_new || (pllctl1 & MASK_PLL_EN) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) SET_PLL_FRS(pll_frs) != (pllctl1 & MASK_PLL_FRS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) tc35874x_sleep_mode(sd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) i2c_wr16(sd, PLLCTL0, pllctl0_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) i2c_wr16_and_or(sd, PLLCTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) (SET_PLL_FRS(pll_frs) | MASK_RESETB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) MASK_PLL_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) udelay(10); /* REF_02, Sheet "Source HDMI" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) tc35874x_sleep_mode(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static void tc35874x_set_ref_clk(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct tc35874x_platform_data *pdata = &state->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u32 sys_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) u32 lockdet_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) u16 fh_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u16 fh_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) BUG_ON(!(pdata->refclk_hz == 26000000 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) pdata->refclk_hz == 27000000 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) pdata->refclk_hz == 42000000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) sys_freq = pdata->refclk_hz / 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) (pdata->refclk_hz == 42000000) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) MASK_PHY_SYSCLK_IND : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) fh_min = pdata->refclk_hz / 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) fh_max = (fh_min * 66) / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) lockdet_ref = pdata->refclk_hz / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) (pdata->refclk_hz == 27000000) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) MASK_NCO_F0_MOD_27MHZ : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static void tc35874x_set_csi_color_space(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) switch (state->mbus_fmt_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) case MEDIA_BUS_FMT_UYVY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) i2c_wr8_and_or(sd, VOUT_SET2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) MASK_SEL422 | MASK_VOUT_422FIL_100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) MASK_VOUT_COLOR_601_YCBCR_LIMITED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) mutex_lock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) MASK_YCBCRFMT_422_8_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) mutex_unlock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) case MEDIA_BUS_FMT_RGB888_1X24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) i2c_wr8_and_or(sd, VOUT_SET2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) MASK_VOUT_COLOR_RGB_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) mutex_lock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) mutex_unlock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) __func__, state->mbus_fmt_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static void tc35874x_set_csi(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct tc35874x_platform_data *pdata = &state->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) unsigned lanes = state->csi_lanes_in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) v4l2_dbg(3, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) tc35874x_reset(sd, MASK_CTXRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (lanes < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (lanes < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (lanes < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (lanes < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (lanes < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) v4l2_dbg(1, debug, sd, "%s: interlaced:%d, fps:%d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) state->timings.bt.interlaced, fps(&(state->timings.bt)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (state->csi_lanes_in_use == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if ((state->timings.bt.interlaced) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) (fps(&(state->timings.bt)) <= 33)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) state->pdata.lineinitcnt = 0x7d0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) state->pdata.lptxtimecnt = 0x002;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) state->pdata.tclk_headercnt = 0x901;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) state->pdata.tclk_trailcnt = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) state->pdata.ths_headercnt = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) state->pdata.twakeup = 0x32c8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) state->pdata.tclk_postcnt = 0x006;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) state->pdata.ths_trailcnt = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) state->pdata.hstxvregcnt = 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) state->pdata.lineinitcnt = 0x1770;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) state->pdata.lptxtimecnt = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) state->pdata.tclk_headercnt = 0x1505;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) state->pdata.tclk_trailcnt = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) state->pdata.ths_headercnt = 0x0105;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) state->pdata.twakeup = 0x332c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) state->pdata.tclk_postcnt = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) state->pdata.ths_trailcnt = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) state->pdata.hstxvregcnt = 0x05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) i2c_wr32(sd, TWAKEUP, pdata->twakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) i2c_wr32(sd, HSTXVREGEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) i2c_wr32(sd, STARTCNTRL, MASK_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) i2c_wr32(sd, CSI_START, MASK_STRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) MASK_ADDRESS_CSI_CONTROL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) MASK_CSI_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) MASK_TXHSMD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ((lanes == 4) ? MASK_NOL_4 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) (lanes == 3) ? MASK_NOL_3 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) MASK_WCER | MASK_INER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static void tc35874x_set_hdmi_phy(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct tc35874x_platform_data *pdata = &state->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /* Default settings from REF_02, sheet "Source HDMI"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * and custom settings as platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) SET_FREQ_RANGE_MODE_CYCLES(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) (pdata->hdmi_phy_auto_reset_tmds_detected ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) MASK_PHY_AUTO_RST2 : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) (pdata->hdmi_phy_auto_reset_tmds_in_range ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) MASK_PHY_AUTO_RST3 : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) (pdata->hdmi_phy_auto_reset_tmds_valid ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) MASK_PHY_AUTO_RST4 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) i2c_wr8(sd, PHY_BIAS, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) i2c_wr8(sd, AVM_CTL, 45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) pdata->hdmi_detection_delay << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) (pdata->hdmi_phy_auto_reset_hsync_out_of_range ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) MASK_H_PI_RST : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) (pdata->hdmi_phy_auto_reset_vsync_out_of_range ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) MASK_V_PI_RST : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static void tc35874x_set_hdmi_audio(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* Default settings from REF_02, sheet "Source HDMI" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) i2c_wr8(sd, FORCE_MUTE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) i2c_wr8(sd, FS_MUTE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) mutex_lock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) mutex_unlock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static void tc35874x_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* Default settings from REF_02, sheet "Source HDMI" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) i2c_wr8(sd, NO_PKT_CLR, 0x53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static void tc35874x_initial_setup(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct tc35874x_platform_data *pdata = &state->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* CEC and IR are not supported by this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) i2c_wr16_and_or(sd, SYSCTL, ~(MASK_CECRST | MASK_IRRST | MASK_I2SDIS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) (MASK_CECRST | MASK_IRRST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) tc35874x_reset(sd, MASK_CTXRST | MASK_HDMIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) tc35874x_sleep_mode(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) tc35874x_set_ref_clk(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) pdata->ddc5v_delay & MASK_DDC5V_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) tc35874x_set_hdmi_phy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) tc35874x_set_hdmi_hdcp(sd, pdata->enable_hdcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) tc35874x_set_hdmi_audio(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) tc35874x_set_hdmi_info_frame_mode(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /* All CE and IT formats are detected as RGB full range in DVI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) MASK_VOUTCOLORMODE_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) /* --------------- IRQ --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) static void tc35874x_format_change(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) const struct v4l2_event tc35874x_ev_fmt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .type = V4L2_EVENT_SOURCE_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (tc35874x_get_detected_timings(sd, &timings)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) enable_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) v4l2_dbg(1, debug, sd, "%s: No signal\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) enable_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* automaticly set timing rather than set by userspace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) tc35874x_s_dv_timings(sd, &timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) v4l2_print_dv_timings(sd->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) "tc35874x_format_change: New format: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) &timings, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (sd->devnode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) v4l2_subdev_notify_event(sd, &tc35874x_ev_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static void tc35874x_init_interrupts(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) u16 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* clear interrupt status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) for (i = SYS_INT; i <= KEY_INT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) i2c_wr8(sd, i, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) i2c_wr16(sd, INTSTATUS, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static void tc35874x_enable_interrupts(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) bool cable_connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) cable_connected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (cable_connected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) MASK_M_HDMI_DET) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) MASK_M_AF_UNLOCK) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) i2c_wr8(sd, CLK_INTM, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) i2c_wr8(sd, CBIT_INTM, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) i2c_wr8(sd, AUDIO_INTM, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) i2c_wr8(sd, MISC_INTM, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static void tc35874x_hdmi_audio_int_handler(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) i2c_wr8(sd, AUDIO_INT, audio_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) tc35874x_s_ctrl_audio_sampling_rate(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) tc35874x_s_ctrl_audio_present(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static void tc35874x_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static void tc35874x_hdmi_misc_int_handler(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) i2c_wr8(sd, MISC_INT, misc_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (misc_int & MASK_I_SYNC_CHG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* Reset the HDMI PHY to try to trigger proper lock on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * incoming video format. Erase BKSV to prevent that old keys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * are used when a new source is connected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (no_sync(sd) || no_signal(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) tc35874x_reset_phy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) tc35874x_erase_bksv(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) tc35874x_format_change(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) misc_int &= ~MASK_I_SYNC_CHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (misc_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) __func__, misc_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static void tc35874x_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) i2c_wr8(sd, CBIT_INT, cbit_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (cbit_int & MASK_I_CBIT_FS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) tc35874x_s_ctrl_audio_sampling_rate(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) cbit_int &= ~MASK_I_CBIT_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) tc35874x_s_ctrl_audio_present(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (cbit_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) __func__, cbit_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static void tc35874x_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* Bit 7 and bit 6 are set even when they are masked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (clk_int & (MASK_I_IN_DE_CHG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) /* If the source switch to a new resolution with the same pixel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) * frequency as the existing (e.g. 1080p25 -> 720p50), the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) * I_SYNC_CHG interrupt is not always triggered, while the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) * I_IN_DE_CHG interrupt seems to work fine. Format change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * notifications are only sent when the signal is stable to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * reduce the number of notifications. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (!no_signal(sd) && !no_sync(sd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) tc35874x_format_change(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) clk_int &= ~(MASK_I_IN_DE_CHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (clk_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) __func__, clk_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static void tc35874x_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) i2c_wr8(sd, SYS_INT, sys_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (sys_int & MASK_I_DDC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) bool tx_5v = tx_5v_power_present(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) __func__, tx_5v ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (tx_5v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) tc35874x_enable_edid(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) tc35874x_enable_interrupts(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) tc35874x_disable_edid(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) memset(&state->timings, 0, sizeof(state->timings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) tc35874x_erase_bksv(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) tc35874x_update_controls(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) sys_int &= ~MASK_I_DDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (sys_int & MASK_I_DVI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) /* Reset the HDMI PHY to try to trigger proper lock on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) * incoming video format. Erase BKSV to prevent that old keys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) * are used when a new source is connected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (no_sync(sd) || no_signal(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) tc35874x_reset_phy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) tc35874x_erase_bksv(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) sys_int &= ~MASK_I_DVI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (sys_int & MASK_I_HDMI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /* Register is reset in DVI mode (REF_01, c. 6.6.41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) sys_int &= ~MASK_I_HDMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) if (sys_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) __func__, sys_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) /* --------------- CTRL OPS --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static int tc35874x_get_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) int ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) struct tc35874x_state *state = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) struct tc35874x_state, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) struct v4l2_subdev *sd = &(state->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (ctrl->id == V4L2_CID_DV_RX_POWER_PRESENT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ret = tx_5v_power_present(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) *ctrl->p_new.p_s32 = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) /* --------------- CORE OPS --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static int tc35874x_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) uint16_t sysctl = i2c_rd16(sd, SYSCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) u8 vi_status3 = i2c_rd8(sd, VI_STATUS3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) const int deep_color_mode[4] = { 8, 10, 12, 16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static const char * const input_color_space[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) "RGB", "YCbCr 601", "Adobe RGB", "YCbCr 709", "NA (4)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) "NA(10)", "NA(11)", "NA(12)", "Adobe YCC 601"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) v4l2_info(sd, "-----Chip status-----\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) v4l2_info(sd, "Chip ID: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) v4l2_info(sd, "Chip revision: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) i2c_rd16(sd, CHIPID) & MASK_REVID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) !!(sysctl & MASK_IRRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) !!(sysctl & MASK_CECRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) !!(sysctl & MASK_CTXRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) !!(sysctl & MASK_HDMIRST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) v4l2_info(sd, "Cable detected (+5V power): %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) v4l2_info(sd, "DDC lines enabled: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) v4l2_info(sd, "Hotplug enabled: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) v4l2_info(sd, "CEC enabled: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) v4l2_info(sd, "-----Signal status-----\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) v4l2_info(sd, "TMDS signal detected: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) v4l2_info(sd, "Stable sync signal: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) v4l2_info(sd, "PHY PLL locked: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) v4l2_info(sd, "PHY DE detected: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (tc35874x_get_detected_timings(sd, &timings)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) v4l2_info(sd, "No video detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) v4l2_info(sd, "-----CSI-TX status-----\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) v4l2_info(sd, "Lanes in use: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) state->csi_lanes_in_use);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) v4l2_info(sd, "Waiting for particular sync signal: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) v4l2_info(sd, "Transmit mode: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) v4l2_info(sd, "Receive mode: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) v4l2_info(sd, "Stopped: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) v4l2_info(sd, "Color space: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_2X8 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) "YCbCr 422 16-bit" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) "RGB 888 24-bit" : "Unsupported");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) v4l2_info(sd, "HDCP encrypted content: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) v4l2_info(sd, "Input color space: %s %s range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) (vi_status3 & MASK_LIMITED) ? "limited" : "full");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (!is_hdmi(sd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) MASK_S_DEEPCOLOR) >> 2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) print_avi_infoframe(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) static void tc35874x_print_register_map(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) v4l2_info(sd, "0x0400-0x05FF: Reserved\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) v4l2_info(sd, "0x0600-0x06FF: CEC Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) v4l2_info(sd, "0x0700-0x84FF: Reserved\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) v4l2_info(sd, "0x9300- : Reserved\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static int tc35874x_get_reg_size(u16 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /* REF_01 p. 66-72 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (address <= 0x00ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) else if ((address >= 0x0100) && (address <= 0x06FF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) else if ((address >= 0x0700) && (address <= 0x84ff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static int tc35874x_g_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if (reg->reg > 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) tc35874x_print_register_map(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) reg->size = tc35874x_get_reg_size(reg->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) reg->val = i2c_rdreg(sd, reg->reg, reg->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) static int tc35874x_s_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (reg->reg > 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) tc35874x_print_register_map(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) /* It should not be possible for the user to enable HDCP with a simple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * v4l2-dbg command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) * DO NOT REMOVE THIS unless all other issues with HDCP have been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) * resolved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (reg->reg == HDCP_MODE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) reg->reg == HDCP_REG1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) reg->reg == HDCP_REG2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) reg->reg == HDCP_REG3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) reg->reg == BCAPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) i2c_wrreg(sd, (u16)reg->reg, reg->val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) tc35874x_get_reg_size(reg->reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static int tc35874x_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) u16 intstatus = i2c_rd16(sd, INTSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) if (intstatus & MASK_HDMI_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (hdmi_int0 & MASK_I_MISC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) tc35874x_hdmi_misc_int_handler(sd, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (hdmi_int1 & MASK_I_CBIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) tc35874x_hdmi_cbit_int_handler(sd, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) if (hdmi_int1 & MASK_I_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) tc35874x_hdmi_clk_int_handler(sd, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (hdmi_int1 & MASK_I_SYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) tc35874x_hdmi_sys_int_handler(sd, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (hdmi_int1 & MASK_I_AUD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) tc35874x_hdmi_audio_int_handler(sd, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) intstatus &= ~MASK_HDMI_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (intstatus & MASK_CSI_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) u32 csi_int = i2c_rd32(sd, CSI_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (csi_int & MASK_INTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) tc35874x_csi_err_int_handler(sd, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) intstatus = i2c_rd16(sd, INTSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (intstatus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) "%s: Unhandled IntStatus interrupts: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) __func__, intstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static irqreturn_t tc35874x_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) struct tc35874x_state *state = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) bool handled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) tc35874x_isr(&state->sd, 0, &handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) return handled ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) static void tc35874x_irq_poll_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) struct tc35874x_state *state = from_timer(state, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) unsigned int msecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) schedule_work(&state->work_i2c_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) * If CEC is present, then we need to poll more frequently,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) * otherwise we will miss CEC messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) msecs = state->cec_adap ? POLL_INTERVAL_CEC_MS : POLL_INTERVAL_MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) mod_timer(&state->timer, jiffies + msecs_to_jiffies(msecs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static void tc35874x_work_i2c_poll(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) struct tc35874x_state *state = container_of(work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) struct tc35874x_state, work_i2c_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) bool handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) tc35874x_isr(&state->sd, 0, &handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) static int tc35874x_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) struct v4l2_event_subscription *sub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) switch (sub->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) case V4L2_EVENT_SOURCE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) case V4L2_EVENT_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) /* --------------- VIDEO OPS --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) static int tc35874x_g_input_status(struct v4l2_subdev *sd, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) static int tc35874x_s_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (!timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) v4l2_print_dv_timings(sd->name, "tc35874x_s_dv_timings: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) timings, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (!v4l2_valid_dv_timings(timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) &tc35874x_timings_cap, NULL, NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) state->timings = *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) enable_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) tc35874x_set_pll(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) tc35874x_set_csi(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) static int tc35874x_g_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) *timings = state->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static int tc35874x_enum_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) struct v4l2_enum_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (timings->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) return v4l2_enum_dv_timings_cap(timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) &tc35874x_timings_cap, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) static int tc35874x_query_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) ret = tc35874x_get_detected_timings(sd, timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) v4l2_print_dv_timings(sd->name, "tc35874x_query_dv_timings: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) timings, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) if (!v4l2_valid_dv_timings(timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) &tc35874x_timings_cap, NULL, NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static int tc35874x_dv_timings_cap(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) struct v4l2_dv_timings_cap *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) if (cap->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) *cap = tc35874x_timings_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) static int tc35874x_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) unsigned int pad, struct v4l2_mbus_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) cfg->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) /* Support for non-continuous CSI-2 clock is missing in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) switch (state->csi_lanes_in_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) static int tc35874x_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) enable_stream(sd, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) /* stop stream to reset csi*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) tc35874x_set_csi(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) /* --------------- PAD OPS --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) static int tc35874x_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) switch (code->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) code->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) code->code = MEDIA_BUS_FMT_RGB888_1X24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) static int tc35874x_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) v4l2_dbg(1, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if (fse->code != MEDIA_BUS_FMT_UYVY8_2X8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) static int tc35874x_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) if (fie->code != MEDIA_BUS_FMT_UYVY8_2X8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) static int tc35874x_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) u8 vi_rep = i2c_rd8(sd, VI_REP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) format->format.code = state->mbus_fmt_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) format->format.width = state->timings.bt.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) format->format.height = state->timings.bt.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) format->format.field =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) state->timings.bt.interlaced ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) V4L2_FIELD_INTERLACED : V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) switch (vi_rep & MASK_VOUT_COLOR_SEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) case MASK_VOUT_COLOR_RGB_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) case MASK_VOUT_COLOR_RGB_LIMITED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) format->format.colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) case MASK_VOUT_COLOR_601_YCBCR_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) case MASK_VOUT_COLOR_709_YCBCR_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) format->format.colorspace = V4L2_COLORSPACE_REC709;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) format->format.colorspace = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) static int tc35874x_get_reso_dist(const struct tc35874x_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) static const struct tc35874x_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) tc35874x_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) dist = tc35874x_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) static int tc35874x_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) const struct tc35874x_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) u32 code = format->format.code; /* is overwritten by get_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) int ret = tc35874x_get_fmt(sd, cfg, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) format->format.code = code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) switch (code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) case MEDIA_BUS_FMT_RGB888_1X24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) case MEDIA_BUS_FMT_UYVY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if (format->which == V4L2_SUBDEV_FORMAT_TRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) state->mbus_fmt_code = format->format.code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) enable_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) mode = tc35874x_find_best_fit(format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) state->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) __v4l2_ctrl_s_ctrl(state->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) link_freq_menu_items[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) __v4l2_ctrl_s_ctrl_int64(state->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) TC35874X_PIXEL_RATE_310M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) tc35874x_set_pll(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) tc35874x_set_csi(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) tc35874x_set_csi_color_space(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) static int tc35874x_g_edid(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) struct v4l2_subdev_edid *edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) memset(edid->reserved, 0, sizeof(edid->reserved));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) if (edid->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (edid->start_block == 0 && edid->blocks == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) edid->blocks = state->edid_blocks_written;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (state->edid_blocks_written == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) if (edid->start_block >= state->edid_blocks_written ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) edid->blocks == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) if (edid->start_block + edid->blocks > state->edid_blocks_written)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) edid->blocks = state->edid_blocks_written - edid->start_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) edid->blocks * EDID_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) static int tc35874x_s_edid(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) struct v4l2_subdev_edid *edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) u16 edid_len = edid->blocks * EDID_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) __func__, edid->pad, edid->start_block, edid->blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) memset(edid->reserved, 0, sizeof(edid->reserved));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) if (edid->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) if (edid->start_block != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) edid->blocks = EDID_NUM_BLOCKS_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) return -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) tc35874x_disable_edid(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if (edid->blocks == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) state->edid_blocks_written = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) i2c_wr(sd, EDID_EXT_RAM + i, EDID_extend + i, EDID_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) state->edid_blocks_written = edid->blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) if (tx_5v_power_present(sd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) tc35874x_enable_edid(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) static int tc35874x_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) const struct tc35874x_mode *mode = state->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) mutex_lock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) mutex_unlock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) static void tc35874x_get_module_inf(struct tc35874x_state *tc35874x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) strlcpy(inf->base.sensor, TC35874X_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) strlcpy(inf->base.module, tc35874x->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) strlcpy(inf->base.lens, tc35874x->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) static long tc35874x_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) struct tc35874x_state *tc35874x = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) tc35874x_get_module_inf(tc35874x, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) static long tc35874x_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) ret = tc35874x_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) ret = tc35874x_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) /* -------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) static const struct v4l2_ctrl_ops tc35874x_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) .g_volatile_ctrl = tc35874x_get_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) static const struct v4l2_subdev_core_ops tc35874x_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) .log_status = tc35874x_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) .g_register = tc35874x_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) .s_register = tc35874x_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .interrupt_service_routine = tc35874x_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .subscribe_event = tc35874x_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .unsubscribe_event = v4l2_event_subdev_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .ioctl = tc35874x_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) .compat_ioctl32 = tc35874x_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) static const struct v4l2_subdev_video_ops tc35874x_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .g_input_status = tc35874x_g_input_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .s_dv_timings = tc35874x_s_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .g_dv_timings = tc35874x_g_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) .query_dv_timings = tc35874x_query_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) .s_stream = tc35874x_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) .g_frame_interval = tc35874x_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) static const struct v4l2_subdev_pad_ops tc35874x_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .enum_mbus_code = tc35874x_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .enum_frame_size = tc35874x_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .enum_frame_interval = tc35874x_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) .set_fmt = tc35874x_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) .get_fmt = tc35874x_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .get_edid = tc35874x_g_edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .set_edid = tc35874x_s_edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .enum_dv_timings = tc35874x_enum_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .dv_timings_cap = tc35874x_dv_timings_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .get_mbus_config = tc35874x_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) static const struct v4l2_subdev_ops tc35874x_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .core = &tc35874x_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .video = &tc35874x_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .pad = &tc35874x_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) /* --------------- CUSTOM CTRLS --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) static int tc35874x_get_custom_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) struct tc35874x_state *state = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) struct tc35874x_state, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) struct v4l2_subdev *sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) if (ctrl->id == TC35874X_CID_AUDIO_SAMPLING_RATE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) ret = get_audio_sampling_rate(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) *ctrl->p_new.p_s32 = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) static const struct v4l2_ctrl_ops tc35874x_custom_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) .g_volatile_ctrl = tc35874x_get_custom_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) static const struct v4l2_ctrl_config tc35874x_ctrl_audio_sampling_rate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) .ops = &tc35874x_custom_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) .id = TC35874X_CID_AUDIO_SAMPLING_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) .name = "Audio sampling rate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) .type = V4L2_CTRL_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) .min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) .max = 768000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) .step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) .def = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) .flags = V4L2_CTRL_FLAG_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) static const struct v4l2_ctrl_config tc35874x_ctrl_audio_present = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .id = TC35874X_CID_AUDIO_PRESENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .name = "Audio present",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .type = V4L2_CTRL_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .def = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .flags = V4L2_CTRL_FLAG_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) /* --------------- PROBE / REMOVE --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) static void tc35874x_gpio_reset(struct tc35874x_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) gpiod_set_value(state->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) gpiod_set_value(state->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) static int tc35874x_probe_of(struct tc35874x_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) struct device *dev = &state->i2c_client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) struct device_node *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) struct clk *refclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) u32 bps_pr_lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) refclk = devm_clk_get(dev, "refclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) if (IS_ERR(refclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) if (PTR_ERR(refclk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) dev_err(dev, "failed to get refclk: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) PTR_ERR(refclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) return PTR_ERR(refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) ep = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) if (!ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) dev_err(dev, "missing endpoint node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), &endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) dev_err(dev, "failed to parse endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) goto put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) if (endpoint.bus_type != V4L2_MBUS_CSI2_DPHY ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) endpoint.bus.mipi_csi2.num_data_lanes == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) endpoint.nr_of_link_frequencies == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) dev_err(dev, "missing CSI-2 properties in endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) goto free_endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) state->csi_lanes_in_use = endpoint.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) state->bus = endpoint.bus.mipi_csi2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) ret = clk_prepare_enable(refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) dev_err(dev, "Failed! to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) goto free_endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) state->pdata.refclk_hz = clk_get_rate(refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) state->pdata.enable_hdcp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) state->pdata.fifo_level = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) * The PLL input clock is obtained by dividing refclk by pll_prd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) * It must be between 6 MHz and 40 MHz, lower frequency is better.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) switch (state->pdata.refclk_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) case 26000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) case 27000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) case 42000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) state->pdata.pll_prd = state->pdata.refclk_hz / 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) dev_err(dev, "unsupported refclk rate: %u Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) state->pdata.refclk_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) bps_pr_lane = 2 * endpoint.link_frequencies[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) /* The CSI speed per lane is refclk / pll_prd * pll_fbd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) state->pdata.pll_fbd = bps_pr_lane /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) state->pdata.refclk_hz * state->pdata.pll_prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) * link frequency). In principle it should be possible to calculate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) * them based on link frequency and resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) if (bps_pr_lane != 594000000U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) state->pdata.lineinitcnt = 0xe80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) state->pdata.lptxtimecnt = 0x003;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) state->pdata.tclk_headercnt = 0x1403;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) state->pdata.tclk_trailcnt = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) /* ths-preparecnt: 3, ths-zerocnt: 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) state->pdata.ths_headercnt = 0x0103;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) state->pdata.twakeup = 0x4882;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) state->pdata.tclk_postcnt = 0x008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) state->pdata.ths_trailcnt = 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) state->pdata.hstxvregcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) if (IS_ERR(state->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) dev_err(dev, "failed to get reset gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) ret = PTR_ERR(state->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) if (state->reset_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) tc35874x_gpio_reset(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) goto free_endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) clk_disable_unprepare(refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) free_endpoint:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) v4l2_fwnode_endpoint_free(&endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) put_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) of_node_put(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) static inline int tc35874x_probe_of(struct tc35874x_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) static int tc35874x_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) static struct v4l2_dv_timings default_timing =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) V4L2_DV_BT_CEA_640X480P59_94;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) struct tc35874x_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) struct tc35874x_platform_data *pdata = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) struct v4l2_subdev_edid def_edid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) int err, data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) state = devm_kzalloc(&client->dev, sizeof(struct tc35874x_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) err = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) &state->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) err |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) &state->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) err |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) &state->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) err |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) &state->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) state->i2c_client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) state->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) /* platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) state->pdata = *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) err = tc35874x_probe_of(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) if (err == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) v4l_err(client, "No platform data!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) v4l2_i2c_subdev_init(sd, client, &tc35874x_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) /* i2c access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) data = i2c_rd16(sd, CHIPID) & MASK_CHIPID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) switch (data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) case 0x0000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) case 0x4700:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) v4l2_info(sd, "not a tc35874x on address 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) client->addr << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) /* control handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) v4l2_ctrl_handler_init(&state->hdl, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) state->link_freq = v4l2_ctrl_new_int_menu(&state->hdl, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) V4L2_CID_LINK_FREQ, 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) state->pixel_rate = v4l2_ctrl_new_std(&state->hdl, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) V4L2_CID_PIXEL_RATE, 0, TC35874X_PIXEL_RATE_310M, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) TC35874X_PIXEL_RATE_310M);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) &tc35874x_ctrl_ops, V4L2_CID_DV_RX_POWER_PRESENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) 0, 1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) if (state->detect_tx_5v_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) state->detect_tx_5v_ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) /* custom controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) &tc35874x_ctrl_audio_sampling_rate, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) if (state->audio_sampling_rate_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) state->audio_sampling_rate_ctrl->flags |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) V4L2_CTRL_FLAG_VOLATILE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) &tc35874x_ctrl_audio_present, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) sd->ctrl_handler = &state->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) if (state->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) err = state->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) if (tc35874x_update_controls(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) state->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) err = media_entity_pads_init(&sd->entity, 1, &state->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) state->mbus_fmt_code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) sd->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) if (strcmp(state->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) state->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) TC35874X_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) err = v4l2_async_register_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) mutex_init(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) tc35874x_delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) tc35874x_initial_setup(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) tc35874x_s_dv_timings(sd, &default_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) tc35874x_set_csi_color_space(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) def_edid.pad = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) def_edid.start_block = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) def_edid.blocks = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) def_edid.edid = EDID_1920x1080_60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) tc35874x_s_edid(sd, &def_edid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) tc35874x_init_interrupts(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) if (state->i2c_client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) err = devm_request_threaded_irq(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) state->i2c_client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) NULL, tc35874x_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) "tc35874x", state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) goto err_work_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) INIT_WORK(&state->work_i2c_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) tc35874x_work_i2c_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) timer_setup(&state->timer, tc35874x_irq_poll_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) state->timer.expires = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) msecs_to_jiffies(POLL_INTERVAL_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) add_timer(&state->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) tc35874x_enable_interrupts(sd, tx_5v_power_present(sd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) i2c_wr16(sd, INTMASK, ~(MASK_HDMI_MSK | MASK_CSI_MSK) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) goto err_work_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) err_work_queues:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) if (!state->i2c_client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) flush_work(&state->work_i2c_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) cancel_delayed_work(&state->delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) mutex_destroy(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) err_hdl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) v4l2_ctrl_handler_free(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) static int tc35874x_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) struct tc35874x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) if (!state->i2c_client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) del_timer_sync(&state->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) flush_work(&state->work_i2c_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) cancel_delayed_work(&state->delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) mutex_destroy(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) v4l2_ctrl_handler_free(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) static struct i2c_device_id tc35874x_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) {"tc358743", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) {"tc358749", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) MODULE_DEVICE_TABLE(i2c, tc35874x_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) static const struct of_device_id tc35874x_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) { .compatible = "toshiba,tc358743" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) { .compatible = "toshiba,tc358749" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) MODULE_DEVICE_TABLE(of, tc35874x_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) static struct i2c_driver tc35874x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .name = TC35874X_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) .of_match_table = of_match_ptr(tc35874x_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .probe = tc35874x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) .remove = tc35874x_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .id_table = tc35874x_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) static int __init tc35874x_driver_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) return i2c_add_driver(&tc35874x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) static void __exit tc35874x_driver_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) i2c_del_driver(&tc35874x_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) device_initcall_sync(tc35874x_driver_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) module_exit(tc35874x_driver_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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