^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * tc358743 - Toshiba HDMI to CSI-2 bridge
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2015 Cisco Systems, Inc. and/or its affiliates. All rights
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * References (c = chapter, p = page):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * REF_01 - Toshiba, TC358743XBG (H2C), Functional Specification, Rev 0.60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * REF_02 - Toshiba, TC358743XBG_HDMI-CSI_Tv11p_nm.xls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/hdmi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/cec.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-dv-timings.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <media/i2c/tc358743.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "tc358743_regs.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MODULE_PARM_DESC(debug, "debug level (0-3)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MODULE_DESCRIPTION("Toshiba TC358743 HDMI to CSI-2 bridge driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MODULE_AUTHOR("Ramakrishnan Muthukrishnan <ram@rkrishnan.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MODULE_AUTHOR("Mikhail Khelik <mkhelik@cisco.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MODULE_AUTHOR("Mats Randgaard <matrandg@cisco.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define EDID_NUM_BLOCKS_MAX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define EDID_BLOCK_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define I2C_MAX_XFER_SIZE (EDID_BLOCK_SIZE + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define POLL_INTERVAL_CEC_MS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define POLL_INTERVAL_MS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static const struct v4l2_dv_timings_cap tc358743_timings_cap = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) .type = V4L2_DV_BT_656_1120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* keep this initialization for compatibility with GCC < 4.4.6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .reserved = { 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Pixel clock from REF_01 p. 20. Min/max height/width are unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) V4L2_INIT_BT_TIMINGS(640, 1920, 350, 1200, 13000000, 165000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) V4L2_DV_BT_STD_GTF | V4L2_DV_BT_STD_CVT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) V4L2_DV_BT_CAP_PROGRESSIVE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) V4L2_DV_BT_CAP_REDUCED_BLANKING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) V4L2_DV_BT_CAP_CUSTOM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct tc358743_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct tc358743_platform_data pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct v4l2_fwnode_bus_mipi_csi2 bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct i2c_client *i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* CONFCTL is modified in ops and tc358743_hdmi_sys_int_handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct mutex confctl_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct v4l2_ctrl *detect_tx_5v_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct v4l2_ctrl *audio_sampling_rate_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct v4l2_ctrl *audio_present_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct delayed_work delayed_work_enable_hotplug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct work_struct work_i2c_poll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* edid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 edid_blocks_written;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 mbus_fmt_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u8 csi_lanes_in_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct cec_adapter *cec_adap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) bool cable_connected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline struct tc358743_state *to_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return container_of(sd, struct tc358743_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* --------------- I2C --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) static void i2c_rd(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct i2c_client *client = state->i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 buf[2] = { reg >> 8, reg & 0xff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct i2c_msg msgs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .buf = buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .flags = I2C_M_RD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .len = n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .buf = values,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) err = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) if (err != ARRAY_SIZE(msgs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) v4l2_err(sd, "%s: reading register 0x%x from 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) __func__, reg, client->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void i2c_wr(struct v4l2_subdev *sd, u16 reg, u8 *values, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct i2c_client *client = state->i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 data[I2C_MAX_XFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if ((2 + n) > I2C_MAX_XFER_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) n = I2C_MAX_XFER_SIZE - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) v4l2_warn(sd, "i2c wr reg=%04x: len=%d is too big!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) reg, 2 + n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) msg.buf = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) msg.len = 2 + n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) msg.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) data[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) data[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) for (i = 0; i < n; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) data[2 + i] = values[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) err = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) if (err != 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) v4l2_err(sd, "%s: writing register 0x%x from 0x%x failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) __func__, reg, client->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (debug < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) switch (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) v4l2_info(sd, "I2C write 0x%04x = 0x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) reg, data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) reg, data[3], data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) v4l2_info(sd, "I2C write 0x%04x = 0x%02x%02x%02x%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) reg, data[5], data[4], data[3], data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) v4l2_info(sd, "I2C write %d bytes from address 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) n, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static noinline u32 i2c_rdreg(struct v4l2_subdev *sd, u16 reg, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) __le32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) i2c_rd(sd, reg, (u8 __force *)&val, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return le32_to_cpu(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static noinline void i2c_wrreg(struct v4l2_subdev *sd, u16 reg, u32 val, u32 n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) __le32 raw = cpu_to_le32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) i2c_wr(sd, reg, (u8 __force *)&raw, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static u8 i2c_rd8(struct v4l2_subdev *sd, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) return i2c_rdreg(sd, reg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static void i2c_wr8(struct v4l2_subdev *sd, u16 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) i2c_wrreg(sd, reg, val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void i2c_wr8_and_or(struct v4l2_subdev *sd, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 1) & mask) | val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static u16 i2c_rd16(struct v4l2_subdev *sd, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return i2c_rdreg(sd, reg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static void i2c_wr16(struct v4l2_subdev *sd, u16 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) i2c_wrreg(sd, reg, val, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void i2c_wr16_and_or(struct v4l2_subdev *sd, u16 reg, u16 mask, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) i2c_wrreg(sd, reg, (i2c_rdreg(sd, reg, 2) & mask) | val, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static u32 i2c_rd32(struct v4l2_subdev *sd, u16 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return i2c_rdreg(sd, reg, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static void i2c_wr32(struct v4l2_subdev *sd, u16 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) i2c_wrreg(sd, reg, val, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* --------------- STATUS --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static inline bool is_hdmi(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) return i2c_rd8(sd, SYS_STATUS) & MASK_S_HDMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static inline bool tx_5v_power_present(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return i2c_rd8(sd, SYS_STATUS) & MASK_S_DDC5V;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static inline bool no_signal(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_TMDS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static inline bool no_sync(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return !(i2c_rd8(sd, SYS_STATUS) & MASK_S_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static inline bool audio_present(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return i2c_rd8(sd, AU_STATUS0) & MASK_S_A_SAMPLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) static int get_audio_sampling_rate(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const int code_to_rate[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 44100, 0, 48000, 32000, 22050, 384000, 24000, 352800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 88200, 768000, 96000, 705600, 176400, 0, 192000, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* Register FS_SET is not cleared when the cable is disconnected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (no_signal(sd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return code_to_rate[i2c_rd8(sd, FS_SET) & MASK_FS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* --------------- TIMINGS --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static inline unsigned fps(const struct v4l2_bt_timings *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (!V4L2_DV_BT_FRAME_HEIGHT(t) || !V4L2_DV_BT_FRAME_WIDTH(t))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return DIV_ROUND_CLOSEST((unsigned)t->pixelclock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) V4L2_DV_BT_FRAME_HEIGHT(t) * V4L2_DV_BT_FRAME_WIDTH(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static int tc358743_get_detected_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct v4l2_bt_timings *bt = &timings->bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) unsigned width, height, frame_width, frame_height, frame_interval, fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) memset(timings, 0, sizeof(struct v4l2_dv_timings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (no_signal(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return -ENOLINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (no_sync(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) v4l2_dbg(1, debug, sd, "%s: no sync on signal\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return -ENOLCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) timings->type = V4L2_DV_BT_656_1120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) bt->interlaced = i2c_rd8(sd, VI_STATUS1) & MASK_S_V_INTERLACE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) V4L2_DV_INTERLACED : V4L2_DV_PROGRESSIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) width = ((i2c_rd8(sd, DE_WIDTH_H_HI) & 0x1f) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) i2c_rd8(sd, DE_WIDTH_H_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) height = ((i2c_rd8(sd, DE_WIDTH_V_HI) & 0x1f) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) i2c_rd8(sd, DE_WIDTH_V_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) frame_width = ((i2c_rd8(sd, H_SIZE_HI) & 0x1f) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) i2c_rd8(sd, H_SIZE_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) frame_height = (((i2c_rd8(sd, V_SIZE_HI) & 0x3f) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) i2c_rd8(sd, V_SIZE_LO)) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* frame interval in milliseconds * 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * Require SYS_FREQ0 and SYS_FREQ1 are precisely set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) frame_interval = ((i2c_rd8(sd, FV_CNT_HI) & 0x3) << 8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) i2c_rd8(sd, FV_CNT_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) fps = (frame_interval > 0) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) DIV_ROUND_CLOSEST(10000, frame_interval) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) bt->width = width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bt->height = height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) bt->vsync = frame_height - height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) bt->hsync = frame_width - width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) bt->pixelclock = frame_width * frame_height * fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (bt->interlaced == V4L2_DV_INTERLACED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) bt->height *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) bt->il_vsync = bt->vsync + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) bt->pixelclock /= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* --------------- HOTPLUG / HDCP / EDID --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static void tc358743_delayed_work_enable_hotplug(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct delayed_work *dwork = to_delayed_work(work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct tc358743_state *state = container_of(dwork,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct tc358743_state, delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct v4l2_subdev *sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) v4l2_dbg(2, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, MASK_HPD_OUT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void tc358743_set_hdmi_hdcp(struct v4l2_subdev *sd, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) v4l2_dbg(2, debug, sd, "%s: %s\n", __func__, enable ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) "enable" : "disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) i2c_wr8_and_or(sd, HDCP_REG3, ~KEY_RD_CMD, KEY_RD_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) i2c_wr8_and_or(sd, HDCP_REG1, 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) MASK_AUTH_UNAUTH_SEL_16_FRAMES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) MASK_AUTH_UNAUTH_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) i2c_wr8_and_or(sd, HDCP_REG2, ~MASK_AUTO_P3_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) SET_AUTO_P3_RESET_FRAMES(0x0f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) i2c_wr8_and_or(sd, HDCP_MODE, ~MASK_MANUAL_AUTHENTICATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MASK_MANUAL_AUTHENTICATION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static void tc358743_disable_edid(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) v4l2_dbg(2, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* DDC access to EDID is also disabled when hotplug is disabled. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * register DDC_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) i2c_wr8_and_or(sd, HPD_CTL, ~MASK_HPD_OUT0, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static void tc358743_enable_edid(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (state->edid_blocks_written == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) v4l2_dbg(2, debug, sd, "%s: no EDID -> no hotplug\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) tc358743_s_ctrl_detect_tx_5v(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) v4l2_dbg(2, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /* Enable hotplug after 100 ms. DDC access to EDID is also enabled when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * hotplug is enabled. See register DDC_CTL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) tc358743_enable_interrupts(sd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) tc358743_s_ctrl_detect_tx_5v(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) static void tc358743_erase_bksv(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) for (i = 0; i < 5; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) i2c_wr8(sd, BKSV + i, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* --------------- AVI infoframe --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) static void print_avi_infoframe(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) union hdmi_infoframe frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (!is_hdmi(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) v4l2_info(sd, "DVI-D signal - AVI infoframe not supported\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) i2c_rd(sd, PK_AVI_0HEAD, buffer, HDMI_INFOFRAME_SIZE(AVI));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (hdmi_infoframe_unpack(&frame, buffer, sizeof(buffer)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) v4l2_err(sd, "%s: unpack of AVI infoframe failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) hdmi_infoframe_log(KERN_INFO, dev, &frame);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /* --------------- CTRLS --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static int tc358743_s_ctrl_detect_tx_5v(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) tx_5v_power_present(sd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static int tc358743_s_ctrl_audio_sampling_rate(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return v4l2_ctrl_s_ctrl(state->audio_sampling_rate_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) get_audio_sampling_rate(sd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int tc358743_s_ctrl_audio_present(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return v4l2_ctrl_s_ctrl(state->audio_present_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) audio_present(sd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int tc358743_update_controls(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) ret |= tc358743_s_ctrl_detect_tx_5v(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) ret |= tc358743_s_ctrl_audio_sampling_rate(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret |= tc358743_s_ctrl_audio_present(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* --------------- INIT --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static void tc358743_reset_phy(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) v4l2_dbg(1, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) i2c_wr8_and_or(sd, PHY_RST, ~MASK_RESET_CTRL, MASK_RESET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static void tc358743_reset(struct v4l2_subdev *sd, uint16_t mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u16 sysctl = i2c_rd16(sd, SYSCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) i2c_wr16(sd, SYSCTL, sysctl | mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) i2c_wr16(sd, SYSCTL, sysctl & ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static inline void tc358743_sleep_mode(struct v4l2_subdev *sd, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) i2c_wr16_and_or(sd, SYSCTL, ~MASK_SLEEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) enable ? MASK_SLEEP : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static inline void enable_stream(struct v4l2_subdev *sd, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) v4l2_dbg(3, debug, sd, "%s: %sable\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) __func__, enable ? "en" : "dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /* It is critical for CSI receiver to see lane transition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * LP11->HS. Set to non-continuous mode to enable clock lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * LP11 state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) i2c_wr32(sd, TXOPTIONCNTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Set to continuous mode to trigger LP11->HS transition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) i2c_wr32(sd, TXOPTIONCNTRL, MASK_CONTCLKMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* Unmute video */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /* Mute video so that all data lanes go to LSP11 state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * No data is output to CSI Tx block. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) i2c_wr8(sd, VI_MUTE, MASK_AUTO_MUTE | MASK_VI_MUTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) mutex_lock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) i2c_wr16_and_or(sd, CONFCTL, ~(MASK_VBUFEN | MASK_ABUFEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) enable ? (MASK_VBUFEN | MASK_ABUFEN) : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mutex_unlock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static void tc358743_set_pll(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct tc358743_platform_data *pdata = &state->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u16 pllctl0 = i2c_rd16(sd, PLLCTL0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u16 pllctl1 = i2c_rd16(sd, PLLCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u16 pllctl0_new = SET_PLL_PRD(pdata->pll_prd) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) SET_PLL_FBD(pdata->pll_fbd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 hsck = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) v4l2_dbg(2, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Only rewrite when needed (new value or disabled), since rewriting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * triggers another format change event. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if ((pllctl0 != pllctl0_new) || ((pllctl1 & MASK_PLL_EN) == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u16 pll_frs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (hsck > 500000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pll_frs = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) else if (hsck > 250000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) pll_frs = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) else if (hsck > 125000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) pll_frs = 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) pll_frs = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) v4l2_dbg(1, debug, sd, "%s: updating PLL clock\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) tc358743_sleep_mode(sd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) i2c_wr16(sd, PLLCTL0, pllctl0_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) i2c_wr16_and_or(sd, PLLCTL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ~(MASK_PLL_FRS | MASK_RESETB | MASK_PLL_EN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) (SET_PLL_FRS(pll_frs) | MASK_RESETB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) MASK_PLL_EN));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) udelay(10); /* REF_02, Sheet "Source HDMI" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) i2c_wr16_and_or(sd, PLLCTL1, ~MASK_CKEN, MASK_CKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) tc358743_sleep_mode(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static void tc358743_set_ref_clk(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct tc358743_platform_data *pdata = &state->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u32 sys_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u32 lockdet_ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u32 cec_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u16 fh_min;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u16 fh_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) BUG_ON(!(pdata->refclk_hz == 26000000 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) pdata->refclk_hz == 27000000 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) pdata->refclk_hz == 42000000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) sys_freq = pdata->refclk_hz / 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) i2c_wr8(sd, SYS_FREQ0, sys_freq & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) i2c_wr8(sd, SYS_FREQ1, (sys_freq & 0xff00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) i2c_wr8_and_or(sd, PHY_CTL0, ~MASK_PHY_SYSCLK_IND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) (pdata->refclk_hz == 42000000) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) MASK_PHY_SYSCLK_IND : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) fh_min = pdata->refclk_hz / 100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) i2c_wr8(sd, FH_MIN0, fh_min & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) i2c_wr8(sd, FH_MIN1, (fh_min & 0xff00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) fh_max = (fh_min * 66) / 10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) i2c_wr8(sd, FH_MAX0, fh_max & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) i2c_wr8(sd, FH_MAX1, (fh_max & 0xff00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) lockdet_ref = pdata->refclk_hz / 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) i2c_wr8(sd, LOCKDET_REF0, lockdet_ref & 0x0000ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) i2c_wr8(sd, LOCKDET_REF1, (lockdet_ref & 0x00ff00) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) i2c_wr8(sd, LOCKDET_REF2, (lockdet_ref & 0x0f0000) >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) i2c_wr8_and_or(sd, NCO_F0_MOD, ~MASK_NCO_F0_MOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) (pdata->refclk_hz == 27000000) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) MASK_NCO_F0_MOD_27MHZ : 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * Trial and error suggests that the default register value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * of 656 is for a 42 MHz reference clock. Use that to derive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * a new value based on the actual reference clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) cec_freq = (656 * sys_freq) / 4200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) i2c_wr16(sd, CECHCLK, cec_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) i2c_wr16(sd, CECLCLK, cec_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static void tc358743_set_csi_color_space(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) switch (state->mbus_fmt_code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) case MEDIA_BUS_FMT_UYVY8_1X16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) v4l2_dbg(2, debug, sd, "%s: YCbCr 422 16-bit\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) i2c_wr8_and_or(sd, VOUT_SET2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) MASK_SEL422 | MASK_VOUT_422FIL_100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) MASK_VOUT_COLOR_601_YCBCR_LIMITED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) mutex_lock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) MASK_YCBCRFMT_422_8_BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) mutex_unlock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) case MEDIA_BUS_FMT_RGB888_1X24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) v4l2_dbg(2, debug, sd, "%s: RGB 888 24-bit\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) i2c_wr8_and_or(sd, VOUT_SET2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ~(MASK_SEL422 | MASK_VOUT_422FIL_100) & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) i2c_wr8_and_or(sd, VI_REP, ~MASK_VOUT_COLOR_SEL & 0xff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) MASK_VOUT_COLOR_RGB_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) mutex_lock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) i2c_wr16_and_or(sd, CONFCTL, ~MASK_YCBCRFMT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) mutex_unlock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) v4l2_dbg(2, debug, sd, "%s: Unsupported format code 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) __func__, state->mbus_fmt_code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static unsigned tc358743_num_csi_lanes_needed(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct v4l2_bt_timings *bt = &state->timings.bt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct tc358743_platform_data *pdata = &state->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u32 bits_pr_pixel =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) (state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16) ? 16 : 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u32 bps = bt->width * bt->height * fps(bt) * bits_pr_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u32 bps_pr_lane = (pdata->refclk_hz / pdata->pll_prd) * pdata->pll_fbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return DIV_ROUND_UP(bps, bps_pr_lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static void tc358743_set_csi(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct tc358743_platform_data *pdata = &state->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) unsigned lanes = tc358743_num_csi_lanes_needed(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) v4l2_dbg(3, debug, sd, "%s:\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) state->csi_lanes_in_use = lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) tc358743_reset(sd, MASK_CTXRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (lanes < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) i2c_wr32(sd, CLW_CNTRL, MASK_CLW_LANEDISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (lanes < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) i2c_wr32(sd, D0W_CNTRL, MASK_D0W_LANEDISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (lanes < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) i2c_wr32(sd, D1W_CNTRL, MASK_D1W_LANEDISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (lanes < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) i2c_wr32(sd, D2W_CNTRL, MASK_D2W_LANEDISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (lanes < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) i2c_wr32(sd, D3W_CNTRL, MASK_D3W_LANEDISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) i2c_wr32(sd, LINEINITCNT, pdata->lineinitcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) i2c_wr32(sd, LPTXTIMECNT, pdata->lptxtimecnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) i2c_wr32(sd, TCLK_HEADERCNT, pdata->tclk_headercnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) i2c_wr32(sd, TCLK_TRAILCNT, pdata->tclk_trailcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) i2c_wr32(sd, THS_HEADERCNT, pdata->ths_headercnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) i2c_wr32(sd, TWAKEUP, pdata->twakeup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) i2c_wr32(sd, TCLK_POSTCNT, pdata->tclk_postcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) i2c_wr32(sd, THS_TRAILCNT, pdata->ths_trailcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) i2c_wr32(sd, HSTXVREGCNT, pdata->hstxvregcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) i2c_wr32(sd, HSTXVREGEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ((lanes > 0) ? MASK_CLM_HSTXVREGEN : 0x0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ((lanes > 0) ? MASK_D0M_HSTXVREGEN : 0x0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ((lanes > 1) ? MASK_D1M_HSTXVREGEN : 0x0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ((lanes > 2) ? MASK_D2M_HSTXVREGEN : 0x0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ((lanes > 3) ? MASK_D3M_HSTXVREGEN : 0x0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) i2c_wr32(sd, TXOPTIONCNTRL, (state->bus.flags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK) ? MASK_CONTCLKMODE : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) i2c_wr32(sd, STARTCNTRL, MASK_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) i2c_wr32(sd, CSI_START, MASK_STRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) MASK_ADDRESS_CSI_CONTROL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) MASK_CSI_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) MASK_TXHSMD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ((lanes == 4) ? MASK_NOL_4 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) (lanes == 3) ? MASK_NOL_3 :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) (lanes == 2) ? MASK_NOL_2 : MASK_NOL_1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) MASK_ADDRESS_CSI_ERR_INTENA | MASK_TXBRK | MASK_QUNK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) MASK_WCER | MASK_INER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) i2c_wr32(sd, CSI_CONFW, MASK_MODE_CLEAR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) MASK_ADDRESS_CSI_ERR_HALT | MASK_TXBRK | MASK_QUNK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) i2c_wr32(sd, CSI_CONFW, MASK_MODE_SET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) MASK_ADDRESS_CSI_INT_ENA | MASK_INTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static void tc358743_set_hdmi_phy(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct tc358743_platform_data *pdata = &state->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Default settings from REF_02, sheet "Source HDMI"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * and custom settings as platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) i2c_wr8(sd, PHY_CTL1, SET_PHY_AUTO_RST1_US(1600) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) SET_FREQ_RANGE_MODE_CYCLES(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) i2c_wr8_and_or(sd, PHY_CTL2, ~MASK_PHY_AUTO_RSTn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) (pdata->hdmi_phy_auto_reset_tmds_detected ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) MASK_PHY_AUTO_RST2 : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) (pdata->hdmi_phy_auto_reset_tmds_in_range ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) MASK_PHY_AUTO_RST3 : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) (pdata->hdmi_phy_auto_reset_tmds_valid ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) MASK_PHY_AUTO_RST4 : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) i2c_wr8(sd, PHY_BIAS, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) i2c_wr8(sd, PHY_CSQ, SET_CSQ_CNT_LEVEL(0x0a));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) i2c_wr8(sd, AVM_CTL, 45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) i2c_wr8_and_or(sd, HDMI_DET, ~MASK_HDMI_DET_V,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) pdata->hdmi_detection_delay << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) i2c_wr8_and_or(sd, HV_RST, ~(MASK_H_PI_RST | MASK_V_PI_RST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) (pdata->hdmi_phy_auto_reset_hsync_out_of_range ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) MASK_H_PI_RST : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) (pdata->hdmi_phy_auto_reset_vsync_out_of_range ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) MASK_V_PI_RST : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) i2c_wr8_and_or(sd, PHY_EN, ~MASK_ENABLE_PHY, MASK_ENABLE_PHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static void tc358743_set_hdmi_audio(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Default settings from REF_02, sheet "Source HDMI" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) i2c_wr8(sd, FORCE_MUTE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) i2c_wr8(sd, AUTO_CMD0, MASK_AUTO_MUTE7 | MASK_AUTO_MUTE6 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) MASK_AUTO_MUTE5 | MASK_AUTO_MUTE4 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) MASK_AUTO_MUTE1 | MASK_AUTO_MUTE0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) i2c_wr8(sd, AUTO_CMD1, MASK_AUTO_MUTE9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) i2c_wr8(sd, AUTO_CMD2, MASK_AUTO_PLAY3 | MASK_AUTO_PLAY2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) i2c_wr8(sd, BUFINIT_START, SET_BUFINIT_START_MS(500));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) i2c_wr8(sd, FS_MUTE, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) i2c_wr8(sd, FS_IMODE, MASK_NLPCM_SMODE | MASK_FS_SMODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) i2c_wr8(sd, ACR_MODE, MASK_CTS_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) i2c_wr8(sd, ACR_MDF0, MASK_ACR_L2MDF_1976_PPM | MASK_ACR_L1MDF_976_PPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) i2c_wr8(sd, ACR_MDF1, MASK_ACR_L3MDF_3906_PPM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) i2c_wr8(sd, SDO_MODE1, MASK_SDO_FMT_I2S);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) i2c_wr8(sd, DIV_MODE, SET_DIV_DLY_MS(100));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) mutex_lock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) i2c_wr16_and_or(sd, CONFCTL, 0xffff, MASK_AUDCHNUM_2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) MASK_AUDOUTSEL_I2S | MASK_AUTOINDEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) mutex_unlock(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static void tc358743_set_hdmi_info_frame_mode(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /* Default settings from REF_02, sheet "Source HDMI" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) i2c_wr8(sd, PK_INT_MODE, MASK_ISRC2_INT_MODE | MASK_ISRC_INT_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) MASK_ACP_INT_MODE | MASK_VS_INT_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) MASK_SPD_INT_MODE | MASK_MS_INT_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) MASK_AUD_INT_MODE | MASK_AVI_INT_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) i2c_wr8(sd, NO_PKT_LIMIT, 0x2c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) i2c_wr8(sd, NO_PKT_CLR, 0x53);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) i2c_wr8(sd, ERR_PK_LIMIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) i2c_wr8(sd, NO_PKT_LIMIT2, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) i2c_wr8(sd, NO_GDB_LIMIT, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static void tc358743_initial_setup(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) struct tc358743_platform_data *pdata = &state->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * IR is not supported by this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * CEC is only enabled if needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) i2c_wr16_and_or(sd, SYSCTL, ~(MASK_IRRST | MASK_CECRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) (MASK_IRRST | MASK_CECRST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) tc358743_reset(sd, MASK_CTXRST | MASK_HDMIRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #ifdef CONFIG_VIDEO_TC358743_CEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) tc358743_reset(sd, MASK_CECRST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) tc358743_sleep_mode(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) i2c_wr16(sd, FIFOCTL, pdata->fifo_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) tc358743_set_ref_clk(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) i2c_wr8_and_or(sd, DDC_CTL, ~MASK_DDC5V_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) pdata->ddc5v_delay & MASK_DDC5V_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) i2c_wr8_and_or(sd, EDID_MODE, ~MASK_EDID_MODE, MASK_EDID_MODE_E_DDC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) tc358743_set_hdmi_phy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) tc358743_set_hdmi_hdcp(sd, pdata->enable_hdcp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) tc358743_set_hdmi_audio(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) tc358743_set_hdmi_info_frame_mode(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* All CE and IT formats are detected as RGB full range in DVI mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) i2c_wr8_and_or(sd, VI_MODE, ~MASK_RGB_DVI, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) i2c_wr8_and_or(sd, VOUT_SET2, ~MASK_VOUTCOLORMODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) MASK_VOUTCOLORMODE_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) i2c_wr8(sd, VOUT_SET3, MASK_VOUT_EXTCNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* --------------- CEC --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #ifdef CONFIG_VIDEO_TC358743_CEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static int tc358743_cec_adap_enable(struct cec_adapter *adap, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct tc358743_state *state = adap->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct v4l2_subdev *sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) i2c_wr32(sd, CECIMSK, enable ? MASK_CECTIM | MASK_CECRIM : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) i2c_wr32(sd, CECICLR, MASK_CECTICLR | MASK_CECRICLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) i2c_wr32(sd, CECEN, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) i2c_wr32(sd, CECREN, MASK_CECREN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static int tc358743_cec_adap_monitor_all_enable(struct cec_adapter *adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct tc358743_state *state = adap->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct v4l2_subdev *sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) reg = i2c_rd32(sd, CECRCTL1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) reg |= MASK_CECOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) reg &= ~MASK_CECOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) i2c_wr32(sd, CECRCTL1, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static int tc358743_cec_adap_log_addr(struct cec_adapter *adap, u8 log_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct tc358743_state *state = adap->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct v4l2_subdev *sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) unsigned int la = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (log_addr != CEC_LOG_ADDR_INVALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) la = i2c_rd32(sd, CECADD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) la |= 1 << log_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) i2c_wr32(sd, CECADD, la);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static int tc358743_cec_adap_transmit(struct cec_adapter *adap, u8 attempts,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) u32 signal_free_time, struct cec_msg *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct tc358743_state *state = adap->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct v4l2_subdev *sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) i2c_wr32(sd, CECTCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) (cec_msg_is_broadcast(msg) ? MASK_CECBRD : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) (signal_free_time - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) for (i = 0; i < msg->len; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) i2c_wr32(sd, CECTBUF1 + i * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) msg->msg[i] | ((i == msg->len - 1) ? MASK_CECTEOM : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) i2c_wr32(sd, CECTEN, MASK_CECTEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static const struct cec_adap_ops tc358743_cec_adap_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .adap_enable = tc358743_cec_adap_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .adap_log_addr = tc358743_cec_adap_log_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .adap_transmit = tc358743_cec_adap_transmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) .adap_monitor_all_enable = tc358743_cec_adap_monitor_all_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static void tc358743_cec_handler(struct v4l2_subdev *sd, u16 intstatus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) unsigned int cec_rxint, cec_txint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) unsigned int clr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) cec_rxint = i2c_rd32(sd, CECRSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) cec_txint = i2c_rd32(sd, CECTSTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (intstatus & MASK_CEC_RINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) clr |= MASK_CECRICLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (intstatus & MASK_CEC_TINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) clr |= MASK_CECTICLR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) i2c_wr32(sd, CECICLR, clr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if ((intstatus & MASK_CEC_TINT) && cec_txint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (cec_txint & MASK_CECTIEND)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) cec_transmit_attempt_done(state->cec_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) CEC_TX_STATUS_OK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) else if (cec_txint & MASK_CECTIAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) cec_transmit_attempt_done(state->cec_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) CEC_TX_STATUS_ARB_LOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) else if (cec_txint & MASK_CECTIACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) cec_transmit_attempt_done(state->cec_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) CEC_TX_STATUS_NACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) else if (cec_txint & MASK_CECTIUR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * Not sure when this bit is set. Treat
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * it as an error for now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) cec_transmit_attempt_done(state->cec_adap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) CEC_TX_STATUS_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if ((intstatus & MASK_CEC_RINT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) (cec_rxint & MASK_CECRIEND)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct cec_msg msg = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) unsigned int v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) v = i2c_rd32(sd, CECRCTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) msg.len = v & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) for (i = 0; i < msg.len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) v = i2c_rd32(sd, CECRBUF1 + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) msg.msg[i] = v & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) cec_received_msg(state->cec_adap, &msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) i2c_wr16(sd, INTSTATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) intstatus & (MASK_CEC_RINT | MASK_CEC_TINT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /* --------------- IRQ --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static void tc358743_format_change(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) const struct v4l2_event tc358743_ev_fmt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .type = V4L2_EVENT_SOURCE_CHANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .u.src_change.changes = V4L2_EVENT_SRC_CH_RESOLUTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (tc358743_get_detected_timings(sd, &timings)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) enable_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) v4l2_dbg(1, debug, sd, "%s: No signal\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (!v4l2_match_dv_timings(&state->timings, &timings, 0, false))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) enable_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) v4l2_print_dv_timings(sd->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) "tc358743_format_change: New format: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) &timings, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (sd->devnode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) v4l2_subdev_notify_event(sd, &tc358743_ev_fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) static void tc358743_init_interrupts(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) u16 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* clear interrupt status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) for (i = SYS_INT; i <= KEY_INT; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) i2c_wr8(sd, i, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) i2c_wr16(sd, INTSTATUS, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static void tc358743_enable_interrupts(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) bool cable_connected)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) v4l2_dbg(2, debug, sd, "%s: cable connected = %d\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) cable_connected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (cable_connected) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) i2c_wr8(sd, SYS_INTM, ~(MASK_M_DDC | MASK_M_DVI_DET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) MASK_M_HDMI_DET) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) i2c_wr8(sd, CLK_INTM, ~MASK_M_IN_DE_CHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) i2c_wr8(sd, CBIT_INTM, ~(MASK_M_CBIT_FS | MASK_M_AF_LOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) MASK_M_AF_UNLOCK) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) i2c_wr8(sd, AUDIO_INTM, ~MASK_M_BUFINIT_END);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) i2c_wr8(sd, MISC_INTM, ~MASK_M_SYNC_CHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) i2c_wr8(sd, SYS_INTM, ~MASK_M_DDC & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) i2c_wr8(sd, CLK_INTM, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) i2c_wr8(sd, CBIT_INTM, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) i2c_wr8(sd, AUDIO_INTM, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) i2c_wr8(sd, MISC_INTM, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static void tc358743_hdmi_audio_int_handler(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) u8 audio_int_mask = i2c_rd8(sd, AUDIO_INTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) u8 audio_int = i2c_rd8(sd, AUDIO_INT) & ~audio_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) i2c_wr8(sd, AUDIO_INT, audio_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) v4l2_dbg(3, debug, sd, "%s: AUDIO_INT = 0x%02x\n", __func__, audio_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) tc358743_s_ctrl_audio_sampling_rate(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) tc358743_s_ctrl_audio_present(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static void tc358743_csi_err_int_handler(struct v4l2_subdev *sd, bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) v4l2_err(sd, "%s: CSI_ERR = 0x%x\n", __func__, i2c_rd32(sd, CSI_ERR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) i2c_wr32(sd, CSI_INT_CLR, MASK_ICRER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static void tc358743_hdmi_misc_int_handler(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) u8 misc_int_mask = i2c_rd8(sd, MISC_INTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) u8 misc_int = i2c_rd8(sd, MISC_INT) & ~misc_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) i2c_wr8(sd, MISC_INT, misc_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) v4l2_dbg(3, debug, sd, "%s: MISC_INT = 0x%02x\n", __func__, misc_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (misc_int & MASK_I_SYNC_CHG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* Reset the HDMI PHY to try to trigger proper lock on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * incoming video format. Erase BKSV to prevent that old keys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * are used when a new source is connected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (no_sync(sd) || no_signal(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) tc358743_reset_phy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) tc358743_erase_bksv(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) tc358743_format_change(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) misc_int &= ~MASK_I_SYNC_CHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (misc_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) v4l2_err(sd, "%s: Unhandled MISC_INT interrupts: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) __func__, misc_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static void tc358743_hdmi_cbit_int_handler(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) u8 cbit_int_mask = i2c_rd8(sd, CBIT_INTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) u8 cbit_int = i2c_rd8(sd, CBIT_INT) & ~cbit_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) i2c_wr8(sd, CBIT_INT, cbit_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) v4l2_dbg(3, debug, sd, "%s: CBIT_INT = 0x%02x\n", __func__, cbit_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (cbit_int & MASK_I_CBIT_FS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) v4l2_dbg(1, debug, sd, "%s: Audio sample rate changed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) tc358743_s_ctrl_audio_sampling_rate(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) cbit_int &= ~MASK_I_CBIT_FS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (cbit_int & (MASK_I_AF_LOCK | MASK_I_AF_UNLOCK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) v4l2_dbg(1, debug, sd, "%s: Audio present changed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) tc358743_s_ctrl_audio_present(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) cbit_int &= ~(MASK_I_AF_LOCK | MASK_I_AF_UNLOCK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (cbit_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) v4l2_err(sd, "%s: Unhandled CBIT_INT interrupts: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) __func__, cbit_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static void tc358743_hdmi_clk_int_handler(struct v4l2_subdev *sd, bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) u8 clk_int_mask = i2c_rd8(sd, CLK_INTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) u8 clk_int = i2c_rd8(sd, CLK_INT) & ~clk_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* Bit 7 and bit 6 are set even when they are masked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) i2c_wr8(sd, CLK_INT, clk_int | 0x80 | MASK_I_OUT_H_CHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) v4l2_dbg(3, debug, sd, "%s: CLK_INT = 0x%02x\n", __func__, clk_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (clk_int & (MASK_I_IN_DE_CHG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) v4l2_dbg(1, debug, sd, "%s: DE size or position has changed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /* If the source switch to a new resolution with the same pixel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) * frequency as the existing (e.g. 1080p25 -> 720p50), the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) * I_SYNC_CHG interrupt is not always triggered, while the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) * I_IN_DE_CHG interrupt seems to work fine. Format change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) * notifications are only sent when the signal is stable to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * reduce the number of notifications. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (!no_signal(sd) && !no_sync(sd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) tc358743_format_change(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) clk_int &= ~(MASK_I_IN_DE_CHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (clk_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) v4l2_err(sd, "%s: Unhandled CLK_INT interrupts: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) __func__, clk_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static void tc358743_hdmi_sys_int_handler(struct v4l2_subdev *sd, bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) u8 sys_int_mask = i2c_rd8(sd, SYS_INTM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) u8 sys_int = i2c_rd8(sd, SYS_INT) & ~sys_int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) i2c_wr8(sd, SYS_INT, sys_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) v4l2_dbg(3, debug, sd, "%s: SYS_INT = 0x%02x\n", __func__, sys_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (sys_int & MASK_I_DDC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) bool tx_5v = tx_5v_power_present(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) v4l2_dbg(1, debug, sd, "%s: Tx 5V power present: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) __func__, tx_5v ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (tx_5v) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) tc358743_enable_edid(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) tc358743_enable_interrupts(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) tc358743_disable_edid(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) memset(&state->timings, 0, sizeof(state->timings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) tc358743_erase_bksv(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) tc358743_update_controls(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) sys_int &= ~MASK_I_DDC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (sys_int & MASK_I_DVI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) v4l2_dbg(1, debug, sd, "%s: HDMI->DVI change detected\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* Reset the HDMI PHY to try to trigger proper lock on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * incoming video format. Erase BKSV to prevent that old keys
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) * are used when a new source is connected. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (no_sync(sd) || no_signal(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) tc358743_reset_phy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) tc358743_erase_bksv(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) sys_int &= ~MASK_I_DVI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (sys_int & MASK_I_HDMI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) v4l2_dbg(1, debug, sd, "%s: DVI->HDMI change detected\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) /* Register is reset in DVI mode (REF_01, c. 6.6.41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) i2c_wr8(sd, ANA_CTL, MASK_APPL_PCSX_NORMAL | MASK_ANALOG_ON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) sys_int &= ~MASK_I_HDMI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) *handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (sys_int) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) v4l2_err(sd, "%s: Unhandled SYS_INT interrupts: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) __func__, sys_int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /* --------------- CORE OPS --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) static int tc358743_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct v4l2_dv_timings timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) uint8_t hdmi_sys_status = i2c_rd8(sd, SYS_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) uint16_t sysctl = i2c_rd16(sd, SYSCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) u8 vi_status3 = i2c_rd8(sd, VI_STATUS3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) const int deep_color_mode[4] = { 8, 10, 12, 16 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static const char * const input_color_space[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) "RGB", "YCbCr 601", "opRGB", "YCbCr 709", "NA (4)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) "xvYCC 601", "NA(6)", "xvYCC 709", "NA(8)", "sYCC601",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) "NA(10)", "NA(11)", "NA(12)", "opYCC 601"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) v4l2_info(sd, "-----Chip status-----\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) v4l2_info(sd, "Chip ID: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) (i2c_rd16(sd, CHIPID) & MASK_CHIPID) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) v4l2_info(sd, "Chip revision: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) i2c_rd16(sd, CHIPID) & MASK_REVID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) v4l2_info(sd, "Reset: IR: %d, CEC: %d, CSI TX: %d, HDMI: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) !!(sysctl & MASK_IRRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) !!(sysctl & MASK_CECRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) !!(sysctl & MASK_CTXRST),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) !!(sysctl & MASK_HDMIRST));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) v4l2_info(sd, "Sleep mode: %s\n", sysctl & MASK_SLEEP ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) v4l2_info(sd, "Cable detected (+5V power): %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) hdmi_sys_status & MASK_S_DDC5V ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) v4l2_info(sd, "DDC lines enabled: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) (i2c_rd8(sd, EDID_MODE) & MASK_EDID_MODE_E_DDC) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) v4l2_info(sd, "Hotplug enabled: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) (i2c_rd8(sd, HPD_CTL) & MASK_HPD_OUT0) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) v4l2_info(sd, "CEC enabled: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) (i2c_rd16(sd, CECEN) & MASK_CECEN) ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) v4l2_info(sd, "-----Signal status-----\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) v4l2_info(sd, "TMDS signal detected: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) hdmi_sys_status & MASK_S_TMDS ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) v4l2_info(sd, "Stable sync signal: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) hdmi_sys_status & MASK_S_SYNC ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) v4l2_info(sd, "PHY PLL locked: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) hdmi_sys_status & MASK_S_PHY_PLL ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) v4l2_info(sd, "PHY DE detected: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) hdmi_sys_status & MASK_S_PHY_SCDT ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (tc358743_get_detected_timings(sd, &timings)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) v4l2_info(sd, "No video detected\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) v4l2_print_dv_timings(sd->name, "Detected format: ", &timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) v4l2_print_dv_timings(sd->name, "Configured format: ", &state->timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) v4l2_info(sd, "-----CSI-TX status-----\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) v4l2_info(sd, "Lanes needed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) tc358743_num_csi_lanes_needed(sd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) v4l2_info(sd, "Lanes in use: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) state->csi_lanes_in_use);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) v4l2_info(sd, "Waiting for particular sync signal: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) (i2c_rd16(sd, CSI_STATUS) & MASK_S_WSYNC) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) v4l2_info(sd, "Transmit mode: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) (i2c_rd16(sd, CSI_STATUS) & MASK_S_TXACT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) v4l2_info(sd, "Receive mode: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) (i2c_rd16(sd, CSI_STATUS) & MASK_S_RXACT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) v4l2_info(sd, "Stopped: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) (i2c_rd16(sd, CSI_STATUS) & MASK_S_HLT) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) v4l2_info(sd, "Color space: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) state->mbus_fmt_code == MEDIA_BUS_FMT_UYVY8_1X16 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) "YCbCr 422 16-bit" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) state->mbus_fmt_code == MEDIA_BUS_FMT_RGB888_1X24 ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) "RGB 888 24-bit" : "Unsupported");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) v4l2_info(sd, "HDCP encrypted content: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) hdmi_sys_status & MASK_S_HDCP ? "yes" : "no");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) v4l2_info(sd, "Input color space: %s %s range\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) input_color_space[(vi_status3 & MASK_S_V_COLOR) >> 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) (vi_status3 & MASK_LIMITED) ? "limited" : "full");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (!is_hdmi(sd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) v4l2_info(sd, "AV Mute: %s\n", hdmi_sys_status & MASK_S_AVMUTE ? "on" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) v4l2_info(sd, "Deep color mode: %d-bits per channel\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) deep_color_mode[(i2c_rd8(sd, VI_STATUS1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) MASK_S_DEEPCOLOR) >> 2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) print_avi_infoframe(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) static void tc358743_print_register_map(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) v4l2_info(sd, "0x0000-0x00FF: Global Control Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) v4l2_info(sd, "0x0100-0x01FF: CSI2-TX PHY Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) v4l2_info(sd, "0x0200-0x03FF: CSI2-TX PPI Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) v4l2_info(sd, "0x0400-0x05FF: Reserved\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) v4l2_info(sd, "0x0600-0x06FF: CEC Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) v4l2_info(sd, "0x0700-0x84FF: Reserved\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) v4l2_info(sd, "0x8500-0x85FF: HDMIRX System Control Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) v4l2_info(sd, "0x8600-0x86FF: HDMIRX Audio Control Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) v4l2_info(sd, "0x8700-0x87FF: HDMIRX InfoFrame packet data Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) v4l2_info(sd, "0x8800-0x88FF: HDMIRX HDCP Port Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) v4l2_info(sd, "0x8900-0x89FF: HDMIRX Video Output Port & 3D Register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) v4l2_info(sd, "0x8A00-0x8BFF: Reserved\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) v4l2_info(sd, "0x8C00-0x8FFF: HDMIRX EDID-RAM (1024bytes)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) v4l2_info(sd, "0x9000-0x90FF: HDMIRX GBD Extraction Control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) v4l2_info(sd, "0x9100-0x92FF: HDMIRX GBD RAM read\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) v4l2_info(sd, "0x9300- : Reserved\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static int tc358743_get_reg_size(u16 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) /* REF_01 p. 66-72 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (address <= 0x00ff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) else if ((address >= 0x0100) && (address <= 0x06FF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) else if ((address >= 0x0700) && (address <= 0x84ff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static int tc358743_g_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (reg->reg > 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) tc358743_print_register_map(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) reg->size = tc358743_get_reg_size(reg->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) reg->val = i2c_rdreg(sd, reg->reg, reg->size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static int tc358743_s_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (reg->reg > 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) tc358743_print_register_map(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) /* It should not be possible for the user to enable HDCP with a simple
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * v4l2-dbg command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * DO NOT REMOVE THIS unless all other issues with HDCP have been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * resolved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (reg->reg == HDCP_MODE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) reg->reg == HDCP_REG1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) reg->reg == HDCP_REG2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) reg->reg == HDCP_REG3 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) reg->reg == BCAPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) i2c_wrreg(sd, (u16)reg->reg, reg->val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) tc358743_get_reg_size(reg->reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) static int tc358743_isr(struct v4l2_subdev *sd, u32 status, bool *handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) u16 intstatus = i2c_rd16(sd, INTSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) v4l2_dbg(1, debug, sd, "%s: IntStatus = 0x%04x\n", __func__, intstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (intstatus & MASK_HDMI_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) u8 hdmi_int0 = i2c_rd8(sd, HDMI_INT0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) u8 hdmi_int1 = i2c_rd8(sd, HDMI_INT1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (hdmi_int0 & MASK_I_MISC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) tc358743_hdmi_misc_int_handler(sd, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (hdmi_int1 & MASK_I_CBIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) tc358743_hdmi_cbit_int_handler(sd, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (hdmi_int1 & MASK_I_CLK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) tc358743_hdmi_clk_int_handler(sd, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (hdmi_int1 & MASK_I_SYS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) tc358743_hdmi_sys_int_handler(sd, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (hdmi_int1 & MASK_I_AUD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) tc358743_hdmi_audio_int_handler(sd, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) i2c_wr16(sd, INTSTATUS, MASK_HDMI_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) intstatus &= ~MASK_HDMI_INT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #ifdef CONFIG_VIDEO_TC358743_CEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (intstatus & (MASK_CEC_RINT | MASK_CEC_TINT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) tc358743_cec_handler(sd, intstatus, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) i2c_wr16(sd, INTSTATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) intstatus & (MASK_CEC_RINT | MASK_CEC_TINT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) intstatus &= ~(MASK_CEC_RINT | MASK_CEC_TINT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (intstatus & MASK_CSI_INT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) u32 csi_int = i2c_rd32(sd, CSI_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (csi_int & MASK_INTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) tc358743_csi_err_int_handler(sd, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) i2c_wr16(sd, INTSTATUS, MASK_CSI_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) intstatus = i2c_rd16(sd, INTSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (intstatus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) "%s: Unhandled IntStatus interrupts: 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) __func__, intstatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static irqreturn_t tc358743_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) struct tc358743_state *state = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) bool handled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) tc358743_isr(&state->sd, 0, &handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return handled ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static void tc358743_irq_poll_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) struct tc358743_state *state = from_timer(state, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) unsigned int msecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) schedule_work(&state->work_i2c_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) * If CEC is present, then we need to poll more frequently,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) * otherwise we will miss CEC messages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) msecs = state->cec_adap ? POLL_INTERVAL_CEC_MS : POLL_INTERVAL_MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) mod_timer(&state->timer, jiffies + msecs_to_jiffies(msecs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static void tc358743_work_i2c_poll(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) struct tc358743_state *state = container_of(work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct tc358743_state, work_i2c_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) bool handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) tc358743_isr(&state->sd, 0, &handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) static int tc358743_subscribe_event(struct v4l2_subdev *sd, struct v4l2_fh *fh,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) struct v4l2_event_subscription *sub)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) switch (sub->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) case V4L2_EVENT_SOURCE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) case V4L2_EVENT_CTRL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) /* --------------- VIDEO OPS --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static int tc358743_g_input_status(struct v4l2_subdev *sd, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) *status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) *status |= no_signal(sd) ? V4L2_IN_ST_NO_SIGNAL : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) *status |= no_sync(sd) ? V4L2_IN_ST_NO_SYNC : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) v4l2_dbg(1, debug, sd, "%s: status = 0x%x\n", __func__, *status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) static int tc358743_s_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (!timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) v4l2_print_dv_timings(sd->name, "tc358743_s_dv_timings: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) timings, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) if (!v4l2_valid_dv_timings(timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) &tc358743_timings_cap, NULL, NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) state->timings = *timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) enable_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) tc358743_set_pll(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) tc358743_set_csi(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) static int tc358743_g_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) *timings = state->timings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) static int tc358743_enum_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) struct v4l2_enum_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (timings->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) return v4l2_enum_dv_timings_cap(timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) &tc358743_timings_cap, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) static int tc358743_query_dv_timings(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) struct v4l2_dv_timings *timings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) ret = tc358743_get_detected_timings(sd, timings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) v4l2_print_dv_timings(sd->name, "tc358743_query_dv_timings: ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) timings, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (!v4l2_valid_dv_timings(timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) &tc358743_timings_cap, NULL, NULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) v4l2_dbg(1, debug, sd, "%s: timings out of range\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static int tc358743_dv_timings_cap(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) struct v4l2_dv_timings_cap *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) if (cap->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) *cap = tc358743_timings_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) static int tc358743_get_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) struct v4l2_mbus_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) cfg->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) /* Support for non-continuous CSI-2 clock is missing in the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) cfg->flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) switch (state->csi_lanes_in_use) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) cfg->flags |= V4L2_MBUS_CSI2_1_LANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) cfg->flags |= V4L2_MBUS_CSI2_2_LANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) cfg->flags |= V4L2_MBUS_CSI2_3_LANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) cfg->flags |= V4L2_MBUS_CSI2_4_LANE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) static int tc358743_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) enable_stream(sd, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) if (!enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) /* Put all lanes in LP-11 state (STOPSTATE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) tc358743_set_csi(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) /* --------------- PAD OPS --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) static int tc358743_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) switch (code->index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) code->code = MEDIA_BUS_FMT_RGB888_1X24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) code->code = MEDIA_BUS_FMT_UYVY8_1X16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) static int tc358743_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) u8 vi_rep = i2c_rd8(sd, VI_REP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (format->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) format->format.code = state->mbus_fmt_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) format->format.width = state->timings.bt.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) format->format.height = state->timings.bt.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) format->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) switch (vi_rep & MASK_VOUT_COLOR_SEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) case MASK_VOUT_COLOR_RGB_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) case MASK_VOUT_COLOR_RGB_LIMITED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) format->format.colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) case MASK_VOUT_COLOR_601_YCBCR_LIMITED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) case MASK_VOUT_COLOR_601_YCBCR_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) case MASK_VOUT_COLOR_709_YCBCR_FULL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) case MASK_VOUT_COLOR_709_YCBCR_LIMITED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) format->format.colorspace = V4L2_COLORSPACE_REC709;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) format->format.colorspace = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) static int tc358743_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) u32 code = format->format.code; /* is overwritten by get_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) int ret = tc358743_get_fmt(sd, cfg, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) format->format.code = code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) switch (code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) case MEDIA_BUS_FMT_RGB888_1X24:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) case MEDIA_BUS_FMT_UYVY8_1X16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (format->which == V4L2_SUBDEV_FORMAT_TRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) state->mbus_fmt_code = format->format.code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) enable_stream(sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) tc358743_set_pll(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) tc358743_set_csi(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) tc358743_set_csi_color_space(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) static int tc358743_g_edid(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) struct v4l2_subdev_edid *edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) memset(edid->reserved, 0, sizeof(edid->reserved));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) if (edid->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) if (edid->start_block == 0 && edid->blocks == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) edid->blocks = state->edid_blocks_written;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) if (state->edid_blocks_written == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) return -ENODATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) if (edid->start_block >= state->edid_blocks_written ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) edid->blocks == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) if (edid->start_block + edid->blocks > state->edid_blocks_written)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) edid->blocks = state->edid_blocks_written - edid->start_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) i2c_rd(sd, EDID_RAM + (edid->start_block * EDID_BLOCK_SIZE), edid->edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) edid->blocks * EDID_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) static int tc358743_s_edid(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) struct v4l2_subdev_edid *edid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) u16 edid_len = edid->blocks * EDID_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) u16 pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) v4l2_dbg(2, debug, sd, "%s, pad %d, start block %d, blocks %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) __func__, edid->pad, edid->start_block, edid->blocks);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) memset(edid->reserved, 0, sizeof(edid->reserved));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (edid->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) if (edid->start_block != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) if (edid->blocks > EDID_NUM_BLOCKS_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) edid->blocks = EDID_NUM_BLOCKS_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) return -E2BIG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) pa = cec_get_edid_phys_addr(edid->edid, edid->blocks * 128, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) err = v4l2_phys_addr_validate(pa, &pa, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) cec_phys_addr_invalidate(state->cec_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) tc358743_disable_edid(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) i2c_wr8(sd, EDID_LEN1, edid_len & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) i2c_wr8(sd, EDID_LEN2, edid_len >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) if (edid->blocks == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) state->edid_blocks_written = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) for (i = 0; i < edid_len; i += EDID_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) i2c_wr(sd, EDID_RAM + i, edid->edid + i, EDID_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) state->edid_blocks_written = edid->blocks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) cec_s_phys_addr(state->cec_adap, pa, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) if (tx_5v_power_present(sd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) tc358743_enable_edid(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) /* -------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) static const struct v4l2_subdev_core_ops tc358743_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) .log_status = tc358743_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .g_register = tc358743_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) .s_register = tc358743_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) .interrupt_service_routine = tc358743_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) .subscribe_event = tc358743_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .unsubscribe_event = v4l2_event_subdev_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) static const struct v4l2_subdev_video_ops tc358743_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .g_input_status = tc358743_g_input_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .s_dv_timings = tc358743_s_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .g_dv_timings = tc358743_g_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .query_dv_timings = tc358743_query_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .s_stream = tc358743_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) static const struct v4l2_subdev_pad_ops tc358743_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .enum_mbus_code = tc358743_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .set_fmt = tc358743_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .get_fmt = tc358743_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .get_edid = tc358743_g_edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .set_edid = tc358743_s_edid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .enum_dv_timings = tc358743_enum_dv_timings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .dv_timings_cap = tc358743_dv_timings_cap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .get_mbus_config = tc358743_get_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) static const struct v4l2_subdev_ops tc358743_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .core = &tc358743_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .video = &tc358743_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .pad = &tc358743_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) /* --------------- CUSTOM CTRLS --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) static const struct v4l2_ctrl_config tc358743_ctrl_audio_sampling_rate = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .id = TC358743_CID_AUDIO_SAMPLING_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) .name = "Audio sampling rate",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) .type = V4L2_CTRL_TYPE_INTEGER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .max = 768000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) .step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) .def = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) .flags = V4L2_CTRL_FLAG_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) static const struct v4l2_ctrl_config tc358743_ctrl_audio_present = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .id = TC358743_CID_AUDIO_PRESENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .name = "Audio present",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .type = V4L2_CTRL_TYPE_BOOLEAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .min = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .max = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .step = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .def = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .flags = V4L2_CTRL_FLAG_READ_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) /* --------------- PROBE / REMOVE --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) static void tc358743_gpio_reset(struct tc358743_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) gpiod_set_value(state->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) gpiod_set_value(state->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) static int tc358743_probe_of(struct tc358743_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) struct device *dev = &state->i2c_client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) struct v4l2_fwnode_endpoint endpoint = { .bus_type = 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) struct device_node *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) struct clk *refclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) u32 bps_pr_lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) refclk = devm_clk_get(dev, "refclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) if (IS_ERR(refclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) if (PTR_ERR(refclk) != -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) dev_err(dev, "failed to get refclk: %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) PTR_ERR(refclk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) return PTR_ERR(refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) ep = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) if (!ep) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) dev_err(dev, "missing endpoint node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) ret = v4l2_fwnode_endpoint_alloc_parse(of_fwnode_handle(ep), &endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) dev_err(dev, "failed to parse endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) goto put_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) if (endpoint.bus_type != V4L2_MBUS_CSI2_DPHY ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) endpoint.bus.mipi_csi2.num_data_lanes == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) endpoint.nr_of_link_frequencies == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) dev_err(dev, "missing CSI-2 properties in endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) goto free_endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (endpoint.bus.mipi_csi2.num_data_lanes > 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) dev_err(dev, "invalid number of lanes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) goto free_endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) state->bus = endpoint.bus.mipi_csi2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) ret = clk_prepare_enable(refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) dev_err(dev, "Failed! to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) goto free_endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) state->pdata.refclk_hz = clk_get_rate(refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) state->pdata.enable_hdcp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) state->pdata.fifo_level = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) * The PLL input clock is obtained by dividing refclk by pll_prd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) * It must be between 6 MHz and 40 MHz, lower frequency is better.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) switch (state->pdata.refclk_hz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) case 26000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) case 27000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) case 42000000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) state->pdata.pll_prd = state->pdata.refclk_hz / 6000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) dev_err(dev, "unsupported refclk rate: %u Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) state->pdata.refclk_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) * The CSI bps per lane must be between 62.5 Mbps and 1 Gbps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) * The default is 594 Mbps for 4-lane 1080p60 or 2-lane 720p60.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) bps_pr_lane = 2 * endpoint.link_frequencies[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) if (bps_pr_lane < 62500000U || bps_pr_lane > 1000000000U) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) dev_err(dev, "unsupported bps per lane: %u bps\n", bps_pr_lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) /* The CSI speed per lane is refclk / pll_prd * pll_fbd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) state->pdata.pll_fbd = bps_pr_lane /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) state->pdata.refclk_hz * state->pdata.pll_prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) * FIXME: These timings are from REF_02 for 594 Mbps per lane (297 MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) * link frequency). In principle it should be possible to calculate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) * them based on link frequency and resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) if (bps_pr_lane != 594000000U)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) dev_warn(dev, "untested bps per lane: %u bps\n", bps_pr_lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) state->pdata.lineinitcnt = 0xe80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) state->pdata.lptxtimecnt = 0x003;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) /* tclk-preparecnt: 3, tclk-zerocnt: 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) state->pdata.tclk_headercnt = 0x1403;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) state->pdata.tclk_trailcnt = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) /* ths-preparecnt: 3, ths-zerocnt: 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) state->pdata.ths_headercnt = 0x0103;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) state->pdata.twakeup = 0x4882;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) state->pdata.tclk_postcnt = 0x008;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) state->pdata.ths_trailcnt = 0x2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) state->pdata.hstxvregcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) state->reset_gpio = devm_gpiod_get_optional(dev, "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) if (IS_ERR(state->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) dev_err(dev, "failed to get reset gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) ret = PTR_ERR(state->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) if (state->reset_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) tc358743_gpio_reset(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) goto free_endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) clk_disable_unprepare(refclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) free_endpoint:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) v4l2_fwnode_endpoint_free(&endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) put_node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) of_node_put(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) static inline int tc358743_probe_of(struct tc358743_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) static int tc358743_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) static struct v4l2_dv_timings default_timing =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) V4L2_DV_BT_CEA_640X480P59_94;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) struct tc358743_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) struct tc358743_platform_data *pdata = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) u16 irq_mask = MASK_HDMI_MSK | MASK_CSI_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) v4l_dbg(1, debug, client, "chip found @ 0x%x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) state = devm_kzalloc(&client->dev, sizeof(struct tc358743_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) if (!state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) state->i2c_client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) /* platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) state->pdata = *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) state->bus.flags = V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) err = tc358743_probe_of(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) if (err == -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) v4l_err(client, "No platform data!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) v4l2_i2c_subdev_init(sd, client, &tc358743_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) /* i2c access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) if ((i2c_rd16(sd, CHIPID) & MASK_CHIPID) != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) v4l2_info(sd, "not a TC358743 on address 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) client->addr << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) /* control handlers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) v4l2_ctrl_handler_init(&state->hdl, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(&state->hdl, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) V4L2_CID_DV_RX_POWER_PRESENT, 0, 1, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) /* custom controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) state->audio_sampling_rate_ctrl = v4l2_ctrl_new_custom(&state->hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) &tc358743_ctrl_audio_sampling_rate, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) state->audio_present_ctrl = v4l2_ctrl_new_custom(&state->hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) &tc358743_ctrl_audio_present, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) sd->ctrl_handler = &state->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) if (state->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) err = state->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) if (tc358743_update_controls(sd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) state->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) err = media_entity_pads_init(&sd->entity, 1, &state->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) state->mbus_fmt_code = MEDIA_BUS_FMT_RGB888_1X24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) sd->dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) err = v4l2_async_register_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) mutex_init(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) tc358743_delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) #ifdef CONFIG_VIDEO_TC358743_CEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) state->cec_adap = cec_allocate_adapter(&tc358743_cec_adap_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) state, dev_name(&client->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) CEC_CAP_DEFAULTS | CEC_CAP_MONITOR_ALL, CEC_MAX_LOG_ADDRS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) if (IS_ERR(state->cec_adap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) err = PTR_ERR(state->cec_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) goto err_hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) irq_mask |= MASK_CEC_RMSK | MASK_CEC_TMSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) tc358743_initial_setup(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) tc358743_s_dv_timings(sd, &default_timing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) tc358743_set_csi_color_space(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) tc358743_init_interrupts(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) if (state->i2c_client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) err = devm_request_threaded_irq(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) state->i2c_client->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) NULL, tc358743_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) "tc358743", state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) goto err_work_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) INIT_WORK(&state->work_i2c_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) tc358743_work_i2c_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) timer_setup(&state->timer, tc358743_irq_poll_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) state->timer.expires = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) msecs_to_jiffies(POLL_INTERVAL_MS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) add_timer(&state->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) err = cec_register_adapter(state->cec_adap, &client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) pr_err("%s: failed to register the cec device\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) cec_delete_adapter(state->cec_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) state->cec_adap = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) goto err_work_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) tc358743_enable_interrupts(sd, tx_5v_power_present(sd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) i2c_wr16(sd, INTMASK, ~irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) err = v4l2_ctrl_handler_setup(sd->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) goto err_work_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) err_work_queues:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) cec_unregister_adapter(state->cec_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) if (!state->i2c_client->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) flush_work(&state->work_i2c_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) cancel_delayed_work(&state->delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) mutex_destroy(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) err_hdl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) v4l2_ctrl_handler_free(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) static int tc358743_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) struct tc358743_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) if (!state->i2c_client->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) del_timer_sync(&state->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) flush_work(&state->work_i2c_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) cec_unregister_adapter(state->cec_adap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) mutex_destroy(&state->confctl_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) v4l2_ctrl_handler_free(&state->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) static const struct i2c_device_id tc358743_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) {"tc358743", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) MODULE_DEVICE_TABLE(i2c, tc358743_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) static const struct of_device_id tc358743_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) { .compatible = "toshiba,tc358743" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) MODULE_DEVICE_TABLE(of, tc358743_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) static struct i2c_driver tc358743_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) .name = "tc358743",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) .of_match_table = of_match_ptr(tc358743_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) .probe_new = tc358743_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) .remove = tc358743_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) .id_table = tc358743_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) module_i2c_driver(tc358743_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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