^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for SiliconFile SR030PC30 VGA (1/10-Inch) Image Sensor with ISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Samsung Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Sylwester Nawrocki, s.nawrocki@samsung.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on original driver authored by Dongsoo Nathaniel Kim
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * and HeungJun Kim <riverful.kim@samsung.com>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Based on mt9v011 Micron Digital Image Sensor driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (c) 2009 Mauro Carvalho Chehab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/i2c/sr030pc30.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MODULE_NAME "SR030PC30"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Register offsets within a page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * b15..b8 - page id, b7..b0 - register address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define POWER_CTRL_REG 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PAGEMODE_REG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DEVICE_ID_REG 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NOON010PC30_ID 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SR030PC30_ID 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define VDO_CTL1_REG 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SUBSAMPL_NONE_VGA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SUBSAMPL_QVGA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SUBSAMPL_QQVGA 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define VDO_CTL2_REG 0x0011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SYNC_CTL_REG 0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define WIN_ROWH_REG 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define WIN_ROWL_REG 0x0021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define WIN_COLH_REG 0x0022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define WIN_COLL_REG 0x0023
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define WIN_HEIGHTH_REG 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define WIN_HEIGHTL_REG 0x0025
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define WIN_WIDTHH_REG 0x0026
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define WIN_WIDTHL_REG 0x0027
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HBLANKH_REG 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HBLANKL_REG 0x0041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define VSYNCH_REG 0x0042
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define VSYNCL_REG 0x0043
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* page 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ISP_CTL_REG(n) (0x1010 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define YOFS_REG 0x1040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DARK_YOFS_REG 0x1041
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AG_ABRTH_REG 0x1050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SAT_CTL_REG 0x1060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BSAT_REG 0x1061
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define RSAT_REG 0x1062
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AG_SAT_TH_REG 0x1063
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* page 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ZLPF_CTRL_REG 0x1110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ZLPF_CTRL2_REG 0x1112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ZLPF_AGH_THR_REG 0x1121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ZLPF_THR_REG 0x1160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ZLPF_DYN_THR_REG 0x1160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* page 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define YCLPF_CTL1_REG 0x1240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define YCLPF_CTL2_REG 0x1241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define YCLPF_THR_REG 0x1250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BLPF_CTL_REG 0x1270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BLPF_THR1_REG 0x1274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BLPF_THR2_REG 0x1275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* page 14 - Lens Shading Compensation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define LENS_CTRL_REG 0x1410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define LENS_XCEN_REG 0x1420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LENS_YCEN_REG 0x1421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LENS_R_COMP_REG 0x1422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LENS_G_COMP_REG 0x1423
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LENS_B_COMP_REG 0x1424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* page 15 - Color correction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CMC_CTL_REG 0x1510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CMC_OFSGH_REG 0x1514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CMC_OFSGL_REG 0x1516
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CMC_SIGN_REG 0x1517
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Color correction coefficients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CMC_COEF_REG(n) (0x1530 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Color correction offset coefficients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CMC_OFS_REG(n) (0x1540 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* page 16 - Gamma correction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GMA_CTL_REG 0x1610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Gamma correction coefficients 0.14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GMA_COEF_REG(n) (0x1630 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* page 20 - Auto Exposure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define AE_CTL1_REG 0x2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define AE_CTL2_REG 0x2011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define AE_FRM_CTL_REG 0x2020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define AE_FINE_CTL_REG(n) (0x2028 + (n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define EXP_TIMEH_REG 0x2083
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define EXP_TIMEM_REG 0x2084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define EXP_TIMEL_REG 0x2085
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define EXP_MMINH_REG 0x2086
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define EXP_MMINL_REG 0x2087
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define EXP_MMAXH_REG 0x2088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define EXP_MMAXM_REG 0x2089
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define EXP_MMAXL_REG 0x208A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* page 22 - Auto White Balance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AWB_CTL1_REG 0x2210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AWB_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AWB_CTL2_REG 0x2211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MWB_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* RGB gain control (manual WB) when AWB_CTL1[7]=0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AWB_RGAIN_REG 0x2280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define AWB_GGAIN_REG 0x2281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define AWB_BGAIN_REG 0x2282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AWB_RMAX_REG 0x2283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AWB_RMIN_REG 0x2284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AWB_BMAX_REG 0x2285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define AWB_BMIN_REG 0x2286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* R, B gain range in bright light conditions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AWB_RMAXB_REG 0x2287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AWB_RMINB_REG 0x2288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AWB_BMAXB_REG 0x2289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AWB_BMINB_REG 0x228A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* manual white balance, when AWB_CTL2[0]=1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MWB_RGAIN_REG 0x22B2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MWB_BGAIN_REG 0x22B3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* the token to mark an array end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define REG_TERM 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Minimum and maximum exposure time in ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define EXPOS_MIN_MS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define EXPOS_MAX_MS 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct sr030pc30_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const struct sr030pc30_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) const struct sr030pc30_format *curr_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const struct sr030pc30_frmsize *curr_win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int hflip:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int vflip:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int sleep:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* auto whitebalance control cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct v4l2_ctrl *awb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct v4l2_ctrl *red;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct v4l2_ctrl *blue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* auto exposure control cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct v4l2_ctrl *autoexp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct v4l2_ctrl *exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u8 i2c_reg_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct sr030pc30_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) enum v4l2_colorspace colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u16 ispctl1_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct sr030pc30_frmsize {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u16 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u16 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int vid_ctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct i2c_regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* supported resolutions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static const struct sr030pc30_frmsize sr030pc30_sizes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) .width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .vid_ctl1 = SUBSAMPL_NONE_VGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .width = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .height = 240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .vid_ctl1 = SUBSAMPL_QVGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .width = 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .height = 120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .vid_ctl1 = SUBSAMPL_QQVGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* supported pixel formats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct sr030pc30_format sr030pc30_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .code = MEDIA_BUS_FMT_YUYV8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .ispctl1_reg = 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .code = MEDIA_BUS_FMT_YVYU8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .ispctl1_reg = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .code = MEDIA_BUS_FMT_VYUY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .ispctl1_reg = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .code = MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .ispctl1_reg = 0x01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .colorspace = V4L2_COLORSPACE_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .ispctl1_reg = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct i2c_regval sr030pc30_base_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Window size and position within pixel matrix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { WIN_ROWH_REG, 0x00 }, { WIN_ROWL_REG, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { WIN_COLH_REG, 0x00 }, { WIN_COLL_REG, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { WIN_HEIGHTH_REG, 0x01 }, { WIN_HEIGHTL_REG, 0xE0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { WIN_WIDTHH_REG, 0x02 }, { WIN_WIDTHL_REG, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { HBLANKH_REG, 0x01 }, { HBLANKL_REG, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { VSYNCH_REG, 0x00 }, { VSYNCL_REG, 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { SYNC_CTL_REG, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Color corection and saturation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { ISP_CTL_REG(0), 0x30 }, { YOFS_REG, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { DARK_YOFS_REG, 0x04 }, { AG_ABRTH_REG, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { SAT_CTL_REG, 0x1F }, { BSAT_REG, 0x90 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { AG_SAT_TH_REG, 0xF0 }, { 0x1064, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { CMC_CTL_REG, 0x03 }, { CMC_OFSGH_REG, 0x3C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { CMC_OFSGL_REG, 0x2C }, { CMC_SIGN_REG, 0x2F },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { CMC_COEF_REG(0), 0xCB }, { CMC_OFS_REG(0), 0x87 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { CMC_COEF_REG(1), 0x61 }, { CMC_OFS_REG(1), 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { CMC_COEF_REG(2), 0x16 }, { CMC_OFS_REG(2), 0x91 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { CMC_COEF_REG(3), 0x23 }, { CMC_OFS_REG(3), 0x94 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { CMC_COEF_REG(4), 0xCE }, { CMC_OFS_REG(4), 0x9f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { CMC_COEF_REG(5), 0x2B }, { CMC_OFS_REG(5), 0x33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { CMC_COEF_REG(6), 0x01 }, { CMC_OFS_REG(6), 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { CMC_COEF_REG(7), 0x34 }, { CMC_OFS_REG(7), 0x94 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { CMC_COEF_REG(8), 0x75 }, { CMC_OFS_REG(8), 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Color corection coefficients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { GMA_CTL_REG, 0x03 }, { GMA_COEF_REG(0), 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { GMA_COEF_REG(1), 0x19 }, { GMA_COEF_REG(2), 0x26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { GMA_COEF_REG(3), 0x3B }, { GMA_COEF_REG(4), 0x5D },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { GMA_COEF_REG(5), 0x79 }, { GMA_COEF_REG(6), 0x8E },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { GMA_COEF_REG(7), 0x9F }, { GMA_COEF_REG(8), 0xAF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { GMA_COEF_REG(9), 0xBD }, { GMA_COEF_REG(10), 0xCA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { GMA_COEF_REG(11), 0xDD }, { GMA_COEF_REG(12), 0xEC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { GMA_COEF_REG(13), 0xF7 }, { GMA_COEF_REG(14), 0xFF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* Noise reduction, Z-LPF, YC-LPF and BLPF filters setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { ZLPF_CTRL_REG, 0x99 }, { ZLPF_CTRL2_REG, 0x0E },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { ZLPF_AGH_THR_REG, 0x29 }, { ZLPF_THR_REG, 0x0F },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { ZLPF_DYN_THR_REG, 0x63 }, { YCLPF_CTL1_REG, 0x23 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { YCLPF_CTL2_REG, 0x3B }, { YCLPF_THR_REG, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { BLPF_CTL_REG, 0x1D }, { BLPF_THR1_REG, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { BLPF_THR2_REG, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Automatic white balance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { AWB_CTL1_REG, 0xFB }, { AWB_CTL2_REG, 0x26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { AWB_RMAX_REG, 0x54 }, { AWB_RMIN_REG, 0x2B },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { AWB_BMAX_REG, 0x57 }, { AWB_BMIN_REG, 0x29 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { AWB_RMAXB_REG, 0x50 }, { AWB_RMINB_REG, 0x43 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { AWB_BMAXB_REG, 0x30 }, { AWB_BMINB_REG, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Auto exposure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { AE_CTL1_REG, 0x8C }, { AE_CTL2_REG, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { AE_FRM_CTL_REG, 0x01 }, { AE_FINE_CTL_REG(0), 0x3F },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { AE_FINE_CTL_REG(1), 0xA3 }, { AE_FINE_CTL_REG(3), 0x34 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* Lens shading compensation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { LENS_CTRL_REG, 0x01 }, { LENS_XCEN_REG, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { LENS_YCEN_REG, 0x70 }, { LENS_R_COMP_REG, 0x53 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { LENS_G_COMP_REG, 0x40 }, { LENS_B_COMP_REG, 0x3e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { REG_TERM, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static inline struct sr030pc30_info *to_sr030pc30(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return container_of(sd, struct sr030pc30_info, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static inline int set_i2c_page(struct sr030pc30_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct i2c_client *client, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 page = reg >> 8 & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (info->i2c_reg_page != page && (reg & 0xFF) != 0x03) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) ret = i2c_smbus_write_byte_data(client, PAGEMODE_REG, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) info->i2c_reg_page = page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) static int cam_i2c_read(struct v4l2_subdev *sd, u32 reg_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct sr030pc30_info *info = to_sr030pc30(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int ret = set_i2c_page(info, client, reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = i2c_smbus_read_byte_data(client, reg_addr & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static int cam_i2c_write(struct v4l2_subdev *sd, u32 reg_addr, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct sr030pc30_info *info = to_sr030pc30(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int ret = set_i2c_page(info, client, reg_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ret = i2c_smbus_write_byte_data(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) client, reg_addr & 0xFF, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) static inline int sr030pc30_bulk_write_reg(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) const struct i2c_regval *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) while (msg->addr != REG_TERM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int ret = cam_i2c_write(sd, msg->addr, msg->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) msg++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Device reset and sleep mode control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) static int sr030pc30_pwr_ctrl(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) bool reset, bool sleep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct sr030pc30_info *info = to_sr030pc30(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u8 reg = sleep ? 0xF1 : 0xF0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) ret = cam_i2c_write(sd, POWER_CTRL_REG, reg | 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = cam_i2c_write(sd, POWER_CTRL_REG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) info->sleep = sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (reset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) info->i2c_reg_page = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int sr030pc30_set_flip(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct sr030pc30_info *info = to_sr030pc30(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) s32 reg = cam_i2c_read(sd, VDO_CTL2_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (reg < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) reg &= 0x7C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (info->hflip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) reg |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (info->vflip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) reg |= 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return cam_i2c_write(sd, VDO_CTL2_REG, reg | 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Configure resolution, color format and image flip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static int sr030pc30_set_params(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct sr030pc30_info *info = to_sr030pc30(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (!info->curr_win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Configure the resolution through subsampling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ret = cam_i2c_write(sd, VDO_CTL1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) info->curr_win->vid_ctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (!ret && info->curr_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ret = cam_i2c_write(sd, ISP_CTL_REG(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) info->curr_fmt->ispctl1_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = sr030pc30_set_flip(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* Find nearest matching image pixel size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) static int sr030pc30_try_frame_size(struct v4l2_mbus_framefmt *mf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned int min_err = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int i = ARRAY_SIZE(sr030pc30_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) const struct sr030pc30_frmsize *fsize = &sr030pc30_sizes[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) *match = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) while (i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int err = abs(fsize->width - mf->width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) + abs(fsize->height - mf->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (err < min_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) min_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) match = fsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) fsize++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) mf->width = match->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mf->height = match->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int sr030pc30_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct sr030pc30_info *info =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) container_of(ctrl->handler, struct sr030pc30_info, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct v4l2_subdev *sd = &info->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) v4l2_dbg(1, debug, sd, "%s: ctrl_id: %d, value: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) case V4L2_CID_AUTO_WHITE_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (ctrl->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) ret = cam_i2c_write(sd, AWB_CTL2_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ctrl->val ? 0x2E : 0x2F);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ret = cam_i2c_write(sd, AWB_CTL1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ctrl->val ? 0xFB : 0x7B);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!ret && info->blue->is_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) ret = cam_i2c_write(sd, MWB_BGAIN_REG, info->blue->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!ret && info->red->is_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ret = cam_i2c_write(sd, MWB_RGAIN_REG, info->red->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case V4L2_CID_EXPOSURE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* auto anti-flicker is also enabled here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (ctrl->is_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ret = cam_i2c_write(sd, AE_CTL1_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ctrl->val == V4L2_EXPOSURE_AUTO ? 0xDC : 0x0C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if (info->exp->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned long expos = info->exp->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) expos = expos * info->pdata->clk_rate / (8 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ret = cam_i2c_write(sd, EXP_TIMEH_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) expos >> 16 & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) ret = cam_i2c_write(sd, EXP_TIMEM_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) expos >> 8 & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ret = cam_i2c_write(sd, EXP_TIMEL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) expos & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int sr030pc30_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (!code || code->pad ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) code->index >= ARRAY_SIZE(sr030pc30_formats))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) code->code = sr030pc30_formats[code->index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static int sr030pc30_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) struct v4l2_mbus_framefmt *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct sr030pc30_info *info = to_sr030pc30(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (!format || format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (!info->curr_win || !info->curr_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) mf->width = info->curr_win->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) mf->height = info->curr_win->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) mf->code = info->curr_fmt->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) mf->colorspace = info->curr_fmt->colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Return nearest media bus frame format. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static const struct sr030pc30_format *try_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct v4l2_mbus_framefmt *mf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) sr030pc30_try_frame_size(mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) for (i = 0; i < ARRAY_SIZE(sr030pc30_formats); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (mf->code == sr030pc30_formats[i].code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (i == ARRAY_SIZE(sr030pc30_formats))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) mf->code = sr030pc30_formats[i].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return &sr030pc30_formats[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Return nearest media bus frame format. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int sr030pc30_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct sr030pc30_info *info = sd ? to_sr030pc30(sd) : NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) const struct sr030pc30_format *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct v4l2_mbus_framefmt *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (!sd || !format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) fmt = try_fmt(sd, mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) cfg->try_fmt = *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) info->curr_fmt = fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return sr030pc30_set_params(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int sr030pc30_base_config(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct sr030pc30_info *info = to_sr030pc30(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned long expmin, expmax;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = sr030pc30_bulk_write_reg(sd, sr030pc30_base_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) info->curr_fmt = &sr030pc30_formats[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) info->curr_win = &sr030pc30_sizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = sr030pc30_set_params(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret = sr030pc30_pwr_ctrl(sd, false, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) expmin = EXPOS_MIN_MS * info->pdata->clk_rate / (8 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) expmax = EXPOS_MAX_MS * info->pdata->clk_rate / (8 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) v4l2_dbg(1, debug, sd, "%s: expmin= %lx, expmax= %lx", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) expmin, expmax);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Setting up manual exposure time range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret = cam_i2c_write(sd, EXP_MMINH_REG, expmin >> 8 & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) ret = cam_i2c_write(sd, EXP_MMINL_REG, expmin & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = cam_i2c_write(sd, EXP_MMAXH_REG, expmax >> 16 & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = cam_i2c_write(sd, EXP_MMAXM_REG, expmax >> 8 & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = cam_i2c_write(sd, EXP_MMAXL_REG, expmax & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int sr030pc30_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct sr030pc30_info *info = to_sr030pc30(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) const struct sr030pc30_platform_data *pdata = info->pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (pdata == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) WARN(1, "No platform data!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) * Put sensor into power sleep mode before switching off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) * power and disabling MCLK.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) sr030pc30_pwr_ctrl(sd, false, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* set_power controls sensor's power and clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (pdata->set_power) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = pdata->set_power(&client->dev, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) ret = sr030pc30_base_config(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) info->curr_win = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) info->curr_fmt = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) static const struct v4l2_ctrl_ops sr030pc30_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) .s_ctrl = sr030pc30_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static const struct v4l2_subdev_core_ops sr030pc30_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .s_power = sr030pc30_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static const struct v4l2_subdev_pad_ops sr030pc30_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .enum_mbus_code = sr030pc30_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .get_fmt = sr030pc30_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .set_fmt = sr030pc30_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static const struct v4l2_subdev_ops sr030pc30_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .core = &sr030pc30_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .pad = &sr030pc30_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) * Detect sensor type. Return 0 if SR030PC30 was detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * or -ENODEV otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int sr030pc30_detect(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) const struct sr030pc30_platform_data *pdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* Enable sensor's power and clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (pdata->set_power) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) ret = pdata->set_power(&client->dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ret = i2c_smbus_read_byte_data(client, DEVICE_ID_REG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (pdata->set_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) pdata->set_power(&client->dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dev_err(&client->dev, "%s: I2C read failed\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return ret == SR030PC30_ID ? 0 : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int sr030pc30_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct sr030pc30_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct v4l2_ctrl_handler *hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) const struct sr030pc30_platform_data *pdata
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (!pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) dev_err(&client->dev, "No platform data!");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ret = sr030pc30_detect(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (!info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) sd = &info->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) info->pdata = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) v4l2_i2c_subdev_init(sd, client, &sr030pc30_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) hdl = &info->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) v4l2_ctrl_handler_init(hdl, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) info->awb = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) info->red = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) V4L2_CID_RED_BALANCE, 0, 127, 1, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) info->blue = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) V4L2_CID_BLUE_BALANCE, 0, 127, 1, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) info->autoexp = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) V4L2_CID_EXPOSURE_AUTO, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) info->exp = v4l2_ctrl_new_std(hdl, &sr030pc30_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) V4L2_CID_EXPOSURE, EXPOS_MIN_MS, EXPOS_MAX_MS, 1, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) sd->ctrl_handler = hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (hdl->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) int err = hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) v4l2_ctrl_handler_free(hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) v4l2_ctrl_auto_cluster(3, &info->awb, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) v4l2_ctrl_auto_cluster(2, &info->autoexp, V4L2_EXPOSURE_MANUAL, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) v4l2_ctrl_handler_setup(hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) info->i2c_reg_page = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) info->hflip = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static int sr030pc30_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) v4l2_ctrl_handler_free(sd->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static const struct i2c_device_id sr030pc30_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) { MODULE_NAME, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) MODULE_DEVICE_TABLE(i2c, sr030pc30_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static struct i2c_driver sr030pc30_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .name = MODULE_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .probe = sr030pc30_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .remove = sr030pc30_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .id_table = sr030pc30_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) module_i2c_driver(sr030pc30_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) MODULE_DESCRIPTION("Siliconfile SR030PC30 camera driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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