Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * drivers/media/i2c/smiapp-pll.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Generic driver for SMIA/SMIA++ compliant camera modules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (C) 2012 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Contact: Sakari Ailus <sakari.ailus@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef SMIAPP_PLL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SMIAPP_PLL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* CSI-2 or CCP-2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SMIAPP_PLL_BUS_TYPE_CSI2				0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SMIAPP_PLL_BUS_TYPE_PARALLEL				0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* op pix clock is for all lanes in total normally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE			(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SMIAPP_PLL_FLAG_NO_OP_CLOCKS				(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct smiapp_pll_branch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	uint16_t sys_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	uint16_t pix_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	uint32_t sys_clk_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	uint32_t pix_clk_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) struct smiapp_pll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	/* input values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	uint8_t bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			uint8_t lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		} csi2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			uint8_t bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		} parallel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	uint8_t binning_horizontal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	uint8_t binning_vertical;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	uint8_t scale_m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	uint8_t scale_n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	uint8_t bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	uint32_t link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	uint32_t ext_clk_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	/* output values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	uint16_t pre_pll_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	uint16_t pll_multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	uint32_t pll_ip_clk_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	uint32_t pll_op_clk_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	struct smiapp_pll_branch vt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	struct smiapp_pll_branch op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	uint32_t pixel_rate_csi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	uint32_t pixel_rate_pixel_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) struct smiapp_pll_branch_limits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	uint16_t min_sys_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	uint16_t max_sys_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	uint32_t min_sys_clk_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	uint32_t max_sys_clk_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	uint16_t min_pix_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	uint16_t max_pix_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	uint32_t min_pix_clk_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	uint32_t max_pix_clk_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct smiapp_pll_limits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	/* Strict PLL limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	uint32_t min_ext_clk_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 	uint32_t max_ext_clk_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 	uint16_t min_pre_pll_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 	uint16_t max_pre_pll_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	uint32_t min_pll_ip_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 	uint32_t max_pll_ip_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	uint16_t min_pll_multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	uint16_t max_pll_multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 	uint32_t min_pll_op_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	uint32_t max_pll_op_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) 	struct smiapp_pll_branch_limits vt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 	struct smiapp_pll_branch_limits op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) 	/* Other relevant limits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 	uint32_t min_line_length_pck_bin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 	uint32_t min_line_length_pck;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) int smiapp_pll_calculate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) 			 const struct smiapp_pll_limits *limits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) 			 struct smiapp_pll *pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #endif /* SMIAPP_PLL_H */