^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/media/i2c/smiapp-pll.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Generic driver for SMIA/SMIA++ compliant camera modules
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2011--2012 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Contact: Sakari Ailus <sakari.ailus@iki.fi>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gcd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/lcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "smiapp-pll.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Return an even number or one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) static inline uint32_t clk_div_even(uint32_t a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) return max_t(uint32_t, 1, a & ~1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Return an even number or one. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static inline uint32_t clk_div_even_up(uint32_t a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) if (a == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) return (a + 1) & ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static inline uint32_t is_one_or_even(uint32_t a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) if (a == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (a & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static int bounds_check(struct device *dev, uint32_t val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) uint32_t min, uint32_t max, char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) if (val >= min && val <= max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) dev_dbg(dev, "%s out of bounds: %d (%d--%d)\n", str, val, min, max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static void print_pll(struct device *dev, struct smiapp_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) dev_dbg(dev, "pre_pll_clk_div\t%u\n", pll->pre_pll_clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) dev_dbg(dev, "pll_multiplier \t%u\n", pll->pll_multiplier);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) dev_dbg(dev, "op_sys_clk_div \t%u\n", pll->op.sys_clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) dev_dbg(dev, "op_pix_clk_div \t%u\n", pll->op.pix_clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) dev_dbg(dev, "vt_sys_clk_div \t%u\n", pll->vt.sys_clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) dev_dbg(dev, "vt_pix_clk_div \t%u\n", pll->vt.pix_clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) dev_dbg(dev, "ext_clk_freq_hz \t%u\n", pll->ext_clk_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) dev_dbg(dev, "pll_ip_clk_freq_hz \t%u\n", pll->pll_ip_clk_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) dev_dbg(dev, "pll_op_clk_freq_hz \t%u\n", pll->pll_op_clk_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) if (!(pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) dev_dbg(dev, "op_sys_clk_freq_hz \t%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pll->op.sys_clk_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) dev_dbg(dev, "op_pix_clk_freq_hz \t%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pll->op.pix_clk_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) dev_dbg(dev, "vt_sys_clk_freq_hz \t%u\n", pll->vt.sys_clk_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) dev_dbg(dev, "vt_pix_clk_freq_hz \t%u\n", pll->vt.pix_clk_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static int check_all_bounds(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) const struct smiapp_pll_limits *limits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) const struct smiapp_pll_branch_limits *op_limits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct smiapp_pll *pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct smiapp_pll_branch *op_pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) rval = bounds_check(dev, pll->pll_ip_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) limits->min_pll_ip_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) limits->max_pll_ip_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) "pll_ip_clk_freq_hz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) if (!rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) rval = bounds_check(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) dev, pll->pll_multiplier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) limits->min_pll_multiplier, limits->max_pll_multiplier,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "pll_multiplier");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) if (!rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) rval = bounds_check(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev, pll->pll_op_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) limits->min_pll_op_freq_hz, limits->max_pll_op_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) "pll_op_clk_freq_hz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (!rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) rval = bounds_check(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) dev, op_pll->sys_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) op_limits->min_sys_clk_div, op_limits->max_sys_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "op_sys_clk_div");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (!rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) rval = bounds_check(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dev, op_pll->sys_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) op_limits->min_sys_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) op_limits->max_sys_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "op_sys_clk_freq_hz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (!rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) rval = bounds_check(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) dev, op_pll->pix_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) op_limits->min_pix_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) op_limits->max_pix_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "op_pix_clk_freq_hz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * If there are no OP clocks, the VT clocks are contained in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * the OP clock struct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (!rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) rval = bounds_check(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dev, pll->vt.sys_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) limits->vt.min_sys_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) limits->vt.max_sys_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) "vt_sys_clk_freq_hz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) rval = bounds_check(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dev, pll->vt.pix_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) limits->vt.min_pix_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) limits->vt.max_pix_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "vt_pix_clk_freq_hz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Heuristically guess the PLL tree for a given common multiplier and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * divisor. Begin with the operational timing and continue to video
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * timing once operational timing has been verified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @mul is the PLL multiplier and @div is the common divisor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * multiplier will be a multiple of @mul.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @return Zero on success, error code on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static int __smiapp_pll_calculate(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct device *dev, const struct smiapp_pll_limits *limits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const struct smiapp_pll_branch_limits *op_limits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct smiapp_pll *pll, struct smiapp_pll_branch *op_pll, uint32_t mul,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) uint32_t div, uint32_t lane_op_clock_ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) uint32_t sys_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) uint32_t best_pix_div = INT_MAX >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) uint32_t vt_op_binning_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Higher multipliers (and divisors) are often required than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * necessitated by the external clock and the output clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * There are limits for all values in the clock tree. These
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * are the minimum and maximum multiplier for mul.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) uint32_t more_mul_min, more_mul_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) uint32_t more_mul_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) uint32_t min_vt_div, max_vt_div, vt_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) uint32_t min_sys_div, max_sys_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Get pre_pll_clk_div so that our pll_op_clk_freq_hz won't be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * too high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) dev_dbg(dev, "pre_pll_clk_div %u\n", pll->pre_pll_clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Don't go above max pll multiplier. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) more_mul_max = limits->max_pll_multiplier / mul;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dev_dbg(dev, "more_mul_max: max_pll_multiplier check: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) more_mul_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Don't go above max pll op frequency. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) more_mul_max =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) min_t(uint32_t,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) more_mul_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) limits->max_pll_op_freq_hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) / (pll->ext_clk_freq_hz / pll->pre_pll_clk_div * mul));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dev_dbg(dev, "more_mul_max: max_pll_op_freq_hz check: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) more_mul_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Don't go above the division capability of op sys clock divider. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) more_mul_max = min(more_mul_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) op_limits->max_sys_clk_div * pll->pre_pll_clk_div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) / div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) dev_dbg(dev, "more_mul_max: max_op_sys_clk_div check: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) more_mul_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Ensure we won't go above min_pll_multiplier. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) more_mul_max = min(more_mul_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) DIV_ROUND_UP(limits->max_pll_multiplier, mul));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_dbg(dev, "more_mul_max: min_pll_multiplier check: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) more_mul_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Ensure we won't go below min_pll_op_freq_hz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) more_mul_min = DIV_ROUND_UP(limits->min_pll_op_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) pll->ext_clk_freq_hz / pll->pre_pll_clk_div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * mul);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) dev_dbg(dev, "more_mul_min: min_pll_op_freq_hz check: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) more_mul_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Ensure we won't go below min_pll_multiplier. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) more_mul_min = max(more_mul_min,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) DIV_ROUND_UP(limits->min_pll_multiplier, mul));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dev_dbg(dev, "more_mul_min: min_pll_multiplier check: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) more_mul_min);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) if (more_mul_min > more_mul_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "unable to compute more_mul_min and more_mul_max\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) more_mul_factor = lcm(div, pll->pre_pll_clk_div) / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_dbg(dev, "more_mul_factor: %u\n", more_mul_factor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) more_mul_factor = lcm(more_mul_factor, op_limits->min_sys_clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) dev_dbg(dev, "more_mul_factor: min_op_sys_clk_div: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) more_mul_factor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) i = roundup(more_mul_min, more_mul_factor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!is_one_or_even(i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) i <<= 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) dev_dbg(dev, "final more_mul: %u\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) if (i > more_mul_max) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) dev_dbg(dev, "final more_mul is bad, max %u\n", more_mul_max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) pll->pll_multiplier = mul * i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) op_pll->sys_clk_div = div * i / pll->pre_pll_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dev_dbg(dev, "op_sys_clk_div: %u\n", op_pll->sys_clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) pll->pll_ip_clk_freq_hz = pll->ext_clk_freq_hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) / pll->pre_pll_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) pll->pll_op_clk_freq_hz = pll->pll_ip_clk_freq_hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * pll->pll_multiplier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* Derive pll_op_clk_freq_hz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) op_pll->sys_clk_freq_hz =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) pll->pll_op_clk_freq_hz / op_pll->sys_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) op_pll->pix_clk_div = pll->bits_per_pixel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_dbg(dev, "op_pix_clk_div: %u\n", op_pll->pix_clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) op_pll->pix_clk_freq_hz =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) op_pll->sys_clk_freq_hz / op_pll->pix_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* No OP clocks --- VT clocks are used instead. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) goto out_skip_vt_calc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Some sensors perform analogue binning and some do this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * digitally. The ones doing this digitally can be roughly be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * found out using this formula. The ones doing this digitally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * should run at higher clock rate, so smaller divisor is used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * on video timing side.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (limits->min_line_length_pck_bin > limits->min_line_length_pck
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) / pll->binning_horizontal)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) vt_op_binning_div = pll->binning_horizontal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) vt_op_binning_div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dev_dbg(dev, "vt_op_binning_div: %u\n", vt_op_binning_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * Profile 2 supports vt_pix_clk_div E [4, 10]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * Horizontal binning can be used as a base for difference in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * divisors. One must make sure that horizontal blanking is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * enough to accommodate the CSI-2 sync codes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * Take scaling factor into account as well.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * Find absolute limits for the factor of vt divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev_dbg(dev, "scale_m: %u\n", pll->scale_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) min_vt_div = DIV_ROUND_UP(op_pll->pix_clk_div * op_pll->sys_clk_div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * pll->scale_n,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) lane_op_clock_ratio * vt_op_binning_div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * pll->scale_m);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* Find smallest and biggest allowed vt divisor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) dev_dbg(dev, "min_vt_div: %u\n", min_vt_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) min_vt_div = max(min_vt_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) limits->vt.max_pix_clk_freq_hz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dev_dbg(dev, "min_vt_div: max_vt_pix_clk_freq_hz: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) min_vt_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) min_vt_div = max_t(uint32_t, min_vt_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) limits->vt.min_pix_clk_div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * limits->vt.min_sys_clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev_dbg(dev, "min_vt_div: min_vt_clk_div: %u\n", min_vt_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) max_vt_div = limits->vt.max_sys_clk_div * limits->vt.max_pix_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev_dbg(dev, "max_vt_div: %u\n", max_vt_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) max_vt_div = min(max_vt_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) limits->vt.min_pix_clk_freq_hz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev_dbg(dev, "max_vt_div: min_vt_pix_clk_freq_hz: %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) max_vt_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * Find limitsits for sys_clk_div. Not all values are possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * with all values of pix_clk_div.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) min_sys_div = limits->vt.min_sys_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev_dbg(dev, "min_sys_div: %u\n", min_sys_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) min_sys_div = max(min_sys_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) DIV_ROUND_UP(min_vt_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) limits->vt.max_pix_clk_div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev_dbg(dev, "min_sys_div: max_vt_pix_clk_div: %u\n", min_sys_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) min_sys_div = max(min_sys_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) pll->pll_op_clk_freq_hz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) / limits->vt.max_sys_clk_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_dbg(dev, "min_sys_div: max_pll_op_clk_freq_hz: %u\n", min_sys_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) min_sys_div = clk_div_even_up(min_sys_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dev_dbg(dev, "min_sys_div: one or even: %u\n", min_sys_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) max_sys_div = limits->vt.max_sys_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dev_dbg(dev, "max_sys_div: %u\n", max_sys_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) max_sys_div = min(max_sys_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) DIV_ROUND_UP(max_vt_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) limits->vt.min_pix_clk_div));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dev_dbg(dev, "max_sys_div: min_vt_pix_clk_div: %u\n", max_sys_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) max_sys_div = min(max_sys_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) DIV_ROUND_UP(pll->pll_op_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) limits->vt.min_pix_clk_freq_hz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dev_dbg(dev, "max_sys_div: min_vt_pix_clk_freq_hz: %u\n", max_sys_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * Find pix_div such that a legal pix_div * sys_div results
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * into a value which is not smaller than div, the desired
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * divisor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) for (vt_div = min_vt_div; vt_div <= max_vt_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) vt_div += 2 - (vt_div & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) for (sys_div = min_sys_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) sys_div <= max_sys_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) sys_div += 2 - (sys_div & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) uint16_t pix_div = DIV_ROUND_UP(vt_div, sys_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (pix_div < limits->vt.min_pix_clk_div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) || pix_div > limits->vt.max_pix_clk_div) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dev_dbg(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) "pix_div %u too small or too big (%u--%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) pix_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) limits->vt.min_pix_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) limits->vt.max_pix_clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Check if this one is better. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (pix_div * sys_div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) <= roundup(min_vt_div, best_pix_div))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) best_pix_div = pix_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (best_pix_div < INT_MAX >> 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) pll->vt.sys_clk_div = DIV_ROUND_UP(min_vt_div, best_pix_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) pll->vt.pix_clk_div = best_pix_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) pll->vt.sys_clk_freq_hz =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) pll->pll_op_clk_freq_hz / pll->vt.sys_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) pll->vt.pix_clk_freq_hz =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) pll->vt.sys_clk_freq_hz / pll->vt.pix_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) out_skip_vt_calc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) pll->pixel_rate_csi =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) op_pll->pix_clk_freq_hz * lane_op_clock_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) pll->pixel_rate_pixel_array = pll->vt.pix_clk_freq_hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return check_all_bounds(dev, limits, op_limits, pll, op_pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) int smiapp_pll_calculate(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) const struct smiapp_pll_limits *limits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct smiapp_pll *pll)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) const struct smiapp_pll_branch_limits *op_limits = &limits->op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct smiapp_pll_branch *op_pll = &pll->op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) uint16_t min_pre_pll_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) uint16_t max_pre_pll_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) uint32_t lane_op_clock_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) uint32_t mul, div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int rval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (pll->flags & SMIAPP_PLL_FLAG_NO_OP_CLOCKS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * If there's no OP PLL at all, use the VT values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * instead. The OP values are ignored for the rest of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * the PLL calculation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) op_limits = &limits->vt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) op_pll = &pll->vt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (pll->flags & SMIAPP_PLL_FLAG_OP_PIX_CLOCK_PER_LANE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) lane_op_clock_ratio = pll->csi2.lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) lane_op_clock_ratio = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dev_dbg(dev, "lane_op_clock_ratio: %u\n", lane_op_clock_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev_dbg(dev, "binning: %ux%u\n", pll->binning_horizontal,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) pll->binning_vertical);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) switch (pll->bus_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) case SMIAPP_PLL_BUS_TYPE_CSI2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* CSI transfers 2 bits per clock per lane; thus times 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) pll->pll_op_clk_freq_hz = pll->link_freq * 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * (pll->csi2.lanes / lane_op_clock_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) case SMIAPP_PLL_BUS_TYPE_PARALLEL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) pll->pll_op_clk_freq_hz = pll->link_freq * pll->bits_per_pixel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) / DIV_ROUND_UP(pll->bits_per_pixel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) pll->parallel.bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* Figure out limits for pre-pll divider based on extclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dev_dbg(dev, "min / max pre_pll_clk_div: %u / %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) limits->min_pre_pll_clk_div, limits->max_pre_pll_clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) max_pre_pll_clk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) min_t(uint16_t, limits->max_pre_pll_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) clk_div_even(pll->ext_clk_freq_hz /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) limits->min_pll_ip_freq_hz));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) min_pre_pll_clk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) max_t(uint16_t, limits->min_pre_pll_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) clk_div_even_up(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) DIV_ROUND_UP(pll->ext_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) limits->max_pll_ip_freq_hz)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dev_dbg(dev, "pre-pll check: min / max pre_pll_clk_div: %u / %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) min_pre_pll_clk_div, max_pre_pll_clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) i = gcd(pll->pll_op_clk_freq_hz, pll->ext_clk_freq_hz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) mul = div_u64(pll->pll_op_clk_freq_hz, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) div = pll->ext_clk_freq_hz / i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_dbg(dev, "mul %u / div %u\n", mul, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) min_pre_pll_clk_div =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) max_t(uint16_t, min_pre_pll_clk_div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) clk_div_even_up(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) DIV_ROUND_UP(mul * pll->ext_clk_freq_hz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) limits->max_pll_op_freq_hz)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dev_dbg(dev, "pll_op check: min / max pre_pll_clk_div: %u / %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) min_pre_pll_clk_div, max_pre_pll_clk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) for (pll->pre_pll_clk_div = min_pre_pll_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) pll->pre_pll_clk_div <= max_pre_pll_clk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pll->pre_pll_clk_div += 2 - (pll->pre_pll_clk_div & 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) rval = __smiapp_pll_calculate(dev, limits, op_limits, pll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) op_pll, mul, div,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) lane_op_clock_ratio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (rval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) print_pll(dev, pll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_dbg(dev, "unable to compute pre_pll divisor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) EXPORT_SYMBOL_GPL(smiapp_pll_calculate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MODULE_AUTHOR("Sakari Ailus <sakari.ailus@iki.fi>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) MODULE_DESCRIPTION("Generic SMIA/SMIA++ PLL calculator");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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