^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sc500ai driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X01 fix set vflip/hflip failed bug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SC500AI_LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SC500AI_LINK_FREQ_198M 198000000 // 396Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SC500AI_LINK_FREQ_405M 405000000 // 810Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SC500AI_MAX_PIXEL_RATE (SC500AI_LINK_FREQ_405M / 10 * 2 * SC500AI_LANES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SC500AI_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SC500AI_CHIP_ID 0xce1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SC500AI_REG_CHIP_ID 0x3107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SC500AI_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SC500AI_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SC500AI_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC500AI_REG_EXPOSURE_H 0x3e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SC500AI_REG_EXPOSURE_M 0x3e01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SC500AI_REG_EXPOSURE_L 0x3e02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SC500AI_EXPOSURE_MIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define sc500ai_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SC500AI_REG_DIG_GAIN 0x3e06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SC500AI_REG_DIG_FINE_GAIN 0x3e07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SC500AI_REG_ANA_GAIN 0x3e08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SC500AI_REG_ANA_FINE_GAIN 0x3e09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SC500AI_GAIN_MIN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SC500AI_GAIN_MAX 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SC500AI_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC500AI_GAIN_DEFAULT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SC500AI_REG_VTS_H 0x320e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SC500AI_REG_VTS_L 0x320f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SC500AI_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SC500AI_SOFTWARE_RESET_REG 0x0103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) // short frame exposure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SC500AI_REG_SHORT_EXPOSURE_H 0x3e22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SC500AI_REG_SHORT_EXPOSURE_M 0x3e04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SC500AI_REG_SHORT_EXPOSURE_L 0x3e05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SC500AI_REG_MAX_SHORT_EXP_H 0x3e23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SC500AI_REG_MAX_SHORT_EXP_L 0x3e24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SC500AI_HDR_EXPOSURE_MIN 5 // Half line exposure time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SC500AI_HDR_EXPOSURE_STEP 4 // Half line exposure time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SC500AI_MAX_SHORT_EXPOSURE 608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) // short frame gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SC500AI_REG_SDIG_GAIN 0x3e10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SC500AI_REG_SDIG_FINE_GAIN 0x3e11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SC500AI_REG_SANA_GAIN 0x3e12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SC500AI_REG_SANA_FINE_GAIN 0x3e13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) //group hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SC500AI_GROUP_UPDATE_ADDRESS 0x3812
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SC500AI_GROUP_UPDATE_START_DATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SC500AI_GROUP_UPDATE_LAUNCH 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SC500AI_FLIP_MIRROR_REG 0x3221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SC500AI_FLIP_MASK 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SC500AI_MIRROR_MASK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SC500AI_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SC500AI_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SC500AI_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SC500AI_NAME "sc500ai"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SC500AI_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SC500AI_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SC500AI_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const char * const sc500ai_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define sc500ai_NUM_SUPPLIES ARRAY_SIZE(sc500ai_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct sc500ai_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 mipi_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct sc500ai {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct regulator_bulk_data supplies[sc500ai_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct v4l2_fract cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) const struct sc500ai_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define to_sc500ai(sd) container_of(sd, struct sc500ai, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * mipi_datarate per lane 1008Mbps, 4lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static const struct regval sc500ai_linear_10_2880x1620_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x301f, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3250, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3253, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3301, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3302, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3303, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3304, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3306, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3308, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3309, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x330b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x330d, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x330e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x330f, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3310, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x331c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x331e, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x331f, 0x61},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3320, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3333, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x334c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3356, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3364, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x336d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3390, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3391, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3392, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3393, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3394, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3395, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3396, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3397, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3398, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3399, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x339a, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x339b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x339c, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x33ac, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x33ae, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x33af, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x360f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3622, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x363a, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x363c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3651, 0x7d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x3670, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3671, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3672, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3673, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3674, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3675, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3676, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x367a, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x367b, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x367c, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x367d, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3690, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3691, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3692, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x369c, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x369d, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x36ea, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x36eb, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x36ec, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x36ed, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x36fa, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x36fb, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x36fc, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x36fd, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3904, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3908, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x391d, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x39c2, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3e01, 0xcd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3e02, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x3e16, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3e17, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x4500, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x4509, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x4800, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x5799, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x59e0, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x59e1, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x59e2, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x59e3, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x59e4, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x59e5, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x59e7, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x59e8, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x59e9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x59ea, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x59ec, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x59ed, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x59ee, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x59ef, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x59f4, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x59f5, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x59f6, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x59f9, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x59fa, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x59fb, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x59fc, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x59ff, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x36e9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x36f9, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct regval sc500ai_hdr_10_2880x1620_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x301f, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x3106, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x320e, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x320f, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x3220, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3250, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3253, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3301, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x3302, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x3303, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x3304, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x3306, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x3308, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x3309, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x330b, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x330d, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x330e, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x330f, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x3310, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x331c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x331e, 0x61},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x331f, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x3320, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x3333, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x334c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x3356, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x3364, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x336d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x3390, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x3391, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x3392, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x3393, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x3394, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x3395, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x3396, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x3397, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x3398, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x3399, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x339a, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x339b, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x339c, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x33ac, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x33ae, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x33af, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x360f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x3621, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x3622, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x3630, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x3633, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x3634, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x3637, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x363a, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x363c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x3651, 0x7d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x3670, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x3671, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x3672, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x3673, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x3674, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x3675, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x3676, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x367a, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x367b, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x367c, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x367d, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x3690, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x3691, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x3692, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x369c, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x369d, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x36ea, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x36eb, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x36ec, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x36ed, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x36fa, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x36fb, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x36fc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x36fd, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x3904, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x3908, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x391f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x39c2, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x3e00, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x3e01, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x3e02, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x3e04, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x3e05, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x3e23, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x3e24, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x4500, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x4509, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x4800, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x4837, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x4853, 0xfd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x36e9, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x36f9, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const struct sc500ai_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .width = 2880,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .height = 1620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .exp_def = 0xcda / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .hts_def = 0xb40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .vts_def = 0x0672,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .reg_list = sc500ai_linear_10_2880x1620_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) .width = 2880,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) .height = 1620,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .exp_def = 0x18c0 / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .hts_def = 0xb40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) .vts_def = 0x0d30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .reg_list = sc500ai_hdr_10_2880x1620_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static const s64 link_freq_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) SC500AI_LINK_FREQ_198M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) SC500AI_LINK_FREQ_405M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int sc500ai_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static int sc500ai_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ret = sc500ai_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) SC500AI_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int sc500ai_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static int sc500ai_get_reso_dist(const struct sc500ai_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) static const struct sc500ai_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) sc500ai_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dist = sc500ai_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int sc500ai_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct sc500ai *sc500ai = to_sc500ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) const struct sc500ai_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mutex_lock(&sc500ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mode = sc500ai_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) mutex_unlock(&sc500ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) sc500ai->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) __v4l2_ctrl_modify_range(sc500ai->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) __v4l2_ctrl_modify_range(sc500ai->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) SC500AI_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) __v4l2_ctrl_s_ctrl(sc500ai->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * SC500AI_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) __v4l2_ctrl_s_ctrl_int64(sc500ai->pixel_rate, pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) sc500ai->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) sc500ai->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) mutex_unlock(&sc500ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int sc500ai_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct sc500ai *sc500ai = to_sc500ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) const struct sc500ai_mode *mode = sc500ai->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) mutex_lock(&sc500ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mutex_unlock(&sc500ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* format info: width/height/data type/virctual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) mutex_unlock(&sc500ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int sc500ai_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct sc500ai *sc500ai = to_sc500ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) code->code = sc500ai->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static int sc500ai_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (fse->code != supported_modes[0].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static int sc500ai_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct sc500ai *sc500ai = to_sc500ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) const struct sc500ai_mode *mode = sc500ai->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (sc500ai->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) fi->interval = sc500ai->cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) static int sc500ai_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct sc500ai *sc500ai = to_sc500ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) const struct sc500ai_mode *mode = sc500ai->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u32 val = 1 << (SC500AI_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) val |= V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) val |= V4L2_MBUS_CSI2_CHANNEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static void sc500ai_get_module_inf(struct sc500ai *sc500ai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) strlcpy(inf->base.sensor, SC500AI_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) strlcpy(inf->base.module, sc500ai->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) strlcpy(inf->base.lens, sc500ai->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static int sc500ai_set_hightemp_dpc(struct sc500ai *sc500ai, u32 total_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (total_gain <= 0x500) { // 20x gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ret = sc500ai_write_reg(sc500ai->client, 0x5799, SC500AI_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) } else if(total_gain >= 0x780) { // 30x gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ret = sc500ai_write_reg(sc500ai->client, 0x5799, SC500AI_REG_VALUE_08BIT, 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static int sc500ai_get_gain_reg(u32 total_gain, u32* again, u32* again_fine, u32* dgain, u32* dgain_fine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u32 step = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (total_gain <= 0x60) { /* 1 - 1.5x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) step = total_gain - 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) *again = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) *again_fine = step + 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) *dgain_fine = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) } else if (total_gain <= 0xc0) { /* 1.5x - 3x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) step = (total_gain - 0x60) * 64 / 0x60 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) *again = 0x23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) *again_fine = step + 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) *dgain_fine = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) } else if (total_gain <= 0x180) { /* 3x - 6x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) step = (total_gain - 0xc0) * 64 / 0xc0 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) *again = 0x27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) *again_fine = step + 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) *dgain_fine = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) } else if (total_gain <= 0x300) { /* 6x - 12x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) step = (total_gain - 0x180) * 64 / 0x180 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) *again = 0x2f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) *again_fine = step + 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) *dgain_fine = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) } else if (total_gain <= 0x600) { /* 12x - 24x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) step = (total_gain - 0x300) * 64 / 0x300 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) *again = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) *again_fine = step + 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) *dgain_fine = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) } else if (total_gain <= 0xc00) { /* 24x - 48x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) step = (total_gain - 0x600) * 128 / 0x600 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) *again = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) *again_fine = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) *dgain_fine = 0x80 + step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) } else if (total_gain <= 0x1800) { /* 48x - 96x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) step = (total_gain - 0xc00) * 128 / 0xc00 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) *again = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) *again_fine = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) *dgain = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) *dgain_fine = 0x80 + step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) } else if (total_gain <= 0x3000) { /* 96x - 192x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) step = (total_gain - 0x1800) * 128 / 0x1800 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) *again = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) *again_fine = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) *dgain = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) *dgain_fine = 0x80 + step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) } else if (total_gain <= 0x6000) { /* 192x - 384x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) step = (total_gain - 0x3000) * 128 / 0x3000 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) *again = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) *again_fine = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) *dgain = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) *dgain_fine = 0x80 + step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) } else if (total_gain <= 0xc000) { /* 384x - 768x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) step = (total_gain - 0x6000) * 128 / 0x6000 - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) *again = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) *again_fine = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) *dgain = 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) *dgain_fine = 0x80 + step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static int sc500ai_set_hdrae(struct sc500ai *sc500ai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u32 l_t_gain, m_t_gain, s_t_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) u32 l_again = 0 , l_again_fine = 0, l_dgain = 0, l_dgain_fine = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u32 s_again = 0, s_again_fine = 0, s_dgain = 0, s_dgain_fine = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (!sc500ai->has_init_exp && !sc500ai->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) sc500ai->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) sc500ai->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) dev_dbg(&sc500ai->client->dev, "sc500ai don't stream, record exp for hdr!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) l_t_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) m_t_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) s_t_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) dev_dbg(&sc500ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) "rev exp req: L_exp: 0x%x, M_exp: 0x%x, S_exp: 0x%x, L_tgain: 0x%x, M_tgain: 0x%x, S_tgain: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) l_exp_time, m_exp_time, s_exp_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) l_t_gain, m_t_gain, s_t_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (sc500ai->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) //2 stagger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) l_t_gain = m_t_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) l_exp_time = m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) l_exp_time = l_exp_time << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) s_exp_time = s_exp_time << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (s_t_gain != l_t_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) dev_err(&sc500ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) "line mode: Long and short frame gains must be equal, l_t_gain: 0x%x, s_t_gain: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) l_t_gain, s_t_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (s_exp_time > SC500AI_MAX_SHORT_EXPOSURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dev_err(&sc500ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) "set short exp error, s_exp_time: 0x%x, max_short_exp: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) s_exp_time, SC500AI_MAX_SHORT_EXPOSURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) // set exposure reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) SC500AI_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) SC500AI_FETCH_EXP_H(l_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) SC500AI_REG_EXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) SC500AI_FETCH_EXP_M(l_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) SC500AI_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) SC500AI_FETCH_EXP_L(l_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) SC500AI_REG_SHORT_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) SC500AI_FETCH_EXP_H(s_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) SC500AI_REG_SHORT_EXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) SC500AI_FETCH_EXP_M(s_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) SC500AI_REG_SHORT_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) SC500AI_FETCH_EXP_L(s_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) // set gain reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) sc500ai_get_gain_reg(l_t_gain, &l_again, &l_again_fine, &l_dgain, &l_dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) sc500ai_get_gain_reg(s_t_gain, &s_again, &s_again_fine, &s_dgain, &s_dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) SC500AI_REG_DIG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) l_dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) SC500AI_REG_DIG_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) l_dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) SC500AI_REG_ANA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) l_again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) SC500AI_REG_ANA_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) l_again_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) SC500AI_REG_SDIG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) s_dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) SC500AI_REG_SDIG_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) s_dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) SC500AI_REG_SANA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) s_again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) SC500AI_REG_SANA_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) s_again_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) sc500ai_set_hightemp_dpc(sc500ai, s_t_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int sc500ai_get_channel_info(struct sc500ai *sc500ai, struct rkmodule_channel_info *ch_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ch_info->vc = sc500ai->cur_mode->vc[ch_info->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ch_info->width = sc500ai->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) ch_info->height = sc500ai->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ch_info->bus_fmt = sc500ai->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) static long sc500ai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct sc500ai *sc500ai = to_sc500ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) const struct sc500ai_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) sc500ai_get_module_inf(sc500ai, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) hdr->hdr_mode = sc500ai->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) w = sc500ai->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) h = sc500ai->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) sc500ai->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (i == ARRAY_SIZE(supported_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) dev_err(&sc500ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) mode = sc500ai->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) w = sc500ai->cur_mode->hts_def - sc500ai->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) h = sc500ai->cur_mode->vts_def - sc500ai->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) __v4l2_ctrl_modify_range(sc500ai->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) __v4l2_ctrl_modify_range(sc500ai->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) SC500AI_VTS_MAX - sc500ai->cur_mode->height, 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) __v4l2_ctrl_s_ctrl(sc500ai->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * SC500AI_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) __v4l2_ctrl_s_ctrl_int64(sc500ai->pixel_rate, pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) sc500ai->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) sc500ai->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dev_info(&sc500ai->client->dev, "sensor mode: %d\n", sc500ai->cur_mode->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (sc500ai->cur_mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ret = sc500ai_set_hdrae(sc500ai, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ret = sc500ai_write_reg(sc500ai->client, SC500AI_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) SC500AI_REG_VALUE_08BIT, SC500AI_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ret = sc500ai_write_reg(sc500ai->client, SC500AI_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) SC500AI_REG_VALUE_08BIT, SC500AI_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ch_info = (struct rkmodule_channel_info *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ret = sc500ai_get_channel_info(sc500ai, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static long sc500ai_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ret = sc500ai_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) ret = sc500ai_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (copy_from_user(hdr, up, sizeof(*hdr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ret = sc500ai_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (copy_from_user(hdrae, up, sizeof(*hdrae)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ret = sc500ai_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (copy_from_user(&stream, up, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) ret = sc500ai_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (!ch_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ret = sc500ai_ioctl(sd, cmd, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ret = copy_to_user(up, ch_info, sizeof(*ch_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) kfree(ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static int __sc500ai_start_stream(struct sc500ai *sc500ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ret = sc500ai_write_array(sc500ai->client, sc500ai->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret = __v4l2_ctrl_handler_setup(&sc500ai->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (sc500ai->has_init_exp && sc500ai->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ret = sc500ai_ioctl(&sc500ai->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) &sc500ai->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) dev_err(&sc500ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return sc500ai_write_reg(sc500ai->client, SC500AI_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) SC500AI_REG_VALUE_08BIT, SC500AI_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static int __sc500ai_stop_stream(struct sc500ai *sc500ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) sc500ai->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return sc500ai_write_reg(sc500ai->client, SC500AI_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) SC500AI_REG_VALUE_08BIT, SC500AI_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static int sc500ai_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) struct sc500ai *sc500ai = to_sc500ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) struct i2c_client *client = sc500ai->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) mutex_lock(&sc500ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (on == sc500ai->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ret = __sc500ai_start_stream(sc500ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) __sc500ai_stop_stream(sc500ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) sc500ai->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) mutex_unlock(&sc500ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static int sc500ai_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct sc500ai *sc500ai = to_sc500ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct i2c_client *client = sc500ai->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) mutex_lock(&sc500ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (sc500ai->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) SC500AI_SOFTWARE_RESET_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) sc500ai->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) sc500ai->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) mutex_unlock(&sc500ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static int __sc500ai_power_on(struct sc500ai *sc500ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct device *dev = &sc500ai->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (!IS_ERR_OR_NULL(sc500ai->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) ret = pinctrl_select_state(sc500ai->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) sc500ai->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) ret = clk_set_rate(sc500ai->xvclk, SC500AI_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) dev_warn(dev, "Failed to set xvclk rate (27MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (clk_get_rate(sc500ai->xvclk) != SC500AI_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) ret = clk_prepare_enable(sc500ai->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (!IS_ERR(sc500ai->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) gpiod_set_value_cansleep(sc500ai->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ret = regulator_bulk_enable(sc500ai_NUM_SUPPLIES, sc500ai->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (!IS_ERR(sc500ai->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) gpiod_set_value_cansleep(sc500ai->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (!IS_ERR(sc500ai->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) gpiod_set_value_cansleep(sc500ai->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) usleep_range(4000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) clk_disable_unprepare(sc500ai->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) static void __sc500ai_power_off(struct sc500ai *sc500ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) struct device *dev = &sc500ai->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (!IS_ERR(sc500ai->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) gpiod_set_value_cansleep(sc500ai->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) clk_disable_unprepare(sc500ai->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (!IS_ERR(sc500ai->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) gpiod_set_value_cansleep(sc500ai->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (!IS_ERR_OR_NULL(sc500ai->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) ret = pinctrl_select_state(sc500ai->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) sc500ai->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) regulator_bulk_disable(sc500ai_NUM_SUPPLIES, sc500ai->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static int sc500ai_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) struct sc500ai *sc500ai = to_sc500ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return __sc500ai_power_on(sc500ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) static int sc500ai_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) struct sc500ai *sc500ai = to_sc500ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) __sc500ai_power_off(sc500ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) static int sc500ai_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) struct sc500ai *sc500ai = to_sc500ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) const struct sc500ai_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) mutex_lock(&sc500ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) mutex_unlock(&sc500ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define DST_WIDTH 2880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define DST_HEIGHT 1616
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * The resolution of the driver configuration needs to be exactly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * the same as the current output resolution of the sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * the input width of the isp needs to be 16 aligned,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * the input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) * Can be cropped to standard resolution by this function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * otherwise it will crop out strange resolution according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * to the alignment rules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) static int sc500ai_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) sel->r.left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) sel->r.width = DST_WIDTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) sel->r.top = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) sel->r.height = DST_HEIGHT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static int sc500ai_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static const struct dev_pm_ops sc500ai_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) SET_RUNTIME_PM_OPS(sc500ai_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) sc500ai_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) static const struct v4l2_subdev_internal_ops sc500ai_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .open = sc500ai_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) static const struct v4l2_subdev_core_ops sc500ai_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .s_power = sc500ai_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .ioctl = sc500ai_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .compat_ioctl32 = sc500ai_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static const struct v4l2_subdev_video_ops sc500ai_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .s_stream = sc500ai_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .g_frame_interval = sc500ai_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) static const struct v4l2_subdev_pad_ops sc500ai_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .enum_mbus_code = sc500ai_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .enum_frame_size = sc500ai_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .enum_frame_interval = sc500ai_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) .get_fmt = sc500ai_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .set_fmt = sc500ai_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .get_selection = sc500ai_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .get_mbus_config = sc500ai_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static const struct v4l2_subdev_ops sc500ai_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .core = &sc500ai_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .video = &sc500ai_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .pad = &sc500ai_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static void sc500ai_modify_fps_info(struct sc500ai *sc500ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) const struct sc500ai_mode *mode = sc500ai->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) sc500ai->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) sc500ai->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static int sc500ai_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) struct sc500ai *sc500ai = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) struct sc500ai, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct i2c_client *client = sc500ai->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) u32 again = 0, again_fine = 0, dgain = 0, dgain_fine = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) u32 val = 0, vts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) u64 delay_time = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) u32 cur_fps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) u32 def_fps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) u32 denominator = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) u32 numerator = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) max = sc500ai->cur_mode->height + ctrl->val - 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) __v4l2_ctrl_modify_range(sc500ai->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) sc500ai->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) sc500ai->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) sc500ai->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (sc500ai->cur_mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) val = ctrl->val << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) ret = sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) SC500AI_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) SC500AI_FETCH_EXP_H(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) SC500AI_REG_EXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) SC500AI_FETCH_EXP_M(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) SC500AI_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) SC500AI_FETCH_EXP_L(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) dev_dbg(&client->dev, "set exposure 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (sc500ai->cur_mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) sc500ai_get_gain_reg(ctrl->val, &again, &again_fine, &dgain, &dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) ret = sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) SC500AI_REG_DIG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) SC500AI_REG_DIG_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) SC500AI_REG_ANA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) SC500AI_REG_ANA_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) again_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) sc500ai_set_hightemp_dpc(sc500ai, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) dev_dbg(&sc500ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) "total_gain:%d again 0x%x, again_fine 0x%x, dgain 0x%x, dgain_fine 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) ctrl->val, again, again_fine, dgain, dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) vts = ctrl->val + sc500ai->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) ret = sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) SC500AI_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) (vts >> 8) & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) SC500AI_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) vts & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) sc500ai->cur_vts = vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) if (sc500ai->cur_vts != sc500ai->cur_mode->vts_def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) sc500ai_modify_fps_info(sc500ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) ret = sc500ai_read_reg(sc500ai->client, SC500AI_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) SC500AI_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) val |= SC500AI_MIRROR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) val &= ~SC500AI_MIRROR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) ret |= sc500ai_write_reg(sc500ai->client, SC500AI_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) SC500AI_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) ret = sc500ai_read_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) SC500AI_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) SC500AI_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) denominator = sc500ai->cur_mode->max_fps.denominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) numerator = sc500ai->cur_mode->max_fps.numerator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) def_fps = denominator / numerator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) cur_fps = def_fps * sc500ai->cur_mode->vts_def / sc500ai->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (cur_fps > 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) vts = def_fps * sc500ai->cur_mode->vts_def / 25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) ret = sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) SC500AI_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) (vts >> 8) & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) SC500AI_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) vts & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) delay_time = 1000000 / 25;//one frame interval
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) delay_time *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) usleep_range(delay_time, delay_time + 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) val |= SC500AI_FLIP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) val &= ~SC500AI_FLIP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) SC500AI_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (cur_fps > 25) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) usleep_range(delay_time, delay_time + 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) vts = sc500ai->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) ret = sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) SC500AI_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) (vts >> 8) & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) ret |= sc500ai_write_reg(sc500ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) SC500AI_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) SC500AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) vts & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static const struct v4l2_ctrl_ops sc500ai_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .s_ctrl = sc500ai_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) static int sc500ai_initialize_controls(struct sc500ai *sc500ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) const struct sc500ai_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) u64 pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) handler = &sc500ai->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) mode = sc500ai->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) handler->lock = &sc500ai->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) sc500ai->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) ARRAY_SIZE(link_freq_items) - 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) link_freq_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) __v4l2_ctrl_s_ctrl(sc500ai->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * SC500AI_LANES ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) sc500ai->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) V4L2_CID_PIXEL_RATE, 0, SC500AI_MAX_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) 1, pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) sc500ai->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (sc500ai->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) sc500ai->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) sc500ai->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) sc500ai->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) sc500ai->vblank = v4l2_ctrl_new_std(handler, &sc500ai_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) SC500AI_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) exposure_max = mode->vts_def - 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) sc500ai->exposure = v4l2_ctrl_new_std(handler, &sc500ai_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) V4L2_CID_EXPOSURE, SC500AI_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) exposure_max, sc500ai_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) sc500ai->anal_gain = v4l2_ctrl_new_std(handler, &sc500ai_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) V4L2_CID_ANALOGUE_GAIN, SC500AI_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) SC500AI_GAIN_MAX, SC500AI_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) SC500AI_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) v4l2_ctrl_new_std(handler, &sc500ai_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) v4l2_ctrl_new_std(handler, &sc500ai_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) dev_err(&sc500ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) sc500ai->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) sc500ai->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static int sc500ai_check_sensor_id(struct sc500ai *sc500ai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) struct device *dev = &sc500ai->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) ret = sc500ai_read_reg(client, SC500AI_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) SC500AI_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (id != SC500AI_CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) dev_info(dev, "Detected SC%06x sensor\n", SC500AI_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) static int sc500ai_configure_regulators(struct sc500ai *sc500ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) for (i = 0; i < sc500ai_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) sc500ai->supplies[i].supply = sc500ai_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) return devm_regulator_bulk_get(&sc500ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) sc500ai_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) sc500ai->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) static int sc500ai_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) struct sc500ai *sc500ai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) sc500ai = devm_kzalloc(dev, sizeof(*sc500ai), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if (!sc500ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) &sc500ai->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) &sc500ai->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) &sc500ai->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) &sc500ai->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) sc500ai->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) sc500ai->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) if (i == ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) sc500ai->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) sc500ai->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) if (IS_ERR(sc500ai->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) sc500ai->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if (IS_ERR(sc500ai->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) sc500ai->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) if (IS_ERR(sc500ai->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) sc500ai->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if (!IS_ERR(sc500ai->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) sc500ai->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) pinctrl_lookup_state(sc500ai->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (IS_ERR(sc500ai->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) sc500ai->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) pinctrl_lookup_state(sc500ai->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) if (IS_ERR(sc500ai->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) ret = sc500ai_configure_regulators(sc500ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) mutex_init(&sc500ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) sd = &sc500ai->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) v4l2_i2c_subdev_init(sd, client, &sc500ai_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) ret = sc500ai_initialize_controls(sc500ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) ret = __sc500ai_power_on(sc500ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) ret = sc500ai_check_sensor_id(sc500ai, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) sd->internal_ops = &sc500ai_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) sc500ai->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) ret = media_entity_pads_init(&sd->entity, 1, &sc500ai->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) if (strcmp(sc500ai->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) sc500ai->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) SC500AI_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) __sc500ai_power_off(sc500ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) v4l2_ctrl_handler_free(&sc500ai->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) mutex_destroy(&sc500ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) static int sc500ai_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) struct sc500ai *sc500ai = to_sc500ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) v4l2_ctrl_handler_free(&sc500ai->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) mutex_destroy(&sc500ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) __sc500ai_power_off(sc500ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) static const struct of_device_id sc500ai_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) { .compatible = "smartsens,sc500ai" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) MODULE_DEVICE_TABLE(of, sc500ai_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) static const struct i2c_device_id sc500ai_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) { "smartsens,sc500ai", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) static struct i2c_driver sc500ai_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .name = SC500AI_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .pm = &sc500ai_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .of_match_table = of_match_ptr(sc500ai_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .probe = &sc500ai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .remove = &sc500ai_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .id_table = sc500ai_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) return i2c_add_driver(&sc500ai_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) i2c_del_driver(&sc500ai_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) MODULE_DESCRIPTION("smartsens sc500ai sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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