^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sc4336 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 first version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) //#define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SC4336_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SC4336_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SC4336_LINK_FREQ_315 315000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PIXEL_RATE_WITH_315M_10BIT (SC4336_LINK_FREQ_315 * 2 * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) SC4336_LANES / SC4336_BITS_PER_SAMPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SC4336_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CHIP_ID 0xdc42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SC4336_REG_CHIP_ID 0x3107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SC4336_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SC4336_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SC4336_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SC4336_REG_EXPOSURE_H 0x3e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC4336_REG_EXPOSURE_M 0x3e01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SC4336_REG_EXPOSURE_L 0x3e02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SC4336_EXPOSURE_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SC4336_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SC4336_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SC4336_REG_DIG_GAIN 0x3e06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SC4336_REG_DIG_FINE_GAIN 0x3e07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SC4336_REG_ANA_GAIN 0x3e09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SC4336_GAIN_MIN 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SC4336_GAIN_MAX (32 * 15 * 32) //32*15*32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SC4336_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SC4336_GAIN_DEFAULT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC4336_REG_GROUP_HOLD 0x3812
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SC4336_GROUP_HOLD_START 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SC4336_GROUP_HOLD_END 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SC4336_REG_TEST_PATTERN 0x4501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SC4336_TEST_PATTERN_BIT_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SC4336_REG_VTS_H 0x320e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SC4336_REG_VTS_L 0x320f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SC4336_FLIP_MIRROR_REG 0x3221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SC4336_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SC4336_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SC4336_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SC4336_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SC4336_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SC4336_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SC4336_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define REG_DELAY 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SC4336_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SC4336_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SC4336_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SC4336_NAME "sc4336"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const char * const sc4336_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SC4336_NUM_SUPPLIES ARRAY_SIZE(sc4336_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct sc4336_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct sc4336 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct regulator_bulk_data supplies[SC4336_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const struct sc4336_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct v4l2_fract cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define to_sc4336(sd) container_of(sd, struct sc4336, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) static const struct regval sc4336_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * mipi_datarate per lane 630Mbps, 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct regval sc4336_linear_10_2560x1440_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x37f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x301f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x30b8, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x3253, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x3301, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x3302, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x3305, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x3306, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x3308, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x330a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x330b, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x330d, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x3333, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x335e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x335f, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x3364, 0x5e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x337d, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x338f, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3390, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3391, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3392, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3393, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3394, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3395, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3396, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3397, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3398, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3399, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x339a, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x339b, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x339c, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x33a2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x33ad, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x33b2, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x33b3, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x33f8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x33f9, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x33fa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x33fb, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x33fc, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x33fd, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x349f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x34a6, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x34a7, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x34a8, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x34a9, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x34aa, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x34ab, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x34ac, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x34ad, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x34f8, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x34f9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3630, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3631, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3633, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3637, 0x4c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3641, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3670, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3674, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3675, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3676, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3677, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3678, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3679, 0x8d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x367c, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x367d, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x367e, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x367f, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3696, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3697, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3698, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x36a0, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x36a1, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x36b0, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x36b1, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x36b2, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x36b3, 0x8b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x36b4, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x36b5, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x36b6, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x36ea, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x36eb, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x36ec, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x36ed, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x370f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3722, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3724, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3771, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3772, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3773, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x377a, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x377b, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x37fa, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x37fb, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x37fc, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x37fd, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3905, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x391d, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x3926, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3933, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3934, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x3935, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x3936, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3937, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3938, 0x6f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x3939, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x393a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x39dc, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x3e01, 0x5d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x3e02, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x440e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x4509, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x450d, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x5000, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x5799, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x579a, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x57d9, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x57da, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x5ae0, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x5ae1, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x5ae2, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x5ae3, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x5ae4, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x5ae5, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x5ae6, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x5ae7, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x5ae8, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x5ae9, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x5aea, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x5aeb, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x5aec, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x5aed, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x36e9, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x37f9, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x320e, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x320f, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const struct sc4336_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .width = 2560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .height = 1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .exp_def = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .hts_def = 0x0578 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .vts_def = 0x0708,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .reg_list = sc4336_linear_10_2560x1440_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) SC4336_LINK_FREQ_315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const char * const sc4336_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int sc4336_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int sc4336_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = sc4336_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) SC4336_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static int sc4336_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int sc4336_set_gain_reg(struct sc4336 *sc4336, u32 gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 coarse_again = 0, coarse_dgian = 0, fine_dgian = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u32 gain_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (gain < 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) gain = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) else if (gain > SC4336_GAIN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) gain = SC4336_GAIN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) gain_factor = gain * 1000 / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) if (gain_factor < 2000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) coarse_again = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) coarse_dgian = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) fine_dgian = gain_factor * 128 / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) } else if (gain_factor < 4000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) coarse_again = 0x08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) coarse_dgian = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) fine_dgian = gain_factor * 128 / 2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } else if (gain_factor < 8000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) coarse_again = 0x09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) coarse_dgian = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) fine_dgian = gain_factor * 128 / 4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) } else if (gain_factor < 16000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) coarse_again = 0x0b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) coarse_dgian = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) fine_dgian = gain_factor * 128 / 8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) } else if (gain_factor < 32000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) coarse_again = 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) coarse_dgian = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) fine_dgian = gain_factor * 128 / 16000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) } else if (gain_factor < 32000 * 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) coarse_again = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) coarse_dgian = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) fine_dgian = gain_factor * 128 / 32000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) } else if (gain_factor < 32000 * 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) //open dgain begin max digital gain 4X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) coarse_again = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) coarse_dgian = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) fine_dgian = gain_factor * 128 / 32000 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) } else if (gain_factor < 32000 * 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) coarse_again = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) coarse_dgian = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) fine_dgian = gain_factor * 128 / 32000 / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) } else if (gain_factor < 32000 * 15) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) coarse_again = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) coarse_dgian = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) fine_dgian = gain_factor * 128 / 32000 / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) coarse_again = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) coarse_dgian = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) fine_dgian = 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ret = sc4336_write_reg(sc4336->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) SC4336_REG_DIG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) SC4336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) coarse_dgian);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ret |= sc4336_write_reg(sc4336->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) SC4336_REG_DIG_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) SC4336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) fine_dgian);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ret |= sc4336_write_reg(sc4336->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) SC4336_REG_ANA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) SC4336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) coarse_again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static int sc4336_get_reso_dist(const struct sc4336_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static const struct sc4336_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) sc4336_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dist = sc4336_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int sc4336_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct sc4336 *sc4336 = to_sc4336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) const struct sc4336_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) mutex_lock(&sc4336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) mode = sc4336_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) mutex_unlock(&sc4336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) sc4336->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) __v4l2_ctrl_modify_range(sc4336->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) __v4l2_ctrl_modify_range(sc4336->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) SC4336_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) sc4336->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mutex_unlock(&sc4336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static int sc4336_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct sc4336 *sc4336 = to_sc4336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) const struct sc4336_mode *mode = sc4336->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mutex_lock(&sc4336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) mutex_unlock(&sc4336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) /* format info: width/height/data type/virctual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) mutex_unlock(&sc4336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int sc4336_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct sc4336 *sc4336 = to_sc4336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) code->code = sc4336->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int sc4336_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (fse->code != supported_modes[0].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int sc4336_enable_test_pattern(struct sc4336 *sc4336, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret = sc4336_read_reg(sc4336->client, SC4336_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) SC4336_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) val |= SC4336_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) val &= ~SC4336_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ret |= sc4336_write_reg(sc4336->client, SC4336_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) SC4336_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int sc4336_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct sc4336 *sc4336 = to_sc4336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) const struct sc4336_mode *mode = sc4336->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (sc4336->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) fi->interval = sc4336->cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int sc4336_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct sc4336 *sc4336 = to_sc4336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) const struct sc4336_mode *mode = sc4336->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) u32 val = 1 << (SC4336_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) val |= V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) val |= V4L2_MBUS_CSI2_CHANNEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static void sc4336_get_module_inf(struct sc4336 *sc4336,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) strscpy(inf->base.sensor, SC4336_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) strscpy(inf->base.module, sc4336->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) strscpy(inf->base.lens, sc4336->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static long sc4336_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct sc4336 *sc4336 = to_sc4336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) sc4336_get_module_inf(sc4336, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) hdr->hdr_mode = sc4336->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) w = sc4336->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) h = sc4336->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) sc4336->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) if (i == ARRAY_SIZE(supported_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) dev_err(&sc4336->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) w = sc4336->cur_mode->hts_def - sc4336->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) h = sc4336->cur_mode->vts_def - sc4336->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) __v4l2_ctrl_modify_range(sc4336->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) __v4l2_ctrl_modify_range(sc4336->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) SC4336_VTS_MAX - sc4336->cur_mode->height, 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ret = sc4336_write_reg(sc4336->client, SC4336_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) SC4336_REG_VALUE_08BIT, SC4336_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ret = sc4336_write_reg(sc4336->client, SC4336_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) SC4336_REG_VALUE_08BIT, SC4336_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static long sc4336_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ret = sc4336_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (copy_to_user(up, inf, sizeof(*inf)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ret = sc4336_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (copy_to_user(up, hdr, sizeof(*hdr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ret = sc4336_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret = sc4336_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ret = sc4336_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int __sc4336_start_stream(struct sc4336 *sc4336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ret = sc4336_write_array(sc4336->client, sc4336->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ret = __v4l2_ctrl_handler_setup(&sc4336->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return sc4336_write_reg(sc4336->client, SC4336_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) SC4336_REG_VALUE_08BIT, SC4336_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static int __sc4336_stop_stream(struct sc4336 *sc4336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return sc4336_write_reg(sc4336->client, SC4336_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) SC4336_REG_VALUE_08BIT, SC4336_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static int sc4336_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct sc4336 *sc4336 = to_sc4336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) struct i2c_client *client = sc4336->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) mutex_lock(&sc4336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (on == sc4336->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ret = __sc4336_start_stream(sc4336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) __sc4336_stop_stream(sc4336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) sc4336->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) mutex_unlock(&sc4336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static int sc4336_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct sc4336 *sc4336 = to_sc4336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct i2c_client *client = sc4336->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) mutex_lock(&sc4336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (sc4336->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ret = sc4336_write_array(sc4336->client, sc4336_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) sc4336->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) sc4336->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) mutex_unlock(&sc4336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static inline u32 sc4336_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) return DIV_ROUND_UP(cycles, SC4336_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) static int __sc4336_power_on(struct sc4336 *sc4336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct device *dev = &sc4336->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (!IS_ERR_OR_NULL(sc4336->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ret = pinctrl_select_state(sc4336->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) sc4336->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ret = clk_set_rate(sc4336->xvclk, SC4336_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (clk_get_rate(sc4336->xvclk) != SC4336_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ret = clk_prepare_enable(sc4336->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (!IS_ERR(sc4336->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) gpiod_set_value_cansleep(sc4336->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ret = regulator_bulk_enable(SC4336_NUM_SUPPLIES, sc4336->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (!IS_ERR(sc4336->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) gpiod_set_value_cansleep(sc4336->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (!IS_ERR(sc4336->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) gpiod_set_value_cansleep(sc4336->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (!IS_ERR(sc4336->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) usleep_range(6000, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) usleep_range(12000, 16000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) delay_us = sc4336_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) clk_disable_unprepare(sc4336->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static void __sc4336_power_off(struct sc4336 *sc4336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct device *dev = &sc4336->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (!IS_ERR(sc4336->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) gpiod_set_value_cansleep(sc4336->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) clk_disable_unprepare(sc4336->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (!IS_ERR(sc4336->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) gpiod_set_value_cansleep(sc4336->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (!IS_ERR_OR_NULL(sc4336->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ret = pinctrl_select_state(sc4336->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) sc4336->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) regulator_bulk_disable(SC4336_NUM_SUPPLIES, sc4336->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static int sc4336_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct sc4336 *sc4336 = to_sc4336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return __sc4336_power_on(sc4336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) static int sc4336_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct sc4336 *sc4336 = to_sc4336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) __sc4336_power_off(sc4336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static int sc4336_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct sc4336 *sc4336 = to_sc4336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) const struct sc4336_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) mutex_lock(&sc4336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) mutex_unlock(&sc4336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static int sc4336_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static const struct dev_pm_ops sc4336_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) SET_RUNTIME_PM_OPS(sc4336_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) sc4336_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static const struct v4l2_subdev_internal_ops sc4336_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .open = sc4336_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) static const struct v4l2_subdev_core_ops sc4336_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .s_power = sc4336_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .ioctl = sc4336_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .compat_ioctl32 = sc4336_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static const struct v4l2_subdev_video_ops sc4336_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .s_stream = sc4336_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .g_frame_interval = sc4336_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static const struct v4l2_subdev_pad_ops sc4336_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) .enum_mbus_code = sc4336_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) .enum_frame_size = sc4336_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) .enum_frame_interval = sc4336_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .get_fmt = sc4336_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .set_fmt = sc4336_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .get_mbus_config = sc4336_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static const struct v4l2_subdev_ops sc4336_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) .core = &sc4336_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .video = &sc4336_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .pad = &sc4336_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) static void sc4336_modify_fps_info(struct sc4336 *sc4336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) const struct sc4336_mode *mode = sc4336->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) sc4336->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) sc4336->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) static int sc4336_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct sc4336 *sc4336 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) struct sc4336, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct i2c_client *client = sc4336->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) max = sc4336->cur_mode->height + ctrl->val - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) __v4l2_ctrl_modify_range(sc4336->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) sc4336->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) sc4336->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) sc4336->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (sc4336->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) val = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) ret = sc4336_write_reg(sc4336->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) SC4336_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) SC4336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) SC4336_FETCH_EXP_H(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ret |= sc4336_write_reg(sc4336->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) SC4336_REG_EXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) SC4336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) SC4336_FETCH_EXP_M(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ret |= sc4336_write_reg(sc4336->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) SC4336_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) SC4336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) SC4336_FETCH_EXP_L(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) dev_dbg(&client->dev, "set gain 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (sc4336->cur_mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) ret = sc4336_set_gain_reg(sc4336, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) ret = sc4336_write_reg(sc4336->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) SC4336_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) SC4336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) (ctrl->val + sc4336->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ret |= sc4336_write_reg(sc4336->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) SC4336_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) SC4336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) (ctrl->val + sc4336->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) sc4336->cur_vts = ctrl->val + sc4336->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (sc4336->cur_vts != sc4336->cur_mode->vts_def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) sc4336_modify_fps_info(sc4336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) ret = sc4336_enable_test_pattern(sc4336, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ret = sc4336_read_reg(sc4336->client, SC4336_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) SC4336_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ret |= sc4336_write_reg(sc4336->client, SC4336_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) SC4336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) SC4336_FETCH_MIRROR(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) ret = sc4336_read_reg(sc4336->client, SC4336_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) SC4336_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ret |= sc4336_write_reg(sc4336->client, SC4336_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) SC4336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) SC4336_FETCH_FLIP(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static const struct v4l2_ctrl_ops sc4336_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .s_ctrl = sc4336_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) static int sc4336_initialize_controls(struct sc4336 *sc4336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) const struct sc4336_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) handler = &sc4336->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) mode = sc4336->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) handler->lock = &sc4336->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) 0, PIXEL_RATE_WITH_315M_10BIT, 1, PIXEL_RATE_WITH_315M_10BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) sc4336->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) if (sc4336->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) sc4336->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) sc4336->vblank = v4l2_ctrl_new_std(handler, &sc4336_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) SC4336_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) sc4336->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) exposure_max = mode->vts_def - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) sc4336->exposure = v4l2_ctrl_new_std(handler, &sc4336_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) V4L2_CID_EXPOSURE, SC4336_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) exposure_max, SC4336_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) sc4336->anal_gain = v4l2_ctrl_new_std(handler, &sc4336_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) V4L2_CID_ANALOGUE_GAIN, SC4336_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) SC4336_GAIN_MAX, SC4336_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) SC4336_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) sc4336->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) &sc4336_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ARRAY_SIZE(sc4336_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) 0, 0, sc4336_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) v4l2_ctrl_new_std(handler, &sc4336_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) v4l2_ctrl_new_std(handler, &sc4336_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) dev_err(&sc4336->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) sc4336->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) static int sc4336_check_sensor_id(struct sc4336 *sc4336,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct device *dev = &sc4336->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) ret = sc4336_read_reg(client, SC4336_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) SC4336_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static int sc4336_configure_regulators(struct sc4336 *sc4336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) for (i = 0; i < SC4336_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) sc4336->supplies[i].supply = sc4336_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return devm_regulator_bulk_get(&sc4336->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) SC4336_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) sc4336->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static int sc4336_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) struct sc4336 *sc4336;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) sc4336 = devm_kzalloc(dev, sizeof(*sc4336), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (!sc4336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) &sc4336->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) &sc4336->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) &sc4336->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) &sc4336->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) sc4336->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) sc4336->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) sc4336->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (IS_ERR(sc4336->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) sc4336->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if (IS_ERR(sc4336->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) sc4336->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (IS_ERR(sc4336->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) sc4336->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (!IS_ERR(sc4336->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) sc4336->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) pinctrl_lookup_state(sc4336->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) if (IS_ERR(sc4336->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) sc4336->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) pinctrl_lookup_state(sc4336->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (IS_ERR(sc4336->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) ret = sc4336_configure_regulators(sc4336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) mutex_init(&sc4336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) sd = &sc4336->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) v4l2_i2c_subdev_init(sd, client, &sc4336_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) ret = sc4336_initialize_controls(sc4336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) ret = __sc4336_power_on(sc4336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) ret = sc4336_check_sensor_id(sc4336, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) sd->internal_ops = &sc4336_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) sc4336->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) ret = media_entity_pads_init(&sd->entity, 1, &sc4336->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (strcmp(sc4336->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) sc4336->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) SC4336_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) __sc4336_power_off(sc4336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) v4l2_ctrl_handler_free(&sc4336->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) mutex_destroy(&sc4336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) static int sc4336_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) struct sc4336 *sc4336 = to_sc4336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) v4l2_ctrl_handler_free(&sc4336->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) mutex_destroy(&sc4336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) __sc4336_power_off(sc4336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static const struct of_device_id sc4336_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) { .compatible = "smartsens,sc4336" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) MODULE_DEVICE_TABLE(of, sc4336_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static const struct i2c_device_id sc4336_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) { "smartsens,sc4336", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) static struct i2c_driver sc4336_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .name = SC4336_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .pm = &sc4336_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .of_match_table = of_match_ptr(sc4336_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .probe = &sc4336_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .remove = &sc4336_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .id_table = sc4336_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return i2c_add_driver(&sc4336_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) i2c_del_driver(&sc4336_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) MODULE_DESCRIPTION("smartsens sc4336 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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