^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sc430cs driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 fix gain range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X04 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X05 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SC430CS_LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SC430CS_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SC430CS_LINK_FREQ_315 157500000// 315Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PIXEL_RATE_WITH_315M_10BIT (SC430CS_LINK_FREQ_315 * 2 * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) SC430CS_LANES / SC430CS_BITS_PER_SAMPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SC430CS_XVCLK_FREQ 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CHIP_ID 0xcd2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SC430CS_REG_CHIP_ID 0x3107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SC430CS_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SC430CS_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC430CS_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SC430CS_REG_EXPOSURE_H 0x3e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SC430CS_REG_EXPOSURE_M 0x3e01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SC430CS_REG_EXPOSURE_L 0x3e02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SC430CS_EXPOSURE_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SC430CS_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SC430CS_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SC430CS_REG_DIG_GAIN 0x3e06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SC430CS_REG_DIG_FINE_GAIN 0x3e07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SC430CS_REG_ANA_GAIN 0x3e08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SC430CS_REG_ANA_FINE_GAIN 0x3e09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SC430CS_GAIN_MIN 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SC430CS_GAIN_MAX (24 * 32 * 64) //23.32*31.75*64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC430CS_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SC430CS_GAIN_DEFAULT 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SC430CS_REG_GROUP_HOLD 0x3812
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SC430CS_GROUP_HOLD_START 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SC430CS_GROUP_HOLD_END 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SC430CS_REG_HIGH_TEMP_H 0x3974
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SC430CS_REG_HIGH_TEMP_L 0x3975
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SC430CS_REG_TEST_PATTERN 0x4501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SC430CS_TEST_PATTERN_BIT_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SC430CS_REG_VTS_H 0x320e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SC430CS_REG_VTS_L 0x320f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SC430CS_FLIP_MIRROR_REG 0x3221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SC430CS_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SC430CS_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SC430CS_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SC430CS_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SC430CS_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SC430CS_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SC430CS_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define REG_DELAY 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SC430CS_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SC430CS_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SC430CS_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SC430CS_NAME "sc430cs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) static const char * const sc430cs_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SC430CS_NUM_SUPPLIES ARRAY_SIZE(sc430cs_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct sc430cs_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct sc430cs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct regulator_bulk_data supplies[SC430CS_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct v4l2_fract cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) const struct sc430cs_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define to_sc430cs(sd) container_of(sd, struct sc430cs, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct regval sc430cs_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Xclk 27Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * mipi_datarate per lane 315Mbps, 4lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct regval sc430cs_linear_10_2560x1440_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x301c, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x301f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x3208, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x3209, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x320a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x320b, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x320e, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x320f, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3214, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3215, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3223, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3250, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3253, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3274, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3301, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3302, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3303, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3304, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3306, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3308, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3309, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x330b, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x330d, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x330e, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x330f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3310, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x331c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x331e, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x331f, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3320, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3333, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x334c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3356, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3364, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x338e, 0xfd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3390, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3391, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3392, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3393, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3394, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3395, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3396, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3397, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3398, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3399, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x339a, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x339b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x339c, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x33ac, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x33ae, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x33af, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x360f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3620, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3637, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x363a, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3670, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3671, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3672, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3673, 0x5e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3674, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3675, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x3676, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x367a, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x367b, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x367c, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x367d, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3690, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3691, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3692, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x369c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x369d, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x36ea, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x36eb, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x36ec, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x36ed, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x36fa, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x36fb, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x36fc, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x36fd, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3908, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x396c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3e01, 0xb6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3e02, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x3e03, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3e08, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3e09, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3e1b, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x4509, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x57a8, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x36e9, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x36f9, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static const struct sc430cs_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .width = 2560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .height = 1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .exp_def = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .hts_def = 0x0578 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .vts_def = 0x05dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .reg_list = sc430cs_linear_10_2560x1440_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) SC430CS_LINK_FREQ_315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const char * const sc430cs_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int sc430cs_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int sc430cs_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) ret = sc430cs_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) SC430CS_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int sc430cs_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int sc430cs_set_gain_reg(struct sc430cs *sc430cs, u32 gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u8 Coarse_gain = 1, DIG_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u32 Dcg_gainx100 = 1, ANA_Fine_gainx64 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u8 Coarse_gain_reg = 0, DIG_gain_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u8 ANA_Fine_gain_reg = 0x20, DIG_Fine_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) gain = gain * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (gain <= 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) gain = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) else if (gain > SC430CS_GAIN_MAX * 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) gain = SC430CS_GAIN_MAX * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (gain < 1504) { // start again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) Dcg_gainx100 = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) Coarse_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) DIG_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) Coarse_gain_reg = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) DIG_gain_reg = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) DIG_Fine_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) } else if (gain <= 3008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) Dcg_gainx100 = 147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) Coarse_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) DIG_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) Coarse_gain_reg = 0x23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) DIG_gain_reg = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DIG_Fine_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) } else if (gain <= 6017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) Dcg_gainx100 = 147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) Coarse_gain = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) DIG_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) Coarse_gain_reg = 0x27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) DIG_gain_reg = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) DIG_Fine_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) } else if (gain <= 12034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) Dcg_gainx100 = 147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) Coarse_gain = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) DIG_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) Coarse_gain_reg = 0x2f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) DIG_gain_reg = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) DIG_Fine_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) } else if (gain <= 23879) { // end again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) Dcg_gainx100 = 147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) Coarse_gain = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) DIG_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) Coarse_gain_reg = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) DIG_gain_reg = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) DIG_Fine_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) } else if (gain < 23879 * 2) { // start dgain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) Dcg_gainx100 = 147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) Coarse_gain = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) DIG_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) ANA_Fine_gainx64 = 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) Coarse_gain_reg = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) DIG_gain_reg = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ANA_Fine_gain_reg = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) } else if (gain < 23879 * 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) Dcg_gainx100 = 147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) Coarse_gain = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) DIG_gain = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ANA_Fine_gainx64 = 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) Coarse_gain_reg = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) DIG_gain_reg = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ANA_Fine_gain_reg = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) } else if (gain < 23879 * 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) Dcg_gainx100 = 147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) Coarse_gain = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) DIG_gain = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ANA_Fine_gainx64 = 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) Coarse_gain_reg = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) DIG_gain_reg = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) ANA_Fine_gain_reg = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) } else if (gain < 23879 * 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) Dcg_gainx100 = 147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) Coarse_gain = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) DIG_gain = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ANA_Fine_gainx64 = 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) Coarse_gain_reg = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) DIG_gain_reg = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) ANA_Fine_gain_reg = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) } else if (gain <= 1754822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) Dcg_gainx100 = 147;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) Coarse_gain = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) DIG_gain = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ANA_Fine_gainx64 = 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) Coarse_gain_reg = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) DIG_gain_reg = 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ANA_Fine_gain_reg = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (gain < 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ANA_Fine_gain_reg = abs(100 * gain / (Dcg_gainx100 * Coarse_gain) / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) else if (gain == 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ANA_Fine_gain_reg = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) else if (gain < 23879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ANA_Fine_gain_reg = abs(100 * gain / (Dcg_gainx100 * Coarse_gain) / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) DIG_Fine_gain_reg = abs(800 * gain / (Dcg_gainx100 * Coarse_gain *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) DIG_gain) / ANA_Fine_gainx64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret = sc430cs_write_reg(sc430cs->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) SC430CS_REG_DIG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) SC430CS_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) DIG_gain_reg & 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ret |= sc430cs_write_reg(sc430cs->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) SC430CS_REG_DIG_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) SC430CS_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) DIG_Fine_gain_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ret |= sc430cs_write_reg(sc430cs->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) SC430CS_REG_ANA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) SC430CS_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) Coarse_gain_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) ret |= sc430cs_write_reg(sc430cs->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) SC430CS_REG_ANA_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) SC430CS_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ANA_Fine_gain_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int sc430cs_get_reso_dist(const struct sc430cs_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static const struct sc430cs_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) sc430cs_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dist = sc430cs_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static int sc430cs_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct sc430cs *sc430cs = to_sc430cs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) const struct sc430cs_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) mutex_lock(&sc430cs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) mode = sc430cs_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mutex_unlock(&sc430cs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) sc430cs->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) __v4l2_ctrl_modify_range(sc430cs->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) __v4l2_ctrl_modify_range(sc430cs->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) SC430CS_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) sc430cs->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) sc430cs->cur_vts = (u32)mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) mutex_unlock(&sc430cs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int sc430cs_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct sc430cs *sc430cs = to_sc430cs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) const struct sc430cs_mode *mode = sc430cs->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mutex_lock(&sc430cs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) mutex_unlock(&sc430cs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* format info: width/height/data type/virctual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) mutex_unlock(&sc430cs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int sc430cs_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct sc430cs *sc430cs = to_sc430cs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) code->code = sc430cs->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int sc430cs_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (fse->code != supported_modes[0].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int sc430cs_enable_test_pattern(struct sc430cs *sc430cs, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) ret = sc430cs_read_reg(sc430cs->client, SC430CS_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) SC430CS_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) val |= SC430CS_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) val &= ~SC430CS_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ret |= sc430cs_write_reg(sc430cs->client, SC430CS_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) SC430CS_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static int sc430cs_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct sc430cs *sc430cs = to_sc430cs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) const struct sc430cs_mode *mode = sc430cs->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (sc430cs->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) fi->interval = sc430cs->cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static int sc430cs_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct sc430cs *sc430cs = to_sc430cs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) const struct sc430cs_mode *mode = sc430cs->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u32 val = 1 << (SC430CS_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) val |= V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) val |= V4L2_MBUS_CSI2_CHANNEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static void sc430cs_get_module_inf(struct sc430cs *sc430cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) strlcpy(inf->base.sensor, SC430CS_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) strlcpy(inf->base.module, sc430cs->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) strlcpy(inf->base.lens, sc430cs->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) static long sc430cs_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct sc430cs *sc430cs = to_sc430cs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) sc430cs_get_module_inf(sc430cs, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) hdr->hdr_mode = sc430cs->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) w = sc430cs->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) h = sc430cs->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) sc430cs->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (i == ARRAY_SIZE(supported_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) dev_err(&sc430cs->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) w = sc430cs->cur_mode->hts_def - sc430cs->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) h = sc430cs->cur_mode->vts_def - sc430cs->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) __v4l2_ctrl_modify_range(sc430cs->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) __v4l2_ctrl_modify_range(sc430cs->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) SC430CS_VTS_MAX - sc430cs->cur_mode->height, 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) sc430cs->cur_fps = sc430cs->cur_mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) sc430cs->cur_vts = sc430cs->cur_mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ret = sc430cs_write_reg(sc430cs->client, SC430CS_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) SC430CS_REG_VALUE_08BIT, SC430CS_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ret = sc430cs_write_reg(sc430cs->client, SC430CS_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) SC430CS_REG_VALUE_08BIT, SC430CS_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static long sc430cs_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ret = sc430cs_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret = sc430cs_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ret = sc430cs_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ret = sc430cs_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ret = sc430cs_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ret = sc430cs_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static int __sc430cs_start_stream(struct sc430cs *sc430cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ret = sc430cs_write_array(sc430cs->client, sc430cs->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) ret = __v4l2_ctrl_handler_setup(&sc430cs->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return sc430cs_write_reg(sc430cs->client, SC430CS_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) SC430CS_REG_VALUE_08BIT, SC430CS_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static int __sc430cs_stop_stream(struct sc430cs *sc430cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return sc430cs_write_reg(sc430cs->client, SC430CS_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) SC430CS_REG_VALUE_08BIT, SC430CS_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static int sc430cs_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct sc430cs *sc430cs = to_sc430cs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct i2c_client *client = sc430cs->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) mutex_lock(&sc430cs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (on == sc430cs->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ret = __sc430cs_start_stream(sc430cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) __sc430cs_stop_stream(sc430cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) sc430cs->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) mutex_unlock(&sc430cs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static int sc430cs_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct sc430cs *sc430cs = to_sc430cs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct i2c_client *client = sc430cs->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) mutex_lock(&sc430cs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (sc430cs->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ret = sc430cs_write_array(sc430cs->client, sc430cs_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) sc430cs->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) sc430cs->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) mutex_unlock(&sc430cs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static inline u32 sc430cs_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return DIV_ROUND_UP(cycles, SC430CS_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static int __sc430cs_power_on(struct sc430cs *sc430cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct device *dev = &sc430cs->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (!IS_ERR_OR_NULL(sc430cs->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ret = pinctrl_select_state(sc430cs->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) sc430cs->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ret = clk_set_rate(sc430cs->xvclk, SC430CS_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (clk_get_rate(sc430cs->xvclk) != SC430CS_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ret = clk_prepare_enable(sc430cs->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (!IS_ERR(sc430cs->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) gpiod_set_value_cansleep(sc430cs->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ret = regulator_bulk_enable(SC430CS_NUM_SUPPLIES, sc430cs->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (!IS_ERR(sc430cs->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) gpiod_set_value_cansleep(sc430cs->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (!IS_ERR(sc430cs->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) gpiod_set_value_cansleep(sc430cs->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (!IS_ERR(sc430cs->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) usleep_range(6000, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) usleep_range(12000, 16000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) delay_us = sc430cs_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) clk_disable_unprepare(sc430cs->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) static void __sc430cs_power_off(struct sc430cs *sc430cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct device *dev = &sc430cs->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (!IS_ERR(sc430cs->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) gpiod_set_value_cansleep(sc430cs->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) clk_disable_unprepare(sc430cs->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (!IS_ERR(sc430cs->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) gpiod_set_value_cansleep(sc430cs->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (!IS_ERR_OR_NULL(sc430cs->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) ret = pinctrl_select_state(sc430cs->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) sc430cs->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) regulator_bulk_disable(SC430CS_NUM_SUPPLIES, sc430cs->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static int sc430cs_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct sc430cs *sc430cs = to_sc430cs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return __sc430cs_power_on(sc430cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static int sc430cs_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct sc430cs *sc430cs = to_sc430cs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) __sc430cs_power_off(sc430cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static int sc430cs_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct sc430cs *sc430cs = to_sc430cs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) const struct sc430cs_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) mutex_lock(&sc430cs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) mutex_unlock(&sc430cs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static int sc430cs_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static const struct dev_pm_ops sc430cs_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) SET_RUNTIME_PM_OPS(sc430cs_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) sc430cs_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static const struct v4l2_subdev_internal_ops sc430cs_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .open = sc430cs_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static const struct v4l2_subdev_core_ops sc430cs_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .s_power = sc430cs_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) .ioctl = sc430cs_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .compat_ioctl32 = sc430cs_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static const struct v4l2_subdev_video_ops sc430cs_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .s_stream = sc430cs_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .g_frame_interval = sc430cs_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static const struct v4l2_subdev_pad_ops sc430cs_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .enum_mbus_code = sc430cs_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) .enum_frame_size = sc430cs_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .enum_frame_interval = sc430cs_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .get_fmt = sc430cs_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .set_fmt = sc430cs_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .get_mbus_config = sc430cs_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static const struct v4l2_subdev_ops sc430cs_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .core = &sc430cs_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .video = &sc430cs_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .pad = &sc430cs_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static void sc430cs_modify_fps_info(struct sc430cs *sc430cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) const struct sc430cs_mode *mode = sc430cs->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) sc430cs->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) sc430cs->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static int sc430cs_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct sc430cs *sc430cs = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct sc430cs, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct i2c_client *client = sc430cs->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) max = sc430cs->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) __v4l2_ctrl_modify_range(sc430cs->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) sc430cs->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) sc430cs->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) sc430cs->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (sc430cs->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) val = ctrl->val << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ret = sc430cs_write_reg(sc430cs->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) SC430CS_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) SC430CS_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) SC430CS_FETCH_EXP_H(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ret |= sc430cs_write_reg(sc430cs->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) SC430CS_REG_EXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) SC430CS_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) SC430CS_FETCH_EXP_M(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ret |= sc430cs_write_reg(sc430cs->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) SC430CS_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) SC430CS_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) SC430CS_FETCH_EXP_L(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (sc430cs->cur_mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ret = sc430cs_set_gain_reg(sc430cs, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ret = sc430cs_write_reg(sc430cs->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) SC430CS_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) SC430CS_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) (ctrl->val + sc430cs->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ret |= sc430cs_write_reg(sc430cs->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) SC430CS_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) SC430CS_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) (ctrl->val + sc430cs->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) sc430cs->cur_vts = ctrl->val + sc430cs->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (sc430cs->cur_vts != sc430cs->cur_mode->vts_def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) sc430cs_modify_fps_info(sc430cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ret = sc430cs_enable_test_pattern(sc430cs, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) ret = sc430cs_read_reg(sc430cs->client, SC430CS_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) SC430CS_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ret |= sc430cs_write_reg(sc430cs->client, SC430CS_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) SC430CS_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) SC430CS_FETCH_MIRROR(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ret = sc430cs_read_reg(sc430cs->client, SC430CS_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) SC430CS_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) ret |= sc430cs_write_reg(sc430cs->client, SC430CS_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) SC430CS_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) SC430CS_FETCH_FLIP(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static const struct v4l2_ctrl_ops sc430cs_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .s_ctrl = sc430cs_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) static int sc430cs_initialize_controls(struct sc430cs *sc430cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) const struct sc430cs_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) handler = &sc430cs->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) mode = sc430cs->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) handler->lock = &sc430cs->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) 0, PIXEL_RATE_WITH_315M_10BIT, 1, PIXEL_RATE_WITH_315M_10BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) sc430cs->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (sc430cs->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) sc430cs->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) sc430cs->vblank = v4l2_ctrl_new_std(handler, &sc430cs_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) SC430CS_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) sc430cs->exposure = v4l2_ctrl_new_std(handler, &sc430cs_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) V4L2_CID_EXPOSURE, SC430CS_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) exposure_max, SC430CS_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) sc430cs->anal_gain = v4l2_ctrl_new_std(handler, &sc430cs_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) V4L2_CID_ANALOGUE_GAIN, SC430CS_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) SC430CS_GAIN_MAX, SC430CS_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) SC430CS_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) sc430cs->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) &sc430cs_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ARRAY_SIZE(sc430cs_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) 0, 0, sc430cs_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) v4l2_ctrl_new_std(handler, &sc430cs_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) v4l2_ctrl_new_std(handler, &sc430cs_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) dev_err(&sc430cs->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) sc430cs->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) sc430cs->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) sc430cs->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) static int sc430cs_check_sensor_id(struct sc430cs *sc430cs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) struct device *dev = &sc430cs->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) ret = sc430cs_read_reg(client, SC430CS_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) SC430CS_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) static int sc430cs_configure_regulators(struct sc430cs *sc430cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) for (i = 0; i < SC430CS_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) sc430cs->supplies[i].supply = sc430cs_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) return devm_regulator_bulk_get(&sc430cs->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) SC430CS_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) sc430cs->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static int sc430cs_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) struct sc430cs *sc430cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) sc430cs = devm_kzalloc(dev, sizeof(*sc430cs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) if (!sc430cs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) &sc430cs->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) &sc430cs->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) &sc430cs->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) &sc430cs->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) sc430cs->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) sc430cs->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (i == ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) sc430cs->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) sc430cs->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (IS_ERR(sc430cs->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) sc430cs->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) if (IS_ERR(sc430cs->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) sc430cs->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (IS_ERR(sc430cs->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) sc430cs->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (!IS_ERR(sc430cs->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) sc430cs->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) pinctrl_lookup_state(sc430cs->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (IS_ERR(sc430cs->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) sc430cs->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) pinctrl_lookup_state(sc430cs->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (IS_ERR(sc430cs->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) ret = sc430cs_configure_regulators(sc430cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) mutex_init(&sc430cs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) sd = &sc430cs->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) v4l2_i2c_subdev_init(sd, client, &sc430cs_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) ret = sc430cs_initialize_controls(sc430cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) ret = __sc430cs_power_on(sc430cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) ret = sc430cs_check_sensor_id(sc430cs, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) sd->internal_ops = &sc430cs_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) sc430cs->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) ret = media_entity_pads_init(&sd->entity, 1, &sc430cs->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (strcmp(sc430cs->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) sc430cs->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) SC430CS_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) __sc430cs_power_off(sc430cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) v4l2_ctrl_handler_free(&sc430cs->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) mutex_destroy(&sc430cs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) static int sc430cs_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct sc430cs *sc430cs = to_sc430cs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) v4l2_ctrl_handler_free(&sc430cs->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) mutex_destroy(&sc430cs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) __sc430cs_power_off(sc430cs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static const struct of_device_id sc430cs_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) { .compatible = "smartsens,sc430cs" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) MODULE_DEVICE_TABLE(of, sc430cs_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) static const struct i2c_device_id sc430cs_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) { "smartsens,sc430cs", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static struct i2c_driver sc430cs_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .name = SC430CS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) .pm = &sc430cs_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .of_match_table = of_match_ptr(sc430cs_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .probe = &sc430cs_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .remove = &sc430cs_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .id_table = sc430cs_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) return i2c_add_driver(&sc430cs_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) i2c_del_driver(&sc430cs_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) MODULE_DESCRIPTION("smartsens sc430cs sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags