^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sc4238 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X01 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X02 support digital gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X03 support 2688x1520@30fps 10bit linear mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X04 fixed hdr exposure issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) //#define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include "../platform/rockchip/isp/rkisp_tb_helper.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MIPI_FREQ_360M 360000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MIPI_FREQ_200M 200000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PIXEL_RATE_WITH_360M (MIPI_FREQ_360M * 2 / 10 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PIXEL_RATE_WITH_200M (MIPI_FREQ_200M * 2 / 12 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SC4238_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CHIP_ID 0x4235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SC4238_REG_CHIP_ID 0x3107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SC4238_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SC4238_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SC4238_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SC4238_EXPOSURE_MIN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SC4238_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SC4238_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SC4238_REG_EXP_LONG_H 0x3e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SC4238_REG_EXP_MID_H 0x3e04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SC4238_REG_EXP_MAX_MID_H 0x3e23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SC4238_REG_COARSE_AGAIN_L 0x3e08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SC4238_REG_FINE_AGAIN_L 0x3e09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC4238_REG_COARSE_AGAIN_S 0x3e12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SC4238_REG_FINE_AGAIN_S 0x3e13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SC4238_REG_COARSE_DGAIN_L 0x3e06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SC4238_REG_FINE_DGAIN_L 0x3e07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SC4238_REG_COARSE_DGAIN_S 0x3e10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SC4238_REG_FINE_DGAIN_S 0x3e11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SC4238_GAIN_MIN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SC4238_GAIN_MAX 0x7D04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SC4238_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SC4238_GAIN_DEFAULT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SC4238_GROUP_UPDATE_ADDRESS 0x3812
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SC4238_GROUP_UPDATE_START_DATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SC4238_GROUP_UPDATE_END_DATA 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SC4238_GROUP_UPDATE_DELAY 0x3802
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SC4238_SOFTWARE_RESET_REG 0x0103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SC4238_REG_TEST_PATTERN 0x4501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SC4238_TEST_PATTERN_BIT_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SC4238_REG_VTS_H 0x320e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SC4238_REG_VTS_L 0x320f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SC4238_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SC4238_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SC4238_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SC4238_LANES V4L2_MBUS_CSI2_4_LANE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SC4238_NAME "sc4238"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static const char * const sc4238_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SC4238_NUM_SUPPLIES ARRAY_SIZE(sc4238_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SC4238_FLIP_REG 0x3221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MIRROR_BIT_MASK (BIT(1) | BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define FLIP_BIT_MASK (BIT(6) | BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct sc4238_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct sc4238 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct regulator_bulk_data supplies[SC4238_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct v4l2_ctrl *h_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct v4l2_ctrl *v_flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct v4l2_fract cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) const struct sc4238_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) bool is_thunderboot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) bool is_thunderboot_ng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) bool is_first_streamoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u8 flip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define to_sc4238(sd) container_of(sd, struct sc4238, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static const struct regval sc4238_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * mipi_datarate per lane 337.5Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static const struct regval sc4238_linear10bit_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3018, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x301f, 0x9a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3031, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3037, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3038, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3106, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3200, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3201, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3202, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3203, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3204, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3205, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3206, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3207, 0xf7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x3208, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3209, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x320a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x320b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x320c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x320d, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x320e, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x320f, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3211, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3213, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3251, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3253, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x325f, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3273, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3301, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3304, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3306, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3308, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3309, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x330b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x330e, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3314, 0x94},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x331e, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x331f, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3320, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x334c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3352, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3356, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x335e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x335f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3363, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3364, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3366, 0x92},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x336d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x337a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x337b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x337c, 0x06},
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^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x337f, 0x2d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3390, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3391, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3392, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3393, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3394, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3395, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3399, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x33a2, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x33a3, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x33e0, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x33e1, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x33e2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x33e3, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x33e4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x33e5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x33e6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x33e7, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x33e8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x33e9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x33ea, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x33eb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x33ec, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x33ed, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x33ee, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x33ef, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x33f4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x33f5, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x33f6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x33f7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x33f8, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x33f9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x33fa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x33fb, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x33fc, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x33fd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x33fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x33ff, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x360f, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x3622, 0xee},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x3625, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x3630, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x3631, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x3633, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x3634, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x3635, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x3636, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x3637, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3638, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x363a, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x363b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x366e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3670, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x3671, 0xee},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x3672, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x3673, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x3674, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x3675, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x3676, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x367a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x367b, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x367c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x367d, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3690, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3691, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3692, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x3699, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x369a, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x369b, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x369c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x369d, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x36a2, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x36a3, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x36ea, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x36eb, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x36ec, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x36ed, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x36fa, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x36fb, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x36fc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x36fd, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x3902, 0xc5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x3905, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x3908, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x391b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x391c, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x391d, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x3933, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x3934, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x3940, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x3942, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x3943, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x3980, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x3981, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x3982, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x3983, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x3984, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x3985, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x3986, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x3987, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x3988, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x3989, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x398a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x398b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x398c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x398d, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x398e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x398f, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x3990, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x3991, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x3992, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x3993, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x3994, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x3995, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x3996, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x3997, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x3998, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x3999, 0xf8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x399a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x399b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x399c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x399d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x399e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x399f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x39a0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x39a1, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x39a2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x39a3, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x39af, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x39b5, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x39b6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x39b7, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x39b8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x39b9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x39ba, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x39bb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x39bc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x39bd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x39be, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x39bf, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x39c0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x39c1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x39c5, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x39c8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x39db, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x39dc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x39de, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x39df, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x39e0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x39e1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x39e2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x39e3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x3e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x3e01, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x3e02, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x3e03, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x3e06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x3e07, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x3e08, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x3e09, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x3e14, 0xb1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x3e25, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x3e26, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x4501, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x4509, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x4800, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x4818, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x4819, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x481a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x481b, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x481c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x481d, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x4821, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x4822, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x4823, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x4828, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x4829, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x4837, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x5784, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x5785, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x5787, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x5788, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x5789, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x578a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x578b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x578c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x5790, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x5791, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x5792, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x5793, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x5794, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x5795, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x57c4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x57c5, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x57c7, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x57c8, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x57c9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x57ca, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x57cb, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x57cc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x57d0, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x57d1, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x57d2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x57d3, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x57d4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x57d5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x5988, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x598e, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x598f, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x36e9, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x36f9, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * mipi_datarate per lane 720Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) static const struct regval sc4238_hdr10bit_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x3018, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x301f, 0x93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x3031, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x3037, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x3038, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x3106, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x3200, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x3201, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x3202, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x3203, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x3204, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x3205, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x3206, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x3207, 0xf7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x3208, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x3209, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x320a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x320b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x320c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x320d, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x320e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x320f, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x3211, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x3213, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x3220, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x3225, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x3235, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x3236, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x3237, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x3238, 0xc7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x3250, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x3251, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x3253, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x325f, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x3273, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x3301, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x3304, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x3305, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x3306, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x3307, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x3308, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x3309, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x330b, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x330d, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x330e, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x3314, 0x94},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x3317, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x3318, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x331e, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x331f, 0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x3320, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x3332, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x334c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x3350, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x3352, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x3356, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x3358, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x335c, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x335e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x335f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x3363, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x3364, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x3366, 0x92},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x336d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x337a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x337b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x337c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x337d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x337f, 0x2d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x3390, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x3391, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x3392, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x3393, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x3394, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x3395, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x3399, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x339e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x33a0, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x33a2, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x33a3, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x33a4, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x33a8, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x33aa, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x33e0, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x33e1, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x33e2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x33e3, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x33e4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0x33e5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {0x33e6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0x33e7, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x33e8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x33e9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x33ea, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x33eb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x33ec, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x33ed, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {0x33ee, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {0x33ef, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0x33f4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x33f5, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x33f6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {0x33f7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {0x33f8, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {0x33f9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {0x33fa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {0x33fb, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {0x33fc, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {0x33fd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x33fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x33ff, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x360f, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {0x3622, 0xee},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x3625, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x3630, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x3631, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x3633, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x3634, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x3635, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x3636, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x3637, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x3638, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x363a, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x363b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x3641, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x366e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x3670, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x3671, 0xee},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x3672, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x3673, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x3674, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {0x3675, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0x3676, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0x367a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {0x367b, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {0x367c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {0x367d, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {0x3690, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {0x3691, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0x3692, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {0x3699, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {0x369a, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {0x369b, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {0x369c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {0x369d, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {0x36a2, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {0x36a3, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {0x36ea, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {0x36eb, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {0x36ec, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {0x36ed, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {0x36fa, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {0x36fb, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {0x36fc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {0x36fd, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {0x3902, 0xc5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {0x3905, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {0x3908, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {0x391b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {0x391c, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {0x391d, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {0x3933, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {0x3934, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {0x3940, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {0x3942, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {0x3943, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {0x3980, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {0x3981, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {0x3982, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {0x3983, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {0x3984, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {0x3985, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {0x3986, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {0x3987, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {0x3988, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {0x3989, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {0x398a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {0x398b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {0x398c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {0x398d, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {0x398e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {0x398f, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {0x3990, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {0x3991, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {0x3992, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {0x3993, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {0x3994, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {0x3995, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {0x3996, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {0x3997, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {0x3998, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {0x3999, 0xf8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {0x399a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {0x399b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {0x399c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {0x399d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {0x399e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {0x399f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {0x39a0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {0x39a1, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {0x39a2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {0x39a3, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {0x39af, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {0x39b5, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {0x39b6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {0x39b7, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {0x39b8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {0x39b9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {0x39ba, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {0x39bb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {0x39bc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {0x39bd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {0x39be, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {0x39bf, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {0x39c0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {0x39c1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {0x39c5, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {0x39c8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {0x39db, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {0x39dc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {0x39de, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {0x39df, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {0x39e0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {0x39e1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {0x39e2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {0x39e3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {0x39e8, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {0x3e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {0x3e01, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {0x3e02, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {0x3e03, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {0x3e04, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {0x3e05, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {0x3e06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {0x3e07, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {0x3e08, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {0x3e09, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {0x3e10, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {0x3e11, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {0x3e12, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {0x3e13, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {0x3e14, 0xb1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {0x3e23, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {0x3e24, 0xba},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {0x3e25, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {0x3e26, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {0x4500, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {0x4501, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {0x4506, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {0x4509, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {0x4800, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {0x4816, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {0x4818, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {0x4819, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {0x481a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {0x481b, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {0x481c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {0x481d, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {0x4821, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {0x4822, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {0x4823, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {0x4828, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {0x4829, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {0x4837, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {0x5784, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {0x5785, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {0x5787, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {0x5788, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {0x5789, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {0x578a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {0x578b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {0x578c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {0x5790, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {0x5791, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {0x5792, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {0x5793, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {0x5794, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {0x5795, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {0x57c4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {0x57c5, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {0x57c7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {0x57c8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {0x57c9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {0x57ca, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {0x57cb, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {0x57cc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {0x57d0, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {0x57d1, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {0x57d2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {0x57d3, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {0x57d4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {0x57d5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {0x5988, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {0x598e, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {0x598f, 0xc6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {0x5a88, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {0x5a8e, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {0x5a8f, 0xc6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {0x36e9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {0x36f9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * mipi_datarate per lane 405Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static const struct regval sc4238_linear12bit_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {0x3018, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {0x301f, 0x96},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {0x3031, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {0x3037, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {0x3038, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {0x3106, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {0x3200, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {0x3201, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {0x3202, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {0x3203, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {0x3204, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {0x3205, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {0x3206, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {0x3207, 0xf7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {0x3208, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {0x3209, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {0x320a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {0x320b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {0x320c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {0x320d, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {0x320e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {0x320f, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {0x3211, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {0x3213, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {0x3251, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {0x3253, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {0x325f, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {0x3273, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {0x3301, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {0x3304, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {0x3306, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {0x3308, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {0x3309, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {0x330b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {0x330e, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {0x3314, 0x94},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {0x331e, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {0x331f, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {0x3320, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {0x334c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {0x3352, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {0x3356, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {0x335e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {0x335f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {0x3363, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {0x3364, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {0x3366, 0x92},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {0x336d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {0x337a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {0x337b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {0x337c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {0x337d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {0x337f, 0x2d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {0x3390, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {0x3391, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {0x3392, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {0x3393, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {0x3394, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {0x3395, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {0x3399, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {0x33a2, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {0x33a3, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {0x33e0, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {0x33e1, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {0x33e2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {0x33e3, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {0x33e4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {0x33e5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {0x33e6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {0x33e7, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {0x33e8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {0x33e9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {0x33ea, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {0x33eb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {0x33ec, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {0x33ed, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {0x33ee, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {0x33ef, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {0x33f4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {0x33f5, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {0x33f6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {0x33f7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {0x33f8, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {0x33f9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {0x33fa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {0x33fb, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {0x33fc, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {0x33fd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {0x33fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {0x33ff, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {0x360f, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {0x3622, 0xee},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {0x3625, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {0x3630, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {0x3631, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {0x3633, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {0x3634, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {0x3635, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {0x3636, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {0x3637, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {0x3638, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {0x363a, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {0x363b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {0x366e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {0x3670, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {0x3671, 0xee},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {0x3672, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {0x3673, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {0x3674, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {0x3675, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {0x3676, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {0x367a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {0x367b, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {0x367c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {0x367d, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {0x3690, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {0x3691, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {0x3692, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {0x3699, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {0x369a, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {0x369b, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {0x369c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {0x369d, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {0x36a2, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {0x36a3, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {0x36ea, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {0x36eb, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {0x36ec, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {0x36ed, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {0x36fa, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {0x36fb, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {0x36fc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {0x36fd, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {0x3902, 0xc5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {0x3905, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {0x3908, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {0x391b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {0x391c, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {0x3933, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {0x3934, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {0x3940, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {0x3942, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {0x3943, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {0x3980, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {0x3981, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {0x3982, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {0x3983, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {0x3984, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {0x3985, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {0x3986, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {0x3987, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {0x3988, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {0x3989, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {0x398a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {0x398b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {0x398c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {0x398d, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {0x398e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {0x398f, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {0x3990, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {0x3991, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {0x3992, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {0x3993, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {0x3994, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {0x3995, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {0x3996, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {0x3997, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {0x3998, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {0x3999, 0xf8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {0x399a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {0x399b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {0x399c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {0x399d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {0x399e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {0x399f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {0x39a0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {0x39a1, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {0x39a2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {0x39a3, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {0x39af, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {0x39b5, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {0x39b6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {0x39b7, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {0x39b8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {0x39b9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {0x39ba, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {0x39bb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {0x39bc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {0x39bd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {0x39be, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {0x39bf, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {0x39c0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {0x39c1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {0x39c5, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {0x39c8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {0x39db, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {0x39dc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {0x39de, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {0x39df, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {0x39e0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {0x39e1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {0x39e2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {0x39e3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {0x3e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {0x3e01, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {0x3e02, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {0x3e03, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {0x3e06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {0x3e07, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {0x3e08, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {0x3e09, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {0x3e14, 0xb1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {0x3e25, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {0x3e26, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) {0x4501, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {0x4509, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {0x4800, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {0x4818, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {0x4819, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {0x481a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {0x481b, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {0x481c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {0x481d, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {0x4821, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {0x4822, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {0x4823, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {0x4828, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {0x4829, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {0x4837, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {0x5784, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {0x5785, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {0x5787, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {0x5788, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {0x5789, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {0x578a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {0x578b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {0x578c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {0x5790, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {0x5791, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {0x5792, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {0x5793, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {0x5794, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) {0x5795, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) {0x57c4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {0x57c5, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {0x57c7, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {0x57c8, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {0x57c9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {0x57ca, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {0x57cb, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {0x57cc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {0x57d0, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {0x57d1, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {0x57d2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {0x57d3, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {0x57d4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {0x57d5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {0x5988, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {0x598e, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {0x598f, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {0x36e9, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {0x36f9, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) * Xclk 27Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * mipi_datarate per lane 405Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static const struct regval sc4238_linear12bit_2560x1440_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {0x3018, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {0x301f, 0x91},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {0x3031, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {0x3037, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {0x3038, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {0x3106, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {0x3200, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {0x3201, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {0x3202, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {0x3203, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {0x3204, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {0x3205, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) {0x3206, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) {0x3207, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {0x3208, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {0x3209, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) {0x320a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {0x320b, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {0x320c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) {0x320d, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {0x320e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {0x320f, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {0x3210, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {0x3211, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {0x3212, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {0x3213, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {0x3251, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {0x3253, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {0x325f, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {0x3273, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {0x3301, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) {0x3304, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {0x3306, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {0x3308, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {0x3309, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {0x330b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {0x330e, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) {0x3314, 0x94},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {0x331e, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) {0x331f, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) {0x3320, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {0x334c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {0x3352, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) {0x3356, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) {0x335e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {0x335f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {0x3363, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {0x3364, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {0x3366, 0x92},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {0x336d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {0x337a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {0x337b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {0x337c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {0x337d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {0x337f, 0x2d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) {0x3390, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) {0x3391, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {0x3392, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) {0x3393, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {0x3394, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {0x3395, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {0x3399, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {0x33a2, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) {0x33a3, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) {0x33e0, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {0x33e1, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {0x33e2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {0x33e3, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {0x33e4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) {0x33e5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {0x33e6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {0x33e7, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) {0x33e8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) {0x33e9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {0x33ea, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {0x33eb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {0x33ec, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {0x33ed, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) {0x33ee, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {0x33ef, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) {0x33f4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) {0x33f5, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {0x33f6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {0x33f7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) {0x33f8, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {0x33f9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {0x33fa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {0x33fb, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) {0x33fc, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {0x33fd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {0x33fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) {0x33ff, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) {0x360f, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {0x3622, 0xee},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {0x3625, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {0x3630, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) {0x3631, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {0x3633, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {0x3634, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) {0x3635, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) {0x3636, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) {0x3637, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {0x3638, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) {0x363a, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {0x363b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {0x366e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) {0x3670, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {0x3671, 0xee},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {0x3672, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) {0x3673, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) {0x3674, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {0x3675, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {0x3676, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) {0x367a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {0x367b, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) {0x367c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {0x367d, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {0x3690, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) {0x3691, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {0x3692, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) {0x3699, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {0x369a, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {0x369b, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {0x369c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {0x369d, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) {0x36a2, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) {0x36a3, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {0x36ea, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) {0x36eb, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) {0x36ec, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {0x36ed, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) {0x36fa, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) {0x36fb, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {0x36fc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {0x36fd, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) {0x3902, 0xc5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) {0x3905, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {0x3908, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) {0x391b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {0x391c, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) {0x3933, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) {0x3934, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {0x3940, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {0x3942, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {0x3943, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) {0x3980, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) {0x3981, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {0x3982, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {0x3983, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {0x3984, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {0x3985, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) {0x3986, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) {0x3987, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {0x3988, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) {0x3989, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) {0x398a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) {0x398b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {0x398c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {0x398d, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) {0x398e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {0x398f, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) {0x3990, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) {0x3991, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) {0x3992, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {0x3993, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) {0x3994, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) {0x3995, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) {0x3996, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) {0x3997, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {0x3998, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {0x3999, 0xf8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) {0x399a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) {0x399b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {0x399c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {0x399d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) {0x399e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) {0x399f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) {0x39a0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) {0x39a1, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) {0x39a2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) {0x39a3, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) {0x39af, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {0x39b5, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) {0x39b6, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) {0x39b7, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {0x39b8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) {0x39b9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) {0x39ba, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {0x39bb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {0x39bc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) {0x39bd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) {0x39be, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {0x39bf, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {0x39c0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {0x39c1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) {0x39c5, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {0x39c8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) {0x39db, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {0x39dc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) {0x39de, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {0x39df, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {0x39e0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {0x39e1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) {0x39e2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {0x39e3, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {0x3e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {0x3e01, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {0x3e02, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {0x3e03, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {0x3e06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {0x3e07, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) {0x3e08, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) {0x3e09, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) {0x3e14, 0xb1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {0x3e25, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) {0x3e26, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {0x4501, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {0x4509, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) {0x4800, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) {0x4818, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) {0x4819, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {0x481a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {0x481b, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) {0x481c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {0x481d, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {0x4821, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) {0x4822, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) {0x4823, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {0x4828, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) {0x4829, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {0x4837, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {0x5784, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) {0x5785, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {0x5787, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) {0x5788, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) {0x5789, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {0x578a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {0x578b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) {0x578c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) {0x5790, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {0x5791, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {0x5792, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) {0x5793, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {0x5794, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {0x5795, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) {0x57c4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) {0x57c5, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) {0x57c7, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) {0x57c8, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) {0x57c9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {0x57ca, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) {0x57cb, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) {0x57cc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) {0x57d0, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) {0x57d1, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) {0x57d2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) {0x57d3, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {0x57d4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {0x57d5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) {0x5988, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) {0x598e, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) {0x598f, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) {0x36e9, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) {0x36f9, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * The width and height must be configured to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) * the same as the current output resolution of the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) * The input width of the isp needs to be 16 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) * The input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) * If the width or height does not meet the alignment rules,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * you can configure the cropping parameters with the following function to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * crop out the appropriate resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * struct v4l2_subdev_pad_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * .get_selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) static const struct sc4238_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .width = 2688,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .height = 1520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .exp_def = 0x0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .hts_def = 0x05A0 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .vts_def = 0x0752,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .reg_list = sc4238_linear10bit_2688x1520_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) .link_freq = 0, /* an index in link_freq[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .pixel_rate = PIXEL_RATE_WITH_200M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .width = 2688,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .height = 1520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /*.denominator = 300000,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .exp_def = 0x0c00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .hts_def = 0x060e * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .vts_def = 0x0e83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /*.vts_def = 0x0c18,*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .reg_list = sc4238_hdr10bit_2688x1520_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .link_freq = 1, /* an index in link_freq[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) .pixel_rate = PIXEL_RATE_WITH_360M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .width = 2688,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .height = 1520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .exp_def = 0x0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .hts_def = 0x05a0 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .vts_def = 0x061a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .reg_list = sc4238_linear12bit_2688x1520_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .link_freq = 0, /* an index in link_freq[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) .pixel_rate = PIXEL_RATE_WITH_200M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .bus_fmt = MEDIA_BUS_FMT_SBGGR12_1X12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .width = 2560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .height = 1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .exp_def = 0x0500,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .hts_def = 0x05a0 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .vts_def = 0x061a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .reg_list = sc4238_linear12bit_2560x1440_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .link_freq = 0, /* an index in link_freq[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .pixel_rate = PIXEL_RATE_WITH_200M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) MIPI_FREQ_200M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) MIPI_FREQ_360M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) static const char * const sc4238_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) static int __sc4238_power_on(struct sc4238 *sc4238);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) static int sc4238_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) static int sc4238_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) ret |= sc4238_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) SC4238_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) static int sc4238_read_reg(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static int sc4238_get_reso_dist(const struct sc4238_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static const struct sc4238_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) sc4238_find_best_fit(struct sc4238 *sc4238, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) for (i = 0; i < sc4238->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) dist = sc4238_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) (supported_modes[i].bus_fmt == framefmt->code)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static int sc4238_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) struct sc4238 *sc4238 = to_sc4238(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) const struct sc4238_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) mutex_lock(&sc4238->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) mode = sc4238_find_best_fit(sc4238, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) mutex_unlock(&sc4238->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) sc4238->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) __v4l2_ctrl_modify_range(sc4238->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) __v4l2_ctrl_modify_range(sc4238->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) SC4238_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) __v4l2_ctrl_s_ctrl_int64(sc4238->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) mode->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) __v4l2_ctrl_s_ctrl(sc4238->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) mode->link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) sc4238->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) sc4238->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) mutex_unlock(&sc4238->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) static int sc4238_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) struct sc4238 *sc4238 = to_sc4238(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) const struct sc4238_mode *mode = sc4238->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) mutex_lock(&sc4238->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) mutex_unlock(&sc4238->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) mutex_unlock(&sc4238->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) static int sc4238_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) struct sc4238 *sc4238 = to_sc4238(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) code->code = sc4238->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) static int sc4238_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) struct sc4238 *sc4238 = to_sc4238(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) if (fse->index >= sc4238->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (fse->code != supported_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) static int sc4238_enable_test_pattern(struct sc4238 *sc4238, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) ret = sc4238_read_reg(sc4238->client, SC4238_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) SC4238_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) val |= SC4238_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) val &= ~SC4238_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) ret |= sc4238_write_reg(sc4238->client, SC4238_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) SC4238_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) static int sc4238_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) struct sc4238 *sc4238 = to_sc4238(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) const struct sc4238_mode *mode = sc4238->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if (sc4238->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) fi->interval = sc4238->cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) static int sc4238_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) struct sc4238 *sc4238 = to_sc4238(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) const struct sc4238_mode *mode = sc4238->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) if (mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) val = SC4238_LANES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if (mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) val = SC4238_LANES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) static void sc4238_get_module_inf(struct sc4238 *sc4238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) strlcpy(inf->base.sensor, SC4238_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) strlcpy(inf->base.module, sc4238->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) strlcpy(inf->base.lens, sc4238->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) static int sc4238_get_gain_reg(struct sc4238 *sc4238, u32 total_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) u32 *again_coarse_reg, u32 *again_fine_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) u32 *dgain_coarse_reg, u32 *dgain_fine_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) u32 again, dgain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) if (total_gain > 32004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) dev_err(&sc4238->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) "total_gain max is 15.875*31.5*64, current total_gain is %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) total_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (total_gain > 1016) {/*15.875*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) again = 1016;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) dgain = total_gain * 128 / 1016;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) again = total_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) dgain = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (again < 0x80) { /*1x ~ 2x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) *again_fine_reg = again & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) *again_coarse_reg = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) } else if (again < 0x100) { /*2x ~ 4x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) *again_fine_reg = (again >> 1) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) *again_coarse_reg = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) } else if (again < 0x200) { /*4x ~ 8x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) *again_fine_reg = (again >> 2) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) *again_coarse_reg = 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) } else { /*8x ~ 16x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) *again_fine_reg = (again >> 3) & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) *again_coarse_reg = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) if (dgain < 0x100) { /*1x ~ 2x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) *dgain_fine_reg = dgain & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) *dgain_coarse_reg = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) } else if (dgain < 0x200) { /*2x ~ 4x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) *dgain_fine_reg = (dgain >> 1) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) *dgain_coarse_reg = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) } else if (dgain < 0x400) { /*4x ~ 8x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) *dgain_fine_reg = (dgain >> 2) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) *dgain_coarse_reg = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) } else if (dgain < 0x800) { /*8x ~ 16x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) *dgain_fine_reg = (dgain >> 3) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) *dgain_coarse_reg = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) } else { /*16x ~ 31.5x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) *dgain_fine_reg = (dgain >> 4) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) *dgain_coarse_reg = 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) dev_dbg(&sc4238->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) "total_gain 0x%x again_coarse 0x%x, again_fine 0x%x, dgain_coarse 0x%x, dgain_fine 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) total_gain, *again_coarse_reg, *again_fine_reg, *dgain_coarse_reg, *dgain_fine_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) static int sc4238_set_hdrae(struct sc4238 *sc4238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) u32 l_a_gain, m_a_gain, s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) u32 again_coarse_reg, again_fine_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) u32 dgain_coarse_reg, dgain_fine_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) u32 max_exp_l, max_exp_s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) u32 rhs1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) if (!sc4238->has_init_exp && !sc4238->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) sc4238->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) sc4238->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) dev_info(&sc4238->client->dev, "sc4238 don't stream, record exp for hdr!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) l_a_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) m_a_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) s_a_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) dev_dbg(&sc4238->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) l_exp_time, l_a_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) m_exp_time, m_a_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) s_exp_time, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) if (sc4238->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) //2 stagger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) l_a_gain = m_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) l_exp_time = m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) m_a_gain = s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) m_exp_time = s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) if (l_a_gain != m_a_gain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) dev_err(&sc4238->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) "gain of long frame must same with short frame, 0x%x != 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) l_a_gain, m_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) /* long frame exp max = 2*({320e,320f} -{3e23,3e24} -9) ,unit 1/2 line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) /* short frame exp max = 2*({3e23,3e24} - 8) ,unit 1/2 line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) //max short exposure limit to 3 ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) rhs1 = 286;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) max_exp_l = sc4238->cur_vts - rhs1 - 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) max_exp_s = rhs1 - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (l_exp_time > max_exp_l || m_exp_time > max_exp_s || l_exp_time <= m_exp_time) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) dev_err(&sc4238->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) "max_exp_long %d, max_exp_short %d, cur_exp_long %d, cur_exp_short %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) max_exp_l, max_exp_s, l_exp_time, m_exp_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) ret = sc4238_get_gain_reg(sc4238, l_a_gain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) &again_coarse_reg, &again_fine_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) &dgain_coarse_reg, &dgain_fine_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) dev_dbg(&sc4238->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) "max exposure reg limit 0x%x-8 line\n", rhs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) ret |= sc4238_write_reg(sc4238->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) SC4238_REG_EXP_MAX_MID_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) SC4238_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) rhs1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) ret |= sc4238_write_reg(sc4238->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) SC4238_REG_EXP_LONG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) SC4238_REG_VALUE_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) l_exp_time << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) ret |= sc4238_write_reg(sc4238->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) SC4238_REG_EXP_MID_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) SC4238_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) m_exp_time << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) ret |= sc4238_write_reg(sc4238->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) SC4238_REG_COARSE_AGAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) SC4238_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) again_coarse_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) ret |= sc4238_write_reg(sc4238->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) SC4238_REG_FINE_AGAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) SC4238_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) again_fine_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) ret |= sc4238_write_reg(sc4238->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) SC4238_REG_COARSE_AGAIN_S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) SC4238_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) again_coarse_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) ret |= sc4238_write_reg(sc4238->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) SC4238_REG_FINE_AGAIN_S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) SC4238_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) again_fine_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) ret |= sc4238_write_reg(sc4238->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) SC4238_REG_COARSE_DGAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) SC4238_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) dgain_coarse_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) ret |= sc4238_write_reg(sc4238->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) SC4238_REG_FINE_DGAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) SC4238_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) dgain_fine_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) ret |= sc4238_write_reg(sc4238->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) SC4238_REG_COARSE_DGAIN_S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) SC4238_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) dgain_coarse_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) ret |= sc4238_write_reg(sc4238->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) SC4238_REG_FINE_DGAIN_S,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) SC4238_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) dgain_fine_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) static int sc4238_get_channel_info(struct sc4238 *sc4238, struct rkmodule_channel_info *ch_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) ch_info->vc = sc4238->cur_mode->vc[ch_info->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) ch_info->width = sc4238->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) ch_info->height = sc4238->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) ch_info->bus_fmt = sc4238->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static long sc4238_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) struct sc4238 *sc4238 = to_sc4238(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) struct rkmodule_hdr_cfg *hdr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) return sc4238_set_hdrae(sc4238, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) w = sc4238->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) h = sc4238->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) dev_info(&sc4238->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) "%s config hdr mode: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) __func__, hdr_cfg->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) for (i = 0; i < sc4238->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) sc4238->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) if (i == sc4238->cfg_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) dev_err(&sc4238->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) hdr_cfg->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) w = sc4238->cur_mode->hts_def - sc4238->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) h = sc4238->cur_mode->vts_def - sc4238->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) __v4l2_ctrl_modify_range(sc4238->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) __v4l2_ctrl_modify_range(sc4238->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) SC4238_VTS_MAX - sc4238->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) sc4238->cur_fps = sc4238->cur_mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) sc4238->cur_vts = sc4238->cur_mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) dev_info(&sc4238->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) "sensor mode: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) sc4238->cur_mode->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) sc4238_get_module_inf(sc4238, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) hdr_cfg->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) hdr_cfg->hdr_mode = sc4238->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) ret = sc4238_write_reg(sc4238->client, SC4238_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) SC4238_REG_VALUE_08BIT, SC4238_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) ret = sc4238_write_reg(sc4238->client, SC4238_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) SC4238_REG_VALUE_08BIT, SC4238_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) ch_info = (struct rkmodule_channel_info *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) ret = sc4238_get_channel_info(sc4238, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) static long sc4238_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) ret = sc4238_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) ret = sc4238_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) ret = sc4238_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) ret = sc4238_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) ret = sc4238_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) ret = sc4238_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) if (!ch_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) ret = sc4238_ioctl(sd, cmd, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) ret = copy_to_user(up, ch_info, sizeof(*ch_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) kfree(ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) static int __sc4238_start_stream(struct sc4238 *sc4238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) ret = sc4238_write_array(sc4238->client, sc4238->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) ret = __v4l2_ctrl_handler_setup(&sc4238->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) if (sc4238->has_init_exp && sc4238->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) ret = sc4238_ioctl(&sc4238->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) &sc4238->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) dev_err(&sc4238->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) return sc4238_write_reg(sc4238->client, SC4238_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) SC4238_REG_VALUE_08BIT, SC4238_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) static int __sc4238_stop_stream(struct sc4238 *sc4238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) sc4238->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) if (sc4238->is_thunderboot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) sc4238->is_first_streamoff = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) return sc4238_write_reg(sc4238->client, SC4238_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) SC4238_REG_VALUE_08BIT, SC4238_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) static int sc4238_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) struct sc4238 *sc4238 = to_sc4238(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) struct i2c_client *client = sc4238->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) dev_info(&client->dev, "%s: on: %d, %dx%d@%d hdr mode(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) __func__, on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) sc4238->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) sc4238->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) DIV_ROUND_CLOSEST(sc4238->cur_mode->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) sc4238->cur_mode->max_fps.numerator),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) sc4238->cur_mode->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) mutex_lock(&sc4238->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) if (on == sc4238->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) if (sc4238->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) sc4238->is_thunderboot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) __sc4238_power_on(sc4238);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) ret = __sc4238_start_stream(sc4238);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) __sc4238_stop_stream(sc4238);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) sc4238->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) mutex_unlock(&sc4238->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) static int sc4238_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) struct sc4238 *sc4238 = to_sc4238(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) struct i2c_client *client = sc4238->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) mutex_lock(&sc4238->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) if (sc4238->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) ret = sc4238_write_array(sc4238->client, sc4238_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) sc4238->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) sc4238->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) mutex_unlock(&sc4238->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) static inline u32 sc4238_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) return DIV_ROUND_UP(cycles, SC4238_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) static int __sc4238_power_on(struct sc4238 *sc4238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) struct device *dev = &sc4238->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) if (sc4238->is_thunderboot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) if (!IS_ERR_OR_NULL(sc4238->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) ret = pinctrl_select_state(sc4238->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) sc4238->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) ret = clk_set_rate(sc4238->xvclk, SC4238_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) if (clk_get_rate(sc4238->xvclk) != SC4238_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) ret = clk_prepare_enable(sc4238->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) if (!IS_ERR(sc4238->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) gpiod_set_value_cansleep(sc4238->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) ret = regulator_bulk_enable(SC4238_NUM_SUPPLIES, sc4238->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) if (!IS_ERR(sc4238->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) gpiod_set_value_cansleep(sc4238->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) if (!IS_ERR(sc4238->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) gpiod_set_value_cansleep(sc4238->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) * There is no need to wait for the delay of RC circuit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) * if the reset signal is directly controlled by GPIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) if (!IS_ERR(sc4238->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) usleep_range(6000, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) usleep_range(12000, 16000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) delay_us = sc4238_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) clk_disable_unprepare(sc4238->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) static void __sc4238_power_off(struct sc4238 *sc4238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) struct device *dev = &sc4238->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (sc4238->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) if (sc4238->is_first_streamoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) sc4238->is_thunderboot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) sc4238->is_first_streamoff = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) if (!IS_ERR(sc4238->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) gpiod_set_value_cansleep(sc4238->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) clk_disable_unprepare(sc4238->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) if (!IS_ERR(sc4238->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) gpiod_set_value_cansleep(sc4238->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) if (!IS_ERR_OR_NULL(sc4238->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) ret = pinctrl_select_state(sc4238->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) sc4238->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) if (sc4238->is_thunderboot_ng) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) sc4238->is_thunderboot_ng = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) regulator_bulk_disable(SC4238_NUM_SUPPLIES, sc4238->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) static int sc4238_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) struct sc4238 *sc4238 = to_sc4238(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) return __sc4238_power_on(sc4238);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) static int sc4238_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) struct sc4238 *sc4238 = to_sc4238(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) __sc4238_power_off(sc4238);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) static int sc4238_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) struct sc4238 *sc4238 = to_sc4238(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) const struct sc4238_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) mutex_lock(&sc4238->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) mutex_unlock(&sc4238->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) static int sc4238_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) struct sc4238 *sc4238 = to_sc4238(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) if (fie->index >= sc4238->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) static const struct dev_pm_ops sc4238_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) SET_RUNTIME_PM_OPS(sc4238_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) sc4238_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) static const struct v4l2_subdev_internal_ops sc4238_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) .open = sc4238_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) static const struct v4l2_subdev_core_ops sc4238_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .s_power = sc4238_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) .ioctl = sc4238_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .compat_ioctl32 = sc4238_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) static const struct v4l2_subdev_video_ops sc4238_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) .s_stream = sc4238_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .g_frame_interval = sc4238_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) static const struct v4l2_subdev_pad_ops sc4238_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) .enum_mbus_code = sc4238_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) .enum_frame_size = sc4238_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) .enum_frame_interval = sc4238_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) .get_fmt = sc4238_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) .set_fmt = sc4238_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .get_mbus_config = sc4238_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) static const struct v4l2_subdev_ops sc4238_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .core = &sc4238_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) .video = &sc4238_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .pad = &sc4238_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) static void sc4238_modify_fps_info(struct sc4238 *sc4238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) const struct sc4238_mode *mode = sc4238->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) sc4238->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) sc4238->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) static int sc4238_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) struct sc4238 *sc4238 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) struct sc4238, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) struct i2c_client *client = sc4238->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) u32 again_coarse_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) u32 again_fine_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) u32 dgain_coarse_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) u32 dgain_fine_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) dev_dbg(&client->dev, "ctrl->id(0x%x) val 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) max = sc4238->cur_mode->height + ctrl->val - 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) __v4l2_ctrl_modify_range(sc4238->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) sc4238->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) sc4238->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) sc4238->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) ret = sc4238_write_reg(sc4238->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) SC4238_REG_EXP_LONG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) SC4238_REG_VALUE_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) ctrl->val << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) dev_dbg(&client->dev, "set exposure 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) ret = sc4238_get_gain_reg(sc4238, ctrl->val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) &again_coarse_reg, &again_fine_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) &dgain_coarse_reg, &dgain_fine_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) ret |= sc4238_write_reg(sc4238->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) SC4238_REG_COARSE_AGAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) SC4238_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) again_coarse_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) ret |= sc4238_write_reg(sc4238->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) SC4238_REG_FINE_AGAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) SC4238_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) again_fine_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) ret |= sc4238_write_reg(sc4238->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) SC4238_REG_COARSE_DGAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) SC4238_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) dgain_coarse_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) ret |= sc4238_write_reg(sc4238->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) SC4238_REG_FINE_DGAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) SC4238_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) dgain_fine_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) dev_dbg(&client->dev, "set analog gain 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) ret = sc4238_write_reg(sc4238->client, SC4238_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) SC4238_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) ctrl->val + sc4238->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) sc4238->cur_vts = ctrl->val + sc4238->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) if (sc4238->cur_vts != sc4238->cur_mode->vts_def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) sc4238_modify_fps_info(sc4238);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) dev_dbg(&client->dev, "set vblank 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) ret = sc4238_enable_test_pattern(sc4238, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) ret = sc4238_read_reg(sc4238->client, SC4238_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) SC4238_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) val |= MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) val &= ~MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) ret |= sc4238_write_reg(sc4238->client, SC4238_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) SC4238_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) sc4238->flip = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) ret = sc4238_read_reg(sc4238->client, SC4238_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) SC4238_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) val |= FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) val &= ~FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) ret |= sc4238_write_reg(sc4238->client, SC4238_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) SC4238_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) sc4238->flip = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) static const struct v4l2_ctrl_ops sc4238_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .s_ctrl = sc4238_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) static int sc4238_initialize_controls(struct sc4238 *sc4238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) const struct sc4238_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) u64 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) dev_info(&sc4238->client->dev, "%s(%d)", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) handler = &sc4238->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) mode = sc4238->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) handler->lock = &sc4238->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) sc4238->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) 1, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) if (sc4238->cur_mode->bus_fmt == MEDIA_BUS_FMT_SBGGR10_1X10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) dst_pixel_rate = PIXEL_RATE_WITH_360M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) dst_link_freq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) dst_pixel_rate = PIXEL_RATE_WITH_200M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) sc4238->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) 0, PIXEL_RATE_WITH_360M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) 1, dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) __v4l2_ctrl_s_ctrl(sc4238->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) sc4238->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) if (sc4238->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) sc4238->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) sc4238->vblank = v4l2_ctrl_new_std(handler, &sc4238_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) SC4238_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) exposure_max = mode->vts_def - 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) sc4238->exposure = v4l2_ctrl_new_std(handler, &sc4238_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) V4L2_CID_EXPOSURE, SC4238_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) exposure_max, SC4238_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) sc4238->anal_gain = v4l2_ctrl_new_std(handler, &sc4238_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) V4L2_CID_ANALOGUE_GAIN, SC4238_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) SC4238_GAIN_MAX, SC4238_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) SC4238_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) sc4238->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) &sc4238_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) ARRAY_SIZE(sc4238_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) 0, 0, sc4238_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) sc4238->h_flip = v4l2_ctrl_new_std(handler, &sc4238_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) sc4238->v_flip = v4l2_ctrl_new_std(handler, &sc4238_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) sc4238->flip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) dev_err(&sc4238->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) sc4238->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) sc4238->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) sc4238->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) sc4238->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) static int sc4238_check_sensor_id(struct sc4238 *sc4238,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) struct device *dev = &sc4238->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) if (sc4238->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) ret = sc4238_read_reg(client, SC4238_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) SC4238_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) dev_info(dev, "Detected SC%06x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) static int sc4238_configure_regulators(struct sc4238 *sc4238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) for (i = 0; i < SC4238_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) sc4238->supplies[i].supply = sc4238_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) return devm_regulator_bulk_get(&sc4238->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) SC4238_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) sc4238->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) static int sc4238_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) struct sc4238 *sc4238;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) sc4238 = devm_kzalloc(dev, sizeof(*sc4238), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) if (!sc4238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) &sc4238->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) &sc4238->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) &sc4238->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) &sc4238->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) sc4238->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) hdr_mode = NO_HDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) dev_warn(dev, " Get hdr mode failed! no hdr default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) sc4238->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) for (i = 0; i < sc4238->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) sc4238->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) if (sc4238->cur_mode == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) sc4238->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) sc4238->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) sc4238->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) if (IS_ERR(sc4238->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) sc4238->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) if (IS_ERR(sc4238->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) sc4238->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) if (IS_ERR(sc4238->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) sc4238->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) if (!IS_ERR(sc4238->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) sc4238->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) pinctrl_lookup_state(sc4238->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) if (IS_ERR(sc4238->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) sc4238->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) pinctrl_lookup_state(sc4238->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) if (IS_ERR(sc4238->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) ret = sc4238_configure_regulators(sc4238);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) mutex_init(&sc4238->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) sd = &sc4238->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) v4l2_i2c_subdev_init(sd, client, &sc4238_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) ret = sc4238_initialize_controls(sc4238);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) ret = __sc4238_power_on(sc4238);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) ret = sc4238_check_sensor_id(sc4238, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) sd->internal_ops = &sc4238_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) sc4238->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) ret = media_entity_pads_init(&sd->entity, 1, &sc4238->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) if (strcmp(sc4238->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) sc4238->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) SC4238_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) __sc4238_power_off(sc4238);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) v4l2_ctrl_handler_free(&sc4238->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) mutex_destroy(&sc4238->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) static int sc4238_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) struct sc4238 *sc4238 = to_sc4238(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) v4l2_ctrl_handler_free(&sc4238->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) mutex_destroy(&sc4238->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) __sc4238_power_off(sc4238);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) static const struct of_device_id sc4238_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) { .compatible = "smartsens,sc4238" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) MODULE_DEVICE_TABLE(of, sc4238_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) static const struct i2c_device_id sc4238_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) { "smartsens,sc4238", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) static struct i2c_driver sc4238_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) .name = SC4238_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) .pm = &sc4238_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) .of_match_table = of_match_ptr(sc4238_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .probe = &sc4238_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) .remove = &sc4238_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) .id_table = sc4238_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) module_i2c_driver(sc4238_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) return i2c_add_driver(&sc4238_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) i2c_del_driver(&sc4238_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) MODULE_DESCRIPTION("Smartsens sc4238 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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