^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sc4210 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) //#define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <media/v4l2-image-sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <stdarg.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/linkage.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/printk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SC4210_LINK_FREQ_2LANE_LINEAR 303000000 // 607.5Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC4210_LINK_FREQ_2LANE_HDR2 540000000 // 1080Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SC4210_LINK_FREQ_4LANE_LINEAR 202500000 // 405Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SC4210_LINK_FREQ_4LANE_HDR2 364500000 // 729Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SC4210_PIXEL_RATES_2LANE_LINEAR (SC4210_LINK_FREQ_2LANE_LINEAR / 10 * 2 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SC4210_PIXEL_RATES_2LANE_HDR2 (SC4210_LINK_FREQ_2LANE_HDR2 / 10 * 2 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SC4210_PIXEL_RATES_4LANE_LINEAR (SC4210_LINK_FREQ_4LANE_LINEAR / 10 * 4 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SC4210_PIXEL_RATES_4LANE_HDR2 (SC4210_LINK_FREQ_4LANE_HDR2 / 10 * 4 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SC4210_MAX_PIXEL_RATE (SC4210_LINK_FREQ_4LANE_HDR2 / 10 * 4 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SC4210_XVCLK_FREQ 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SC4210_CHIP_ID 0x4210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SC4210_REG_CHIP_ID 0x3107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC4210_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SC4210_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SC4210_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SC4210_REG_EXPOSURE_H 0x3e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SC4210_REG_EXPOSURE_M 0x3e01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SC4210_REG_EXPOSURE_L 0x3e02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SC4210_EXPOSURE_MIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SC4210_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SC4210_REG_DIG_GAIN 0x3e06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SC4210_REG_DIG_FINE_GAIN 0x3e07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SC4210_REG_ANA_GAIN 0x3e08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SC4210_REG_ANA_FINE_GAIN 0x3e09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SC4210_GAIN_MIN 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SC4210_GAIN_MAX (43.65 * 32 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SC4210_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SC4210_GAIN_DEFAULT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SC4210_REG_VTS_H 0x320e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SC4210_REG_VTS_L 0x320f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SC4210_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SC4210_SOFTWARE_RESET_REG 0x0103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) // short frame exposure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SC4210_REG_SHORT_EXPOSURE_H 0x3e22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SC4210_REG_SHORT_EXPOSURE_M 0x3e04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SC4210_REG_SHORT_EXPOSURE_L 0x3e05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SC4210_REG_MAX_SHORT_EXP_H 0x3e23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SC4210_REG_MAX_SHORT_EXP_L 0x3e24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SC4210_HDR_EXPOSURE_MIN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SC4210_HDR_EXPOSURE_STEP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SC4210_MAX_SHORT_EXPOSURE 608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) // short frame gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SC4210_REG_SDIG_GAIN 0x3e10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SC4210_REG_SDIG_FINE_GAIN 0x3e11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SC4210_REG_SANA_GAIN 0x3e12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SC4210_REG_SANA_FINE_GAIN 0x3e13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) //group hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SC4210_GROUP_UPDATE_ADDRESS 0x3800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SC4210_GROUP_UPDATE_START_DATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SC4210_GROUP_UPDATE_END_DATA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SC4210_GROUP_UPDATE_LAUNCH 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SC4210_FLIP_MIRROR_REG 0x3221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SC4210_FLIP_MASK 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SC4210_MIRROR_MASK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SC4210_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SC4210_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SC4210_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SC4210_NAME "sc4210"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SC4210_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SC4210_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SC4210_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const char * const sc4210_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define sc4210_NUM_SUPPLIES ARRAY_SIZE(sc4210_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct sc4210_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 mipi_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct sc4210 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct regulator_bulk_data supplies[sc4210_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) const struct sc4210_mode *support_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) const struct sc4210_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct v4l2_fract cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 support_modes_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned int lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define to_sc4210(sd) container_of(sd, struct sc4210, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * sc4210 27Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * mipi_datarate per lane 405Mbps, 4lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static const struct regval sc4210_linear_10_30fps_2560x1440_4lane_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3001, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x3002, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x300a, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x300f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3018, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x301f, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3031, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3038, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x320c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x320d, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3220, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3225, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3227, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3229, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3231, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3241, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3243, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3249, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3251, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3253, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x325e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x325f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3273, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3301, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3302, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3000, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3304, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3305, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3306, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x3308, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3309, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x330b, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x330e, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3312, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3314, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x331e, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x331f, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x3320, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x3338, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x334c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x335d, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3366, 0x92},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3367, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3368, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3369, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x336a, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x336b, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x336c, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x337a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x337b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x337e, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x33a3, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x33e0, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x33e1, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x33e2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x33e3, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x33e4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x33e5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x33e6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x33e7, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x33e8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x33e9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x33ea, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x33eb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x33ec, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x33ed, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x33ee, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x33ef, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x33f4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x33f5, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x33f6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x33f7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x33f8, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x33f9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x33fa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x33fb, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x33fc, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x33fd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x33fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x33ff, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x360f, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x3622, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x3624, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x3625, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x3630, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x3631, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3632, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x3633, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x3634, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3635, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3636, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x3638, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x363b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x363c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x363d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x366e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x3670, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x3671, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x3672, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3673, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x367a, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x367b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3690, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3691, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x3692, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x3699, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x369a, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x369b, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x369c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x369d, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x36a2, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x36a3, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x36cc, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x36cd, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x36ce, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x36d0, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x36d1, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x36d2, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x36ea, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x36eb, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x36ec, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x36ed, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x36fa, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x36fb, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x36fc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x36fd, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x3817, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x3905, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x3908, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x391b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x391c, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x391d, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x3933, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x3934, 0xf5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x3935, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x3936, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x3940, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x3942, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x3943, 0xf6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x3980, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x3981, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x3982, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x3983, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x3984, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x3985, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x3986, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x3987, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x3988, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x3989, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x398a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x398b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x398c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x398d, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x398e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x398f, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x3990, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x3991, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x3992, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x3993, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x3994, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x3995, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x3996, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x3997, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x3998, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x3999, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x399a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x399b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x399c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x399d, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x399e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x399f, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x39a0, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x39a1, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x39a2, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x39a3, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x39a4, 0x97},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x39a5, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x39a6, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x39a7, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x39a8, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x39a9, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x39aa, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x39ab, 0x95},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x39ac, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x39ad, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x39ae, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x39af, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x39b9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x39ba, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x39bb, 0xba},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x39bc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x39bd, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x39be, 0x99},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x39bf, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x39c0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x39c5, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x3e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x3e01, 0xbb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x3e02, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x3e03, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x3e06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x3e07, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x3e08, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x3e09, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x3e0e, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x3e26, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x4407, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x4418, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x4501, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x4509, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x4603, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x4800, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x4837, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x5000, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x550f, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x5784, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x5785, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x5787, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x5788, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x5789, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x578a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x578b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x578c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x5790, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x5791, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x5792, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x5793, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x5794, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x5795, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x57c4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x57c5, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x57c7, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x57c8, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x57c9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x57ca, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x57cb, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x57cc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x57d0, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x57d1, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x57d2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x57d3, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x57d4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x57d5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x36e9, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x36f9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) //{0x0100, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {REG_NULL, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * sc4210 27Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * mipi_datarate per lane 729Mbps, 4lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static const struct regval sc4210_hdr_10_30fps_2560x1440_4lane_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x3001, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x3002, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x300a, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x300f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x3018, 0x73},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x301f, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x3031, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x3038, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x3207, 0xa7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x320c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x320d, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x320e, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x320f, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x3213, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x3220, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x3225, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x3227, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x3229, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x3231, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x3241, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x3243, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x3249, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x3250, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x3251, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x3253, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x325e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x3000, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x325f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x3273, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x3301, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x3302, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x3304, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x3305, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x3306, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x3308, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x3309, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x330b, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x330e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x3312, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x3314, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x331e, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x331f, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x3320, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x3338, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x334c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x335d, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x335e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x335f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x3360, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x3362, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x3364, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x3366, 0x92},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x3367, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x3368, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x3369, 0xd4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x336a, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x336b, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x336c, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x337a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x337b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x337c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x337d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x337e, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x3390, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x3391, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x3392, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x3393, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x3394, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x3395, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x3396, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x3397, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x3398, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x3399, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x339a, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x339b, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x339c, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x33a2, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x33a3, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x33e0, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x33e1, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x33e2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x33e3, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x33e4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x33e5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x33e6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x33e7, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x33e8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x33e9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x33ea, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x33eb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x33ec, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0x33ed, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {0x33ee, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0x33ef, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x33f4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x33f5, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x33f6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x33f7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x33f8, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x33f9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {0x33fa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {0x33fb, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0x33fc, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x33fd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x33fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {0x33ff, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {0x360f, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {0x3622, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {0x3624, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {0x3625, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {0x3630, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {0x3631, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x3632, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x3633, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x3634, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {0x3635, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x3636, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x3638, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x363b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x363c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x363d, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x366e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x3670, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x3671, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x3672, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x3673, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x3674, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x3675, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x3676, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x367a, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x367b, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x367c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x367d, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x3690, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {0x3691, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0x3692, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0x3699, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {0x369a, 0x96},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {0x369b, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {0x369c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {0x369d, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {0x36a2, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0x36a3, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {0x36cc, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {0x36cd, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {0x36ce, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {0x36d0, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {0x36d1, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {0x36d2, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {0x36ea, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {0x36eb, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {0x36ec, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {0x36ed, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {0x36fa, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {0x36fb, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {0x36fc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {0x36fd, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {0x3817, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {0x3905, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {0x3908, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {0x391b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {0x391c, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {0x391d, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {0x3933, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {0x3934, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {0x3935, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {0x3936, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {0x393e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {0x3940, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {0x3942, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {0x3943, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {0x3980, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {0x3981, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {0x3982, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {0x3983, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {0x3984, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {0x3985, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {0x3986, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {0x3987, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {0x3988, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {0x3989, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {0x398a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {0x398b, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {0x398c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) {0x398d, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {0x398e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {0x398f, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {0x3990, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {0x3991, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {0x3992, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {0x3993, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {0x3994, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {0x3995, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {0x3996, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {0x3997, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {0x3998, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {0x3999, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {0x399a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {0x399b, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {0x399c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {0x399d, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {0x399e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {0x399f, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {0x39a0, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {0x39a1, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {0x39a2, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {0x39a3, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {0x39a4, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {0x39a5, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {0x39a6, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {0x39a7, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {0x39a8, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {0x39a9, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {0x39aa, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {0x39ab, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {0x39ac, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {0x39ad, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {0x39ae, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {0x39af, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {0x39b9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {0x39ba, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {0x39bb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {0x39bc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {0x39bd, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {0x39be, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {0x39bf, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {0x39c0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {0x39c5, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {0x3c09, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {0x3c10, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {0x3c11, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {0x3c12, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {0x3c13, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {0x3c14, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {0x3e00, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {0x3e01, 0x5a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {0x3e02, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {0x3e03, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {0x3e04, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {0x3e05, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {0x3e06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {0x3e07, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {0x3e08, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {0x3e09, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {0x3e0e, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {0x3e10, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {0x3e11, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {0x3e12, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {0x3e13, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {0x3e23, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {0x3e24, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {0x3e26, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {0x4401, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {0x4407, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {0x4418, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {0x4501, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {0x4509, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {0x4603, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {0x4800, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {0x4816, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {0x4819, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {0x4829, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {0x4837, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {0x5000, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {0x550f, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {0x5784, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {0x5785, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {0x5787, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {0x5788, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {0x5789, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {0x578a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {0x578b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {0x578c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {0x5790, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {0x5791, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {0x5792, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {0x5793, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {0x5794, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {0x5795, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {0x57c4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {0x57c5, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {0x57c7, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {0x57c8, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {0x57c9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {0x57ca, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {0x57cb, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {0x57cc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {0x57d0, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {0x57d1, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {0x57d2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {0x57d3, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {0x57d4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {0x57d5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {0x36e9, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {0x36f9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) //{0x0100, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * Xclk 27Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) * mipi_datarate per lane 607.5Mbps, 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static const struct regval sc4210_liner_10_30fps_2560x1440_2lane_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {0x36e9, 0xd1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {0x36f9, 0xd1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {0x3001, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {0x3002, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {0x300a, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {0x300f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {0x3018, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {0x301f, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {0x3031, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {0x3038, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {0x320c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {0x320d, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {0x3220, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {0x3225, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {0x3227, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {0x3229, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {0x3231, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {0x3241, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {0x3243, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {0x3249, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {0x3251, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {0x3253, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {0x325e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {0x325f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {0x3273, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {0x3301, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {0x3302, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {0x3304, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {0x3000, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {0x3305, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {0x3306, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {0x3308, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {0x3309, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {0x330b, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {0x330e, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {0x3312, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {0x3314, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {0x331e, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {0x331f, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {0x3320, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {0x3338, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {0x334c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {0x335d, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {0x3366, 0x92},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {0x3367, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) {0x3368, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {0x3369, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {0x336a, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {0x336b, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {0x336c, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {0x337a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {0x337b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {0x337e, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) {0x33a3, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {0x33e0, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) {0x33e1, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {0x33e2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {0x33e3, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {0x33e4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {0x33e5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {0x33e6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {0x33e7, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {0x33e8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {0x33e9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {0x33ea, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) {0x33eb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {0x33ec, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {0x33ed, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {0x33ee, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {0x33ef, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {0x33f4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {0x33f5, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {0x33f6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {0x33f7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {0x33f8, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {0x33f9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {0x33fa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {0x33fb, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {0x33fc, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {0x33fd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {0x33fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {0x33ff, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {0x360f, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {0x3622, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {0x3624, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {0x3625, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {0x3630, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {0x3631, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {0x3632, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {0x3633, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {0x3634, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {0x3635, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {0x3636, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {0x3638, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {0x363b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {0x363c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {0x363d, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {0x366e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {0x3670, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {0x3671, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {0x3672, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {0x3673, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {0x367a, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {0x367b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) {0x3690, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {0x3691, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {0x3692, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) {0x3699, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {0x369a, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {0x369b, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {0x369c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {0x369d, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {0x36a2, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) {0x36a3, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {0x36cc, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {0x36cd, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) {0x36ce, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {0x36d0, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {0x36d1, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {0x36d2, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {0x36ea, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {0x36eb, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {0x36ec, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {0x36ed, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {0x36fa, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {0x36fb, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {0x36fc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) {0x36fd, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {0x3817, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {0x3905, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {0x3908, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {0x391b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {0x391c, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {0x391d, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {0x3933, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) {0x3934, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {0x3935, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {0x3936, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {0x3940, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {0x3942, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) {0x3943, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) {0x3980, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {0x3981, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {0x3982, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {0x3983, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {0x3984, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {0x3985, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {0x3986, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {0x3987, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {0x3988, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {0x3989, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {0x398a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {0x398b, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {0x398c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {0x398d, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) {0x398e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {0x398f, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {0x3990, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) {0x3991, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {0x3992, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {0x3993, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {0x3994, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {0x3995, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {0x3996, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {0x3997, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {0x3998, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {0x3999, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {0x399a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {0x399b, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {0x399c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {0x399d, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {0x399e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {0x399f, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) {0x39a0, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {0x39a1, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {0x39a2, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {0x39a3, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {0x39a4, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {0x39a5, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {0x39a6, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {0x39a7, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {0x39a8, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {0x39a9, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {0x39aa, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {0x39ab, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) {0x39ac, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {0x39ad, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {0x39ae, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {0x39af, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) {0x39b9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {0x39ba, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {0x39bb, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) {0x39bc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {0x39bd, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {0x39be, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {0x39bf, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {0x39c0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {0x39c5, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) {0x3e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {0x3e01, 0xbb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {0x3e02, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {0x3e03, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {0x3e06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) {0x3e07, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {0x3e08, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) {0x3e09, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {0x3e0e, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {0x3e26, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {0x4401, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {0x4407, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {0x4418, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) {0x4501, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {0x4509, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) {0x4603, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {0x4837, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) {0x5000, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {0x550f, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {0x5784, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {0x5785, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {0x5787, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {0x5788, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {0x5789, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {0x578a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) {0x578b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {0x578c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {0x5790, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {0x5791, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {0x5792, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {0x5793, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {0x5794, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {0x5795, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {0x57c4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {0x57c5, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {0x57c7, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {0x57c8, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {0x57c9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {0x57ca, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {0x57cb, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {0x57cc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {0x57d0, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {0x57d1, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {0x57d2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {0x57d3, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {0x57d4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {0x57d5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {0x36e9, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {0x36f9, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) //{0x0100, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * Xclk 27Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * max_framerate 25fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * mipi_datarate per lane 1080Mbps, 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static const struct regval sc4210_hdr_10_25fps_2560x1440_2lane_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {0x3001, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) {0x3002, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) {0x300a, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {0x300f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {0x3018, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {0x3019, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) {0x301f, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {0x3031, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {0x3038, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {0x3207, 0xa7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {0x320c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {0x320d, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {0x320e, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) {0x320f, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {0x3213, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {0x3220, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) {0x3225, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {0x3227, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {0x3229, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) {0x3231, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {0x3241, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) {0x3243, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {0x3249, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) {0x3250, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {0x3251, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {0x3000, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) {0x3253, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {0x325e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {0x325f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {0x3273, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {0x3301, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {0x3302, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {0x3304, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {0x3305, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) {0x3306, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) {0x3308, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) {0x3309, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {0x330b, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) {0x330e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {0x3312, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {0x3314, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) {0x331e, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {0x331f, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {0x3320, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) {0x3338, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {0x334c, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {0x335d, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {0x335e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {0x335f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {0x3360, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {0x3362, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) {0x3364, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {0x3366, 0x92},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) {0x3367, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {0x3368, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {0x3369, 0xd4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {0x336a, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {0x336b, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {0x336c, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) {0x337a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {0x337b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) {0x337c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) {0x337d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) {0x337e, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {0x3390, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) {0x3391, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) {0x3392, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {0x3393, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) {0x3394, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {0x3395, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) {0x3396, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {0x3397, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) {0x3398, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {0x3399, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {0x339a, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) {0x339b, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {0x339c, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) {0x33a2, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) {0x33a3, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {0x33e0, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) {0x33e1, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {0x33e2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {0x33e3, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {0x33e4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) {0x33e5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) {0x33e6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) {0x33e7, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {0x33e8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {0x33e9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {0x33ea, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {0x33eb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) {0x33ec, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) {0x33ed, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {0x33ee, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) {0x33ef, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) {0x33f4, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {0x33f5, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {0x33f6, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {0x33f7, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {0x33f8, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) {0x33f9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {0x33fa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) {0x33fb, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) {0x33fc, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {0x33fd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) {0x33fe, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) {0x33ff, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {0x360f, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {0x3622, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) {0x3624, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) {0x3625, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {0x3630, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {0x3631, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) {0x3632, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) {0x3633, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) {0x3634, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {0x3635, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {0x3636, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) {0x3638, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {0x363b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {0x363c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) {0x363d, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) {0x366e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) {0x3670, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {0x3671, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) {0x3672, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {0x3673, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {0x3674, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) {0x3675, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {0x3676, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {0x367a, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) {0x367b, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) {0x367c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {0x367d, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {0x3690, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) {0x3691, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {0x3692, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) {0x3699, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {0x369a, 0x96},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {0x369b, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) {0x369c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {0x369d, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) {0x36a2, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {0x36a3, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {0x36cc, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {0x36cd, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {0x36ce, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) {0x36d0, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) {0x36d1, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) {0x36d2, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) {0x36ea, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) {0x36eb, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) {0x36ec, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) {0x36ed, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) {0x36fa, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {0x36fb, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {0x36fc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) {0x36fd, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) {0x3817, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {0x3905, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) {0x3908, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) {0x391b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) {0x391c, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) {0x391d, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {0x3933, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {0x3934, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {0x3935, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) {0x3936, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) {0x393e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {0x3940, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {0x3942, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {0x3943, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {0x3980, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) {0x3981, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) {0x3982, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {0x3983, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) {0x3984, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) {0x3985, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) {0x3986, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {0x3987, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {0x3988, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) {0x3989, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) {0x398a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) {0x398b, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) {0x398c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) {0x398d, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {0x398e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) {0x398f, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) {0x3990, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) {0x3991, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) {0x3992, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {0x3993, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {0x3994, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) {0x3995, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) {0x3996, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {0x3997, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {0x3998, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) {0x3999, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) {0x399a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) {0x399b, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) {0x399c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) {0x399d, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) {0x399e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) {0x399f, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) {0x39a0, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) {0x39a1, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) {0x39a2, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {0x39a3, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) {0x39a4, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) {0x39a5, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {0x39a6, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {0x39a7, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) {0x39a8, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) {0x39a9, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {0x39aa, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {0x39ab, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {0x39ac, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) {0x39ad, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {0x39ae, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) {0x39af, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {0x39b9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) {0x39ba, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {0x39bb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {0x39bc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {0x39bd, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) {0x39be, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {0x39bf, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) {0x39c0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {0x39c5, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {0x3c09, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {0x3c10, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {0x3c11, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {0x3c12, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) {0x3c13, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) {0x3c14, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) {0x3e00, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {0x3e01, 0x5a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) {0x3e02, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) {0x3e03, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {0x3e04, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) {0x3e05, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) {0x3e06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) {0x3e07, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {0x3e08, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {0x3e09, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) {0x3e0e, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {0x3e10, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {0x3e11, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) {0x3e12, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) {0x3e13, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {0x3e23, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) {0x3e24, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) {0x3e26, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {0x4401, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) {0x4407, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {0x4418, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) {0x4501, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) {0x4509, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {0x4603, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {0x4800, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) {0x4816, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) {0x4819, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {0x4829, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {0x4837, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) {0x5000, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {0x550f, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {0x5784, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) {0x5785, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) {0x5787, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) {0x5788, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) {0x5789, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) {0x578a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {0x578b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) {0x578c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) {0x5790, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) {0x5791, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) {0x5792, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) {0x5793, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) {0x5794, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {0x5795, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {0x57c4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) {0x57c5, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) {0x57c7, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) {0x57c8, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) {0x57c9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) {0x57ca, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {0x57cb, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {0x57cc, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) {0x57d0, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) {0x57d1, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) {0x57d2, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {0x57d3, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) {0x57d4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) {0x57d5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) {0x36e9, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) {0x36f9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) //{0x0100, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static const struct sc4210_mode supported_modes_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) .width = 2560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .height = 1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .exp_def = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .hts_def = 0x0546,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .vts_def = 0x05dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .reg_list = sc4210_liner_10_30fps_2560x1440_2lane_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .width = 2560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .height = 1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) .exp_def = 0x015a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .hts_def = 0x0668,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) .vts_def = 0x0b90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .reg_list = sc4210_hdr_10_25fps_2560x1440_2lane_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) static const struct sc4210_mode supported_modes_4lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) .width = 2560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) .height = 1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) .exp_def = 0x0100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) .hts_def = 0x0546,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) .vts_def = 0x05dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) .reg_list = sc4210_linear_10_30fps_2560x1440_4lane_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) .mipi_freq_idx = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) .width = 2560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) .height = 1440,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .exp_def = 0x05a1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .hts_def = 0x0558,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .vts_def = 0x0b90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) .reg_list = sc4210_hdr_10_30fps_2560x1440_4lane_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) .mipi_freq_idx = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static const s64 link_freq_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) SC4210_LINK_FREQ_2LANE_LINEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) SC4210_LINK_FREQ_2LANE_HDR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) SC4210_LINK_FREQ_4LANE_LINEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) SC4210_LINK_FREQ_4LANE_HDR2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) static int sc4210_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) static int sc4210_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) ret = sc4210_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) SC4210_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static int sc4210_read_reg(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) u16 reg, unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) static int sc4210_get_reso_dist(const struct sc4210_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static const struct sc4210_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) sc4210_find_best_fit(struct sc4210 *sc4210, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) for (i = 0; i < sc4210->support_modes_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) dist = sc4210_get_reso_dist(&sc4210->support_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) return &sc4210->support_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) static int sc4210_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) struct sc4210 *sc4210 = to_sc4210(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) const struct sc4210_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) mutex_lock(&sc4210->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) mode = sc4210_find_best_fit(sc4210, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) mutex_unlock(&sc4210->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) sc4210->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) __v4l2_ctrl_modify_range(sc4210->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) __v4l2_ctrl_modify_range(sc4210->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) SC4210_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) __v4l2_ctrl_s_ctrl(sc4210->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) mode->bpp * 2 * sc4210->lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) __v4l2_ctrl_s_ctrl_int64(sc4210->pixel_rate, pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) sc4210->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) mutex_unlock(&sc4210->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) static int sc4210_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) struct sc4210 *sc4210 = to_sc4210(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) const struct sc4210_mode *mode = sc4210->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) mutex_lock(&sc4210->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) mutex_unlock(&sc4210->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) /* format info: width/height/data type/virctual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) mutex_unlock(&sc4210->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) static int sc4210_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) struct sc4210 *sc4210 = to_sc4210(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) code->code = sc4210->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) static int sc4210_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) struct sc4210 *sc4210 = to_sc4210(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (fse->index >= sc4210->support_modes_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (fse->code != sc4210->support_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) fse->min_width = sc4210->support_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) fse->max_width = sc4210->support_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) fse->max_height = sc4210->support_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) fse->min_height = sc4210->support_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static int sc4210_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) struct sc4210 *sc4210 = to_sc4210(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) const struct sc4210_mode *mode = sc4210->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (sc4210->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) fi->interval = sc4210->cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) static int sc4210_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) struct sc4210 *sc4210 = to_sc4210(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) const struct sc4210_mode *mode = sc4210->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) u32 val = 1 << (sc4210->lane_num - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) val |= V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) if (mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) val |= V4L2_MBUS_CSI2_CHANNEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) static void sc4210_get_module_inf(struct sc4210 *sc4210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) strscpy(inf->base.sensor, SC4210_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) strscpy(inf->base.module, sc4210->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) strscpy(inf->base.lens, sc4210->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) static void sc4210_get_gain_reg(u32 total_gain, u32 *again, u32 *again_fine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) u32 *dgain, u32 *dgain_fine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) u32 dgain_total = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) if (total_gain < SC4210_GAIN_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) total_gain = SC4210_GAIN_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) else if (total_gain > SC4210_GAIN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) total_gain = SC4210_GAIN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) dgain_total = total_gain * 1000 / 43656;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) if (total_gain < 2000) { /* 1 - 2x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) *again = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) *again_fine = total_gain*64/1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) *dgain_fine = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) } else if (total_gain < 2750) { /* 2x - 2.75x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) *again = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) *again_fine = total_gain*64/2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) *dgain_fine = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) } else if (total_gain < 2750 * 2) { /* 2.75xx - 5.5x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) *again = 0x23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) *again_fine = total_gain*64/2750;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) *dgain_fine = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) } else if (total_gain < 2750 * 4) { /* 5.5x - 11.0x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) *again = 0x27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) *again_fine = total_gain*64/5500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) *dgain_fine = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) } else if (total_gain < 2750 * 8) { /* 11.0x - 22.0x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) *again = 0x2f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) *again_fine = total_gain*64/11000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) *dgain_fine = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) } else if (total_gain < 2750 * 16) { /* 22.0x - 43.656x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) *again = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) *again_fine = total_gain*64/22000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) *dgain_fine = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) } else if (total_gain < 43656 * 2) { /* 43.656x - 87.312x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) *again = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) *again_fine = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) *dgain_fine = dgain_total*128/1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) } else if (total_gain < 43656 * 4) { /* 87.312x - 174.624x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) *again = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) *again_fine = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) *dgain = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) *dgain_fine = dgain_total*128/2000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) } else if (total_gain < 43656 * 8) { /* 174.624x - 349.248x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) *again = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) *again_fine = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) *dgain = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) *dgain_fine = dgain_total*128/4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) } else if (total_gain < 43656 * 16) { /* 349.248x - 698.496x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) *again = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) *again_fine = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) *dgain = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) *dgain_fine = dgain_total*128/8000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) } else if (total_gain < 43656 * 32) { /* 698.496x - 1375.164x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) *again = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) *again_fine = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) *dgain = 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) *dgain_fine = dgain_total*128/16000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) static int sc4210_set_hdrae(struct sc4210 *sc4210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) u32 l_t_gain, m_t_gain, s_t_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) u32 l_again = 0, l_again_fine = 0, l_dgain = 0, l_dgain_fine = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) u32 s_again = 0, s_again_fine = 0, s_dgain = 0, s_dgain_fine = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) if (!sc4210->has_init_exp && !sc4210->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) sc4210->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) sc4210->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) dev_dbg(&sc4210->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) "sc4210 don't stream, record exp for hdr!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) l_t_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) m_t_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) s_t_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) if (sc4210->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) //2 stagger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) l_t_gain = m_t_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) l_exp_time = m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) l_exp_time = l_exp_time << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) s_exp_time = s_exp_time << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) // set exposure reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) SC4210_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) SC4210_FETCH_EXP_H(l_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) SC4210_REG_EXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) SC4210_FETCH_EXP_M(l_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) SC4210_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) SC4210_FETCH_EXP_L(l_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) //ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) // SC4210_REG_SHORT_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) // SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) // SC4210_FETCH_EXP_H(s_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) SC4210_REG_SHORT_EXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) SC4210_FETCH_EXP_M(s_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) SC4210_REG_SHORT_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) SC4210_FETCH_EXP_L(s_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) // set gain reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) sc4210_get_gain_reg(l_t_gain, &l_again, &l_again_fine, &l_dgain, &l_dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) sc4210_get_gain_reg(s_t_gain, &s_again, &s_again_fine, &s_dgain, &s_dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) SC4210_REG_DIG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) l_dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) SC4210_REG_DIG_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) l_dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) SC4210_REG_ANA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) l_again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) SC4210_REG_ANA_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) l_again_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) SC4210_REG_SDIG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) s_dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) SC4210_REG_SDIG_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) s_dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) SC4210_REG_SANA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) s_again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) SC4210_REG_SANA_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) s_again_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) static int sc4210_get_channel_info(struct sc4210 *sc4210, struct rkmodule_channel_info *ch_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) ch_info->vc = sc4210->cur_mode->vc[ch_info->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) ch_info->width = sc4210->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) ch_info->height = sc4210->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) ch_info->bus_fmt = sc4210->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) static long sc4210_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) struct sc4210 *sc4210 = to_sc4210(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) const struct sc4210_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) u32 i, h = 0, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) int pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) sc4210_get_module_inf(sc4210, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) hdr->hdr_mode = sc4210->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) w = sc4210->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) h = sc4210->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) for (i = 0; i < sc4210->support_modes_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) if (w == sc4210->support_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) h == sc4210->support_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) sc4210->support_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) sc4210->cur_mode = &sc4210->support_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) if (i == sc4210->support_modes_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) dev_err(&sc4210->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) mode = sc4210->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) w = sc4210->cur_mode->hts_def -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) sc4210->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) h = sc4210->cur_mode->vts_def -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) sc4210->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) __v4l2_ctrl_modify_range(sc4210->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) __v4l2_ctrl_modify_range(sc4210->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) SC4210_VTS_MAX -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) sc4210->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) __v4l2_ctrl_s_ctrl(sc4210->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) pixel_rate = (int)link_freq_items[mode->mipi_freq_idx]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) / mode->bpp * 2 * sc4210->lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) __v4l2_ctrl_s_ctrl_int64(sc4210->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) dev_info(&sc4210->client->dev, "sensor mode: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) sc4210->cur_mode->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) if (sc4210->cur_mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) ret = sc4210_set_hdrae(sc4210, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) ret = sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) SC4210_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) SC4210_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) ret = sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) SC4210_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) SC4210_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) ch_info = (struct rkmodule_channel_info *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) ret = sc4210_get_channel_info(sc4210, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) static long sc4210_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) ret = sc4210_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) ret = sc4210_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) if (copy_from_user(hdr, up, sizeof(*hdr))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) ret = sc4210_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) if (copy_from_user(hdrae, up, sizeof(*hdrae))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) ret = sc4210_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) if (copy_from_user(&stream, up, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) ret = sc4210_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) if (!ch_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) ret = sc4210_ioctl(sd, cmd, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) ret = copy_to_user(up, ch_info, sizeof(*ch_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) kfree(ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) static int __sc4210_start_stream(struct sc4210 *sc4210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) ret = sc4210_write_array(sc4210->client, sc4210->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) ret = __v4l2_ctrl_handler_setup(&sc4210->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) if (sc4210->has_init_exp && sc4210->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) ret = sc4210_ioctl(&sc4210->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) &sc4210->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) dev_err(&sc4210->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) return sc4210_write_reg(sc4210->client, SC4210_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) SC4210_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) static int __sc4210_stop_stream(struct sc4210 *sc4210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) sc4210->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) return sc4210_write_reg(sc4210->client, SC4210_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) SC4210_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) static int sc4210_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) struct sc4210 *sc4210 = to_sc4210(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) struct i2c_client *client = sc4210->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) mutex_lock(&sc4210->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) if (on == sc4210->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) ret = __sc4210_start_stream(sc4210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) __sc4210_stop_stream(sc4210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) sc4210->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) mutex_unlock(&sc4210->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) static int sc4210_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) struct sc4210 *sc4210 = to_sc4210(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) struct i2c_client *client = sc4210->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) mutex_lock(&sc4210->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) if (sc4210->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) sc4210->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) sc4210->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) mutex_unlock(&sc4210->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) static int __sc4210_power_on(struct sc4210 *sc4210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) struct device *dev = &sc4210->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) if (!IS_ERR_OR_NULL(sc4210->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) ret = pinctrl_select_state(sc4210->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) sc4210->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) ret = clk_set_rate(sc4210->xvclk, SC4210_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) dev_warn(dev, "Failed to set xvclk rate (27MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) if (clk_get_rate(sc4210->xvclk) != SC4210_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) ret = clk_prepare_enable(sc4210->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) if (!IS_ERR(sc4210->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) gpiod_set_value_cansleep(sc4210->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) ret = regulator_bulk_enable(sc4210_NUM_SUPPLIES, sc4210->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) if (!IS_ERR(sc4210->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) gpiod_set_value_cansleep(sc4210->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) if (!IS_ERR(sc4210->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) gpiod_set_value_cansleep(sc4210->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) usleep_range(4000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) clk_disable_unprepare(sc4210->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) static void __sc4210_power_off(struct sc4210 *sc4210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) struct device *dev = &sc4210->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) if (!IS_ERR(sc4210->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) gpiod_set_value_cansleep(sc4210->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) clk_disable_unprepare(sc4210->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) if (!IS_ERR(sc4210->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) gpiod_set_value_cansleep(sc4210->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) if (!IS_ERR_OR_NULL(sc4210->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) ret = pinctrl_select_state(sc4210->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) sc4210->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) regulator_bulk_disable(sc4210_NUM_SUPPLIES, sc4210->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) static int sc4210_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) struct sc4210 *sc4210 = to_sc4210(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) return __sc4210_power_on(sc4210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) static int sc4210_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) struct sc4210 *sc4210 = to_sc4210(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) __sc4210_power_off(sc4210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) static int sc4210_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) struct sc4210 *sc4210 = to_sc4210(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) const struct sc4210_mode *def_mode = &sc4210->support_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) mutex_lock(&sc4210->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) mutex_unlock(&sc4210->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) static int sc4210_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) struct sc4210 *sc4210 = to_sc4210(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) if (fie->index >= sc4210->support_modes_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) fie->code = sc4210->support_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) fie->width = sc4210->support_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) fie->height = sc4210->support_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) fie->interval = sc4210->support_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) fie->reserved[0] = sc4210->support_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) static const struct dev_pm_ops sc4210_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) SET_RUNTIME_PM_OPS(sc4210_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) sc4210_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) static const struct v4l2_subdev_internal_ops sc4210_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .open = sc4210_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) static const struct v4l2_subdev_core_ops sc4210_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .s_power = sc4210_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .ioctl = sc4210_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .compat_ioctl32 = sc4210_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) static const struct v4l2_subdev_video_ops sc4210_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .s_stream = sc4210_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .g_frame_interval = sc4210_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) static const struct v4l2_subdev_pad_ops sc4210_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .enum_mbus_code = sc4210_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .enum_frame_size = sc4210_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .enum_frame_interval = sc4210_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) .get_fmt = sc4210_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .set_fmt = sc4210_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .get_mbus_config = sc4210_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) static const struct v4l2_subdev_ops sc4210_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .core = &sc4210_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .video = &sc4210_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .pad = &sc4210_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) static void sc4210_modify_fps_info(struct sc4210 *sc4210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) const struct sc4210_mode *mode = sc4210->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) sc4210->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) sc4210->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) static int sc4210_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) struct sc4210 *sc4210 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) struct sc4210, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) struct i2c_client *client = sc4210->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) u32 again = 0, again_fine = 0, dgain = 0, dgain_fine = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) u32 val = 0, vts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) max = sc4210->cur_mode->height + ctrl->val - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) __v4l2_ctrl_modify_range(sc4210->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) sc4210->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) sc4210->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) sc4210->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) if (sc4210->cur_mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) val = ctrl->val << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) ret = sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) SC4210_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) SC4210_FETCH_EXP_H(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) SC4210_REG_EXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) SC4210_FETCH_EXP_M(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) SC4210_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) SC4210_FETCH_EXP_L(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) dev_dbg(&client->dev, "set exposure 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) if (sc4210->cur_mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) sc4210_get_gain_reg(ctrl->val, &again, &again_fine, &dgain, &dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) ret = sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) SC4210_REG_DIG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) SC4210_REG_DIG_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) SC4210_REG_ANA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) SC4210_REG_ANA_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) again_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) dev_dbg(&client->dev, "set gain 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) vts = ctrl->val + sc4210->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) ret = sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) SC4210_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) (vts >> 8) & 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) SC4210_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) vts & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) sc4210->cur_vts = ctrl->val + sc4210->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) if (sc4210->cur_vts != sc4210->cur_mode->vts_def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) sc4210_modify_fps_info(sc4210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) ret = sc4210_read_reg(sc4210->client, SC4210_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) SC4210_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) val |= SC4210_MIRROR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) val &= ~SC4210_MIRROR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) SC4210_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) SC4210_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) ret = sc4210_read_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) SC4210_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) SC4210_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) val |= SC4210_FLIP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) val &= ~SC4210_FLIP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) ret |= sc4210_write_reg(sc4210->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) SC4210_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) SC4210_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) static const struct v4l2_ctrl_ops sc4210_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .s_ctrl = sc4210_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) static int sc4210_parse_of(struct sc4210 *sc4210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) struct device *dev = &sc4210->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) dev_err(dev, "Failed to get endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) fwnode = of_fwnode_handle(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) if (rval <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) dev_err(dev, " Get mipi lane num failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) sc4210->lane_num = rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) dev_info(dev, "lane_num = %d\n", sc4210->lane_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) if (sc4210->lane_num == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) sc4210->support_modes = supported_modes_2lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) sc4210->support_modes_num = ARRAY_SIZE(supported_modes_2lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) } else if (sc4210->lane_num == 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) sc4210->support_modes = supported_modes_4lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) sc4210->support_modes_num = ARRAY_SIZE(supported_modes_4lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) sc4210->cur_mode = &sc4210->support_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) static int sc4210_initialize_controls(struct sc4210 *sc4210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) const struct sc4210_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) handler = &sc4210->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) mode = sc4210->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) handler->lock = &sc4210->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) sc4210->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) ARRAY_SIZE(link_freq_items) - 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) link_freq_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) __v4l2_ctrl_s_ctrl(sc4210->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) if (mode->mipi_freq_idx == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) dst_pixel_rate = SC4210_PIXEL_RATES_2LANE_LINEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) else if (mode->mipi_freq_idx == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) dst_pixel_rate = SC4210_PIXEL_RATES_2LANE_HDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) else if (mode->mipi_freq_idx == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) dst_pixel_rate = SC4210_PIXEL_RATES_4LANE_LINEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) else if (mode->mipi_freq_idx == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) dst_pixel_rate = SC4210_PIXEL_RATES_4LANE_HDR2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) sc4210->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) V4L2_CID_PIXEL_RATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) SC4210_MAX_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) 1, dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) sc4210->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) if (sc4210->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) sc4210->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) sc4210->vblank = v4l2_ctrl_new_std(handler, &sc4210_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) SC4210_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) sc4210->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) exposure_max = (mode->vts_def << 1) - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) sc4210->exposure = v4l2_ctrl_new_std(handler, &sc4210_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) V4L2_CID_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) SC4210_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) exposure_max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) SC4210_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) sc4210->anal_gain = v4l2_ctrl_new_std(handler, &sc4210_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) V4L2_CID_ANALOGUE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) SC4210_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) SC4210_GAIN_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) SC4210_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) SC4210_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) v4l2_ctrl_new_std(handler, &sc4210_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) v4l2_ctrl_new_std(handler, &sc4210_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) dev_err(&sc4210->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) sc4210->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) sc4210->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) static int sc4210_check_sensor_id(struct sc4210 *sc4210,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) struct device *dev = &sc4210->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) ret = sc4210_read_reg(client, SC4210_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) SC4210_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) if (id != SC4210_CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) dev_info(dev, "Detected SC%06x sensor\n", SC4210_CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) static int sc4210_configure_regulators(struct sc4210 *sc4210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) for (i = 0; i < sc4210_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) sc4210->supplies[i].supply = sc4210_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) return devm_regulator_bulk_get(&sc4210->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) sc4210_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) sc4210->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) static int sc4210_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) struct sc4210 *sc4210;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) u32 hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) sc4210 = devm_kzalloc(dev, sizeof(*sc4210), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) if (!sc4210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) &sc4210->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) &sc4210->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) &sc4210->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) &sc4210->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) sc4210->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) ret = sc4210_parse_of(sc4210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) sc4210->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) if (IS_ERR(sc4210->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) sc4210->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) if (IS_ERR(sc4210->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) sc4210->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) if (IS_ERR(sc4210->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) sc4210->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) if (!IS_ERR(sc4210->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) sc4210->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) pinctrl_lookup_state(sc4210->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) if (IS_ERR(sc4210->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) sc4210->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) pinctrl_lookup_state(sc4210->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) if (IS_ERR(sc4210->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) ret = sc4210_configure_regulators(sc4210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) mutex_init(&sc4210->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) sd = &sc4210->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) v4l2_i2c_subdev_init(sd, client, &sc4210_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) ret = sc4210_initialize_controls(sc4210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) ret = __sc4210_power_on(sc4210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) ret = sc4210_check_sensor_id(sc4210, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) sd->internal_ops = &sc4210_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) sc4210->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) ret = media_entity_pads_init(&sd->entity, 1, &sc4210->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) if (strcmp(sc4210->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) sc4210->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) SC4210_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) dev_err(&sc4210->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) __sc4210_power_off(sc4210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) v4l2_ctrl_handler_free(&sc4210->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) mutex_destroy(&sc4210->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) static int sc4210_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) struct sc4210 *sc4210 = to_sc4210(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) v4l2_ctrl_handler_free(&sc4210->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) mutex_destroy(&sc4210->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) __sc4210_power_off(sc4210);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) static const struct of_device_id sc4210_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) { .compatible = "smartsens,sc4210" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) MODULE_DEVICE_TABLE(of, sc4210_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) static const struct i2c_device_id sc4210_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) { "smartsens,sc4210", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) static struct i2c_driver sc4210_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) .name = SC4210_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) .pm = &sc4210_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) .of_match_table = of_match_ptr(sc4210_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) .probe = &sc4210_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) .remove = &sc4210_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) .id_table = sc4210_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) return i2c_add_driver(&sc4210_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) i2c_del_driver(&sc4210_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) MODULE_DESCRIPTION("smartsens sc4210 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags