^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sc3338 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 first version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) //#define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "../platform/rockchip/isp/rkisp_tb_helper.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SC3338_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SC3338_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SC3338_LINK_FREQ_253 253125000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PIXEL_RATE_WITH_253M_10BIT (SC3338_LINK_FREQ_253 * 2 * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SC3338_LANES / SC3338_BITS_PER_SAMPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SC3338_XVCLK_FREQ 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CHIP_ID 0xcc41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SC3338_REG_CHIP_ID 0x3107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SC3338_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SC3338_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SC3338_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC3338_REG_EXPOSURE_H 0x3e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SC3338_REG_EXPOSURE_M 0x3e01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SC3338_REG_EXPOSURE_L 0x3e02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SC3338_EXPOSURE_MIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SC3338_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SC3338_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SC3338_REG_DIG_GAIN 0x3e06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SC3338_REG_DIG_FINE_GAIN 0x3e07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SC3338_REG_ANA_GAIN 0x3e09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SC3338_GAIN_MIN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SC3338_GAIN_MAX (99614) //48.64*16*128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SC3338_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SC3338_GAIN_DEFAULT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SC3338_REG_GROUP_HOLD 0x3812
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SC3338_GROUP_HOLD_START 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SC3338_GROUP_HOLD_END 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SC3338_REG_TEST_PATTERN 0x4501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SC3338_TEST_PATTERN_BIT_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SC3338_REG_VTS_H 0x320e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SC3338_REG_VTS_L 0x320f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SC3338_FLIP_MIRROR_REG 0x3221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SC3338_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SC3338_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SC3338_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SC3338_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SC3338_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SC3338_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SC3338_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define REG_DELAY 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SC3338_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SC3338_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SC3338_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SC3338_NAME "sc3338"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const char * const sc3338_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SC3338_NUM_SUPPLIES ARRAY_SIZE(sc3338_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct sc3338_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct sc3338 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct regulator_bulk_data supplies[SC3338_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct v4l2_fract cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const struct sc3338_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) bool is_thunderboot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) bool is_first_streamoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define to_sc3338(sd) container_of(sd, struct sc3338, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Xclk 27Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static const struct regval sc3338_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Xclk 27Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * max_framerate 25fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * mipi_datarate per lane 506.25Mbps, 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static const struct regval sc3338_linear_10_2304x1296_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x37f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x301f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x30b8, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x320e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x320f, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x3253, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x325f, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x3301, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x3306, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3309, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x330b, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x3314, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x331f, 0x99},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3333, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x335e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x335f, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3364, 0x5e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x337c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x337d, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3390, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3391, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3392, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3393, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3394, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3395, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3396, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3397, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3398, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3399, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x339a, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x339b, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x339c, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x33a2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x33ac, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x33ad, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x33ae, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x33af, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x33b1, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x33b3, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x33f9, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x33fb, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x33fc, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x33fd, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x349f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x34a6, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x34a7, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x34a8, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x34a9, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x34ab, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x34ac, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x34ad, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x34f8, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x34f9, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3630, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3631, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3632, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3633, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x363b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x363c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3641, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3670, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3674, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3675, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3676, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x3677, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x3678, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x3679, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x367c, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x367d, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x367e, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x367f, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3690, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3691, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3692, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x369c, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x369d, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x36b0, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x36b1, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x36b2, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x36b3, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x36b4, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x36b5, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x36b6, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x370f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3722, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3724, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3725, 0xc1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x3771, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3772, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3773, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x377a, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x377b, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3904, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3905, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x391d, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x3921, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3926, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3933, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x3934, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3935, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3936, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3937, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x3938, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x39dc, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x3e01, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x3e02, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x3e09, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x440e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x4509, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x5ae0, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x5ae1, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x5ae2, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x5ae3, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x5ae4, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x5ae5, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x5ae6, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x5ae7, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x5ae8, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x5ae9, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x5aea, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x5aeb, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x5aec, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x5aed, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x36e9, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x37f9, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) static const struct sc3338_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) .width = 2304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) .height = 1296,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .exp_def = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .hts_def = 0x05dc * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .vts_def = 0x0654,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .reg_list = sc3338_linear_10_2304x1296_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) SC3338_LINK_FREQ_253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static const char * const sc3338_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static int sc3338_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int sc3338_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) ret = sc3338_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) SC3338_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int sc3338_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) static int sc3338_set_gain_reg(struct sc3338 *sc3338, u32 gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct i2c_client *client = sc3338->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 coarse_again = 0, coarse_dgain = 0, fine_dgain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int ret = 0, gain_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) if (gain < 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) gain = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) else if (gain > SC3338_GAIN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) gain = SC3338_GAIN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) gain_factor = gain * 1000 / 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (gain_factor < 1520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) coarse_again = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) coarse_dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) fine_dgain = gain_factor * 128 / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) } else if (gain_factor < 3040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) coarse_again = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) coarse_dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) fine_dgain = gain_factor * 128 / 1520;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) } else if (gain_factor < 6080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) coarse_again = 0x48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) coarse_dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) fine_dgain = gain_factor * 128 / 3040;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) } else if (gain_factor < 12160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) coarse_again = 0x49;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) coarse_dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) fine_dgain = gain_factor * 128 / 6080;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) } else if (gain_factor < 24320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) coarse_again = 0x4b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) coarse_dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) fine_dgain = gain_factor * 128 / 12160;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) } else if (gain_factor < 48640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) coarse_again = 0x4f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) coarse_dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) fine_dgain = gain_factor * 128 / 24320;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) } else if (gain_factor < 48640 * 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) //open dgain begin max digital gain 4X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) coarse_again = 0x5f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) coarse_dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) fine_dgain = gain_factor * 128 / 48640;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) } else if (gain_factor < 48640 * 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) coarse_again = 0x5f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) coarse_dgain = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) fine_dgain = gain_factor * 128 / 48640 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) } else if (gain_factor < 48640 * 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) coarse_again = 0x5f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) coarse_dgain = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) fine_dgain = gain_factor * 128 / 48640 / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) } else if (gain_factor < 48640 * 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) coarse_again = 0x5f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) coarse_dgain = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) fine_dgain = gain_factor * 128 / 48640 / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_dbg(&client->dev, "c_again: 0x%x, c_dgain: 0x%x, f_dgain: 0x%0x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) coarse_again, coarse_dgain, fine_dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) ret = sc3338_write_reg(sc3338->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) SC3338_REG_DIG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) SC3338_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) coarse_dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ret |= sc3338_write_reg(sc3338->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) SC3338_REG_DIG_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) SC3338_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) fine_dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret |= sc3338_write_reg(sc3338->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) SC3338_REG_ANA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) SC3338_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) coarse_again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int sc3338_get_reso_dist(const struct sc3338_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) static const struct sc3338_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) sc3338_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dist = sc3338_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) static int sc3338_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct sc3338 *sc3338 = to_sc3338(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) const struct sc3338_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mutex_lock(&sc3338->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) mode = sc3338_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) mutex_unlock(&sc3338->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) sc3338->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) __v4l2_ctrl_modify_range(sc3338->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) __v4l2_ctrl_modify_range(sc3338->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) SC3338_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) sc3338->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) mutex_unlock(&sc3338->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int sc3338_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct sc3338 *sc3338 = to_sc3338(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) const struct sc3338_mode *mode = sc3338->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) mutex_lock(&sc3338->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mutex_unlock(&sc3338->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* format info: width/height/data type/virctual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) mutex_unlock(&sc3338->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int sc3338_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct sc3338 *sc3338 = to_sc3338(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) code->code = sc3338->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static int sc3338_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (fse->code != supported_modes[0].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int sc3338_enable_test_pattern(struct sc3338 *sc3338, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ret = sc3338_read_reg(sc3338->client, SC3338_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) SC3338_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) val |= SC3338_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) val &= ~SC3338_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ret |= sc3338_write_reg(sc3338->client, SC3338_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) SC3338_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static int sc3338_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct sc3338 *sc3338 = to_sc3338(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) const struct sc3338_mode *mode = sc3338->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (sc3338->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) fi->interval = sc3338->cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int sc3338_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct sc3338 *sc3338 = to_sc3338(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) const struct sc3338_mode *mode = sc3338->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u32 val = 1 << (SC3338_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) val |= V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) val |= V4L2_MBUS_CSI2_CHANNEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static void sc3338_get_module_inf(struct sc3338 *sc3338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) strscpy(inf->base.sensor, SC3338_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) strscpy(inf->base.module, sc3338->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) strscpy(inf->base.lens, sc3338->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static long sc3338_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct sc3338 *sc3338 = to_sc3338(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) sc3338_get_module_inf(sc3338, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) hdr->hdr_mode = sc3338->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) w = sc3338->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) h = sc3338->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) sc3338->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (i == ARRAY_SIZE(supported_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) dev_err(&sc3338->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) w = sc3338->cur_mode->hts_def - sc3338->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) h = sc3338->cur_mode->vts_def - sc3338->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) __v4l2_ctrl_modify_range(sc3338->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) __v4l2_ctrl_modify_range(sc3338->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) SC3338_VTS_MAX - sc3338->cur_mode->height, 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) sc3338->cur_fps = sc3338->cur_mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ret = sc3338_write_reg(sc3338->client, SC3338_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) SC3338_REG_VALUE_08BIT, SC3338_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ret = sc3338_write_reg(sc3338->client, SC3338_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) SC3338_REG_VALUE_08BIT, SC3338_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static long sc3338_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ret = sc3338_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (copy_to_user(up, inf, sizeof(*inf)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) ret = sc3338_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (copy_to_user(up, hdr, sizeof(*hdr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ret = sc3338_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = sc3338_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ret = sc3338_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static int __sc3338_start_stream(struct sc3338 *sc3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (!sc3338->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) ret = sc3338_write_array(sc3338->client, sc3338->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ret = __v4l2_ctrl_handler_setup(&sc3338->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (sc3338->has_init_exp && sc3338->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ret = sc3338_ioctl(&sc3338->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) &sc3338->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) dev_err(&sc3338->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return sc3338_write_reg(sc3338->client, SC3338_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) SC3338_REG_VALUE_08BIT, SC3338_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static int __sc3338_stop_stream(struct sc3338 *sc3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) sc3338->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (sc3338->is_thunderboot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) sc3338->is_first_streamoff = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return sc3338_write_reg(sc3338->client, SC3338_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) SC3338_REG_VALUE_08BIT, SC3338_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static int __sc3338_power_on(struct sc3338 *sc3338);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static int sc3338_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct sc3338 *sc3338 = to_sc3338(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct i2c_client *client = sc3338->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) mutex_lock(&sc3338->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (on == sc3338->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (sc3338->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) sc3338->is_thunderboot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) __sc3338_power_on(sc3338);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ret = __sc3338_start_stream(sc3338);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) __sc3338_stop_stream(sc3338);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) sc3338->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) mutex_unlock(&sc3338->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static int sc3338_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) struct sc3338 *sc3338 = to_sc3338(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct i2c_client *client = sc3338->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) mutex_lock(&sc3338->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (sc3338->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (!sc3338->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ret = sc3338_write_array(sc3338->client, sc3338_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) sc3338->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) sc3338->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) mutex_unlock(&sc3338->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static inline u32 sc3338_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return DIV_ROUND_UP(cycles, SC3338_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) static int __sc3338_power_on(struct sc3338 *sc3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct device *dev = &sc3338->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (!IS_ERR_OR_NULL(sc3338->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) ret = pinctrl_select_state(sc3338->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) sc3338->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ret = clk_set_rate(sc3338->xvclk, SC3338_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) if (clk_get_rate(sc3338->xvclk) != SC3338_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ret = clk_prepare_enable(sc3338->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (sc3338->is_thunderboot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (!IS_ERR(sc3338->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) gpiod_set_value_cansleep(sc3338->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ret = regulator_bulk_enable(SC3338_NUM_SUPPLIES, sc3338->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (!IS_ERR(sc3338->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) gpiod_set_value_cansleep(sc3338->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (!IS_ERR(sc3338->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) gpiod_set_value_cansleep(sc3338->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (!IS_ERR(sc3338->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) usleep_range(6000, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) usleep_range(12000, 16000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) delay_us = sc3338_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) clk_disable_unprepare(sc3338->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static void __sc3338_power_off(struct sc3338 *sc3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct device *dev = &sc3338->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) clk_disable_unprepare(sc3338->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (sc3338->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (sc3338->is_first_streamoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) sc3338->is_thunderboot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) sc3338->is_first_streamoff = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (!IS_ERR(sc3338->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) gpiod_set_value_cansleep(sc3338->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) clk_disable_unprepare(sc3338->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (!IS_ERR(sc3338->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) gpiod_set_value_cansleep(sc3338->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (!IS_ERR_OR_NULL(sc3338->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ret = pinctrl_select_state(sc3338->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) sc3338->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) regulator_bulk_disable(SC3338_NUM_SUPPLIES, sc3338->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) static int sc3338_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) struct sc3338 *sc3338 = to_sc3338(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return __sc3338_power_on(sc3338);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static int sc3338_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct sc3338 *sc3338 = to_sc3338(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) __sc3338_power_off(sc3338);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static int sc3338_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct sc3338 *sc3338 = to_sc3338(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) const struct sc3338_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) mutex_lock(&sc3338->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) mutex_unlock(&sc3338->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static int sc3338_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static const struct dev_pm_ops sc3338_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) SET_RUNTIME_PM_OPS(sc3338_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) sc3338_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static const struct v4l2_subdev_internal_ops sc3338_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) .open = sc3338_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static const struct v4l2_subdev_core_ops sc3338_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .s_power = sc3338_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .ioctl = sc3338_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .compat_ioctl32 = sc3338_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static const struct v4l2_subdev_video_ops sc3338_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) .s_stream = sc3338_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) .g_frame_interval = sc3338_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static const struct v4l2_subdev_pad_ops sc3338_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) .enum_mbus_code = sc3338_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) .enum_frame_size = sc3338_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .enum_frame_interval = sc3338_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .get_fmt = sc3338_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) .set_fmt = sc3338_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .get_mbus_config = sc3338_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static const struct v4l2_subdev_ops sc3338_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .core = &sc3338_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .video = &sc3338_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .pad = &sc3338_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static void sc3338_modify_fps_info(struct sc3338 *sc3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) const struct sc3338_mode *mode = sc3338->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) sc3338->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) sc3338->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static int sc3338_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct sc3338 *sc3338 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct sc3338, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct i2c_client *client = sc3338->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) max = sc3338->cur_mode->height + ctrl->val - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) __v4l2_ctrl_modify_range(sc3338->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) sc3338->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) sc3338->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) sc3338->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (sc3338->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) val = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) ret = sc3338_write_reg(sc3338->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) SC3338_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) SC3338_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) SC3338_FETCH_EXP_H(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ret |= sc3338_write_reg(sc3338->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) SC3338_REG_EXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) SC3338_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) SC3338_FETCH_EXP_M(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ret |= sc3338_write_reg(sc3338->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) SC3338_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) SC3338_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) SC3338_FETCH_EXP_L(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) dev_dbg(&client->dev, "set gain 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (sc3338->cur_mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) ret = sc3338_set_gain_reg(sc3338, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ret = sc3338_write_reg(sc3338->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) SC3338_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) SC3338_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) (ctrl->val + sc3338->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) ret |= sc3338_write_reg(sc3338->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) SC3338_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) SC3338_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) (ctrl->val + sc3338->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) sc3338->cur_vts = ctrl->val + sc3338->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (sc3338->cur_vts != sc3338->cur_mode->vts_def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) sc3338_modify_fps_info(sc3338);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) ret = sc3338_enable_test_pattern(sc3338, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ret = sc3338_read_reg(sc3338->client, SC3338_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) SC3338_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) ret |= sc3338_write_reg(sc3338->client, SC3338_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) SC3338_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) SC3338_FETCH_MIRROR(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) ret = sc3338_read_reg(sc3338->client, SC3338_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) SC3338_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) ret |= sc3338_write_reg(sc3338->client, SC3338_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) SC3338_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) SC3338_FETCH_FLIP(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) static const struct v4l2_ctrl_ops sc3338_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .s_ctrl = sc3338_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static int sc3338_initialize_controls(struct sc3338 *sc3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) const struct sc3338_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) handler = &sc3338->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) mode = sc3338->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) handler->lock = &sc3338->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) 0, PIXEL_RATE_WITH_253M_10BIT, 1, PIXEL_RATE_WITH_253M_10BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) sc3338->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (sc3338->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) sc3338->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) sc3338->vblank = v4l2_ctrl_new_std(handler, &sc3338_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) SC3338_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) exposure_max = mode->vts_def - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) sc3338->exposure = v4l2_ctrl_new_std(handler, &sc3338_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) V4L2_CID_EXPOSURE, SC3338_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) exposure_max, SC3338_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) sc3338->anal_gain = v4l2_ctrl_new_std(handler, &sc3338_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) V4L2_CID_ANALOGUE_GAIN, SC3338_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) SC3338_GAIN_MAX, SC3338_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) SC3338_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) sc3338->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) &sc3338_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ARRAY_SIZE(sc3338_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) 0, 0, sc3338_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) v4l2_ctrl_new_std(handler, &sc3338_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) v4l2_ctrl_new_std(handler, &sc3338_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) dev_err(&sc3338->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) sc3338->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) sc3338->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) sc3338->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) static int sc3338_check_sensor_id(struct sc3338 *sc3338,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct device *dev = &sc3338->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (sc3338->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) ret = sc3338_read_reg(client, SC3338_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) SC3338_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static int sc3338_configure_regulators(struct sc3338 *sc3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) for (i = 0; i < SC3338_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) sc3338->supplies[i].supply = sc3338_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) return devm_regulator_bulk_get(&sc3338->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) SC3338_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) sc3338->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) static int sc3338_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) struct sc3338 *sc3338;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) int i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) sc3338 = devm_kzalloc(dev, sizeof(*sc3338), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (!sc3338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) &sc3338->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) &sc3338->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) &sc3338->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) &sc3338->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) sc3338->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) sc3338->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) sc3338->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (i == ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) sc3338->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) sc3338->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (IS_ERR(sc3338->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) sc3338->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (IS_ERR(sc3338->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) sc3338->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (IS_ERR(sc3338->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) sc3338->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (!IS_ERR(sc3338->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) sc3338->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) pinctrl_lookup_state(sc3338->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (IS_ERR(sc3338->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) sc3338->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) pinctrl_lookup_state(sc3338->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (IS_ERR(sc3338->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) ret = sc3338_configure_regulators(sc3338);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) mutex_init(&sc3338->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) sd = &sc3338->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) v4l2_i2c_subdev_init(sd, client, &sc3338_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) ret = sc3338_initialize_controls(sc3338);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) ret = __sc3338_power_on(sc3338);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) ret = sc3338_check_sensor_id(sc3338, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) sd->internal_ops = &sc3338_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) sc3338->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) ret = media_entity_pads_init(&sd->entity, 1, &sc3338->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (strcmp(sc3338->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) sc3338->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) SC3338_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) __sc3338_power_off(sc3338);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) v4l2_ctrl_handler_free(&sc3338->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) mutex_destroy(&sc3338->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static int sc3338_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) struct sc3338 *sc3338 = to_sc3338(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) v4l2_ctrl_handler_free(&sc3338->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) mutex_destroy(&sc3338->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) __sc3338_power_off(sc3338);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) static const struct of_device_id sc3338_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) { .compatible = "smartsens,sc3338" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) MODULE_DEVICE_TABLE(of, sc3338_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static const struct i2c_device_id sc3338_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) { "smartsens,sc3338", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) static struct i2c_driver sc3338_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .name = SC3338_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .pm = &sc3338_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) .of_match_table = of_match_ptr(sc3338_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .probe = &sc3338_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .remove = &sc3338_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .id_table = sc3338_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return i2c_add_driver(&sc3338_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) i2c_del_driver(&sc3338_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) subsys_initcall(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) MODULE_DESCRIPTION("smartsens sc3338 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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