^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sc3336 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 first version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) //#define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "../platform/rockchip/isp/rkisp_tb_helper.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SC3336_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SC3336_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SC3336_LINK_FREQ_253 253125000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SC3336_LINK_FREQ_255 255000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PIXEL_RATE_WITH_253M_10BIT (SC3336_LINK_FREQ_253 * 2 * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) SC3336_LANES / SC3336_BITS_PER_SAMPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PIXEL_RATE_WITH_255M_10BIT (SC3336_LINK_FREQ_255 * 2 * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SC3336_LANES / SC3336_BITS_PER_SAMPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SC3336_XVCLK_FREQ 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CHIP_ID 0xcc41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SC3336_REG_CHIP_ID 0x3107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC3336_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SC3336_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SC3336_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SC3336_REG_EXPOSURE_H 0x3e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SC3336_REG_EXPOSURE_M 0x3e01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SC3336_REG_EXPOSURE_L 0x3e02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SC3336_EXPOSURE_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SC3336_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SC3336_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SC3336_REG_DIG_GAIN 0x3e06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SC3336_REG_DIG_FINE_GAIN 0x3e07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SC3336_REG_ANA_GAIN 0x3e09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SC3336_GAIN_MIN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC3336_GAIN_MAX (99614) //48.64*16*128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SC3336_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SC3336_GAIN_DEFAULT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SC3336_REG_GROUP_HOLD 0x3812
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SC3336_GROUP_HOLD_START 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SC3336_GROUP_HOLD_END 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SC3336_REG_TEST_PATTERN 0x4501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SC3336_TEST_PATTERN_BIT_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SC3336_REG_VTS_H 0x320e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SC3336_REG_VTS_L 0x320f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SC3336_FLIP_MIRROR_REG 0x3221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SC3336_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SC3336_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SC3336_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SC3336_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SC3336_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SC3336_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SC3336_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define REG_DELAY 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SC3336_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SC3336_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SC3336_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SC3336_NAME "sc3336"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const char * const sc3336_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SC3336_NUM_SUPPLIES ARRAY_SIZE(sc3336_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct sc3336_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 xvclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 link_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct sc3336 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct regulator_bulk_data supplies[SC3336_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct v4l2_fract cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) const struct sc3336_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) bool is_thunderboot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) bool is_first_streamoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define to_sc3336(sd) container_of(sd, struct sc3336, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static const struct regval sc3336_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * Xclk 27Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * max_framerate 25fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * mipi_datarate per lane 506.25Mbps, 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) static const struct regval sc3336_linear_10_2304x1296_25fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x37f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x301f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x30b8, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x320e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x320f, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3253, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x325f, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3301, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3306, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3309, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x330b, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3314, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x331f, 0x99},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3333, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x335e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x335f, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3364, 0x5e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x337c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x337d, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3390, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3391, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x3392, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3393, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3394, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3395, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3396, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3397, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3398, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3399, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x339a, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x339b, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x339c, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x33a2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x33ac, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x33ad, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x33ae, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x33af, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x33b1, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x33b3, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x33f9, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x33fb, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x33fc, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x33fd, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x349f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x34a6, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x34a7, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x34a8, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x34a9, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x34ab, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x34ac, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x34ad, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x34f8, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x34f9, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3630, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3631, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3632, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x3633, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x363b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x363c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x3641, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3670, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3674, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3675, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3676, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3677, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3678, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3679, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x367c, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x367d, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x367e, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x367f, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3690, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3691, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3692, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x369c, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x369d, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x36b0, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x36b1, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x36b2, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x36b3, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x36b4, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x36b5, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x36b6, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x370f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3722, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3724, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x3725, 0xc1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x3771, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3772, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3773, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x377a, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x377b, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3904, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3905, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x391d, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x3921, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x3926, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x3933, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x3934, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x3935, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x3936, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x3937, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x3938, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x39dc, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x3e01, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x3e02, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x3e09, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x440e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x4509, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x5ae0, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x5ae1, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x5ae2, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x5ae3, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x5ae4, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x5ae5, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x5ae6, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x5ae7, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x5ae8, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x5ae9, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x5aea, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x5aeb, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x5aec, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x5aed, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x36e9, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x37f9, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * mipi_datarate per lane 510Mbps, 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static const struct regval sc3336_linear_10_2304x1296_30fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x37f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x301f, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x30b8, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x320e, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x320f, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x3253, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x325f, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x3301, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x3306, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x330b, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x3314, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x3333, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x3334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x335e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x335f, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x3364, 0x5e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x337c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x337d, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x3390, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x3391, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x3392, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x3393, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x3394, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x3395, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x3396, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x3397, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x3398, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x3399, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x339a, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x339b, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x339c, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x33a2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x33ac, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x33ad, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x33ae, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x33af, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x33b1, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x33b3, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x33f9, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x33fb, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x33fc, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x33fd, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x349f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x34a6, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x34a7, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x34a8, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x34a9, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x34ab, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x34ac, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x34ad, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x34f8, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x34f9, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x3630, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x3631, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x3632, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x3633, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x363b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x363c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x3641, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x3670, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x3674, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x3675, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x3676, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x3677, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x3678, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x3679, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x367c, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x367d, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x367e, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x367f, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x3690, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x3691, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x3692, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x369c, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x369d, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x36b0, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x36b1, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x36b2, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x36b3, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x36b4, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x36b5, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x36b6, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x36ea, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x36eb, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x36ec, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x36ed, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x370f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x3722, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x3724, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x3725, 0xc1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x3771, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x3772, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x3773, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x377a, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x377b, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x37fa, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x37fb, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x37fc, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x37fd, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x3904, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x3905, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x391d, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x3921, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x3926, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x3933, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x3934, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x3935, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x3936, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x3937, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x3938, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x39dc, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x3e01, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3e02, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x3e09, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x440e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x4509, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x5ae0, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x5ae1, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x5ae2, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x5ae3, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x5ae4, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x5ae5, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x5ae6, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x5ae7, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x5ae8, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x5ae9, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x5aea, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x5aeb, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x5aec, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x5aed, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x36e9, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x37f9, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const struct sc3336_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .width = 2304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .height = 1296,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .exp_def = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .hts_def = 0x05dc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .vts_def = 0x0654,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .reg_list = sc3336_linear_10_2304x1296_25fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .xvclk_freq = 27000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .link_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .width = 2304,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .height = 1296,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .exp_def = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .hts_def = 0x0578 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .vts_def = 0x0550,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .reg_list = sc3336_linear_10_2304x1296_30fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .xvclk_freq = 24000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .link_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) SC3336_LINK_FREQ_253,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) SC3336_LINK_FREQ_255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const char * const sc3336_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) "Vertical Color Bar Type 4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static int sc3336_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int sc3336_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ret = sc3336_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) SC3336_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static int sc3336_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int sc3336_set_gain_reg(struct sc3336 *sc3336, u32 gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct i2c_client *client = sc3336->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u32 coarse_again = 0, coarse_dgain = 0, fine_dgain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) if (gain < 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) gain = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) else if (gain > SC3336_GAIN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) gain = SC3336_GAIN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (gain < 1520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) coarse_again = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) coarse_dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) fine_dgain = gain * 128 / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) } else if (gain < 3040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) coarse_again = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) coarse_dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) fine_dgain = gain * 128 / 1520;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) } else if (gain < 6080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) coarse_again = 0x48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) coarse_dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) fine_dgain = gain * 128 / 3040;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) } else if (gain < 12160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) coarse_again = 0x49;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) coarse_dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) fine_dgain = gain * 128 / 6080;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) } else if (gain < 24320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) coarse_again = 0x4b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) coarse_dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) fine_dgain = gain * 128 / 12160;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) } else if (gain < 48640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) coarse_again = 0x4f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) coarse_dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) fine_dgain = gain * 128 / 24320;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) } else if (gain < 48640 * 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) //open dgain begin max digital gain 4X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) coarse_again = 0x5f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) coarse_dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) fine_dgain = gain * 128 / 48640;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) } else if (gain < 48640 * 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) coarse_again = 0x5f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) coarse_dgain = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) fine_dgain = gain * 128 / 48640 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) } else if (gain < 48640 * 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) coarse_again = 0x5f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) coarse_dgain = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) fine_dgain = gain * 128 / 48640 / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) } else if (gain < 48640 * 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) coarse_again = 0x5f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) coarse_dgain = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) fine_dgain = gain * 128 / 48640 / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dev_dbg(&client->dev, "c_again: 0x%x, c_dgain: 0x%x, f_dgain: 0x%0x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) coarse_again, coarse_dgain, fine_dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ret = sc3336_write_reg(sc3336->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) SC3336_REG_DIG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) SC3336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) coarse_dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ret |= sc3336_write_reg(sc3336->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) SC3336_REG_DIG_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) SC3336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) fine_dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ret |= sc3336_write_reg(sc3336->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) SC3336_REG_ANA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) SC3336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) coarse_again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int sc3336_get_reso_dist(const struct sc3336_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static const struct sc3336_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) sc3336_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dist = sc3336_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int sc3336_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct sc3336 *sc3336 = to_sc3336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) const struct sc3336_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u64 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) mutex_lock(&sc3336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) mode = sc3336_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) mutex_unlock(&sc3336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) sc3336->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) __v4l2_ctrl_modify_range(sc3336->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) __v4l2_ctrl_modify_range(sc3336->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) SC3336_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) dst_link_freq = mode->link_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) SC3336_BITS_PER_SAMPLE * 2 * SC3336_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) __v4l2_ctrl_s_ctrl_int64(sc3336->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) __v4l2_ctrl_s_ctrl(sc3336->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) sc3336->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) mutex_unlock(&sc3336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static int sc3336_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct sc3336 *sc3336 = to_sc3336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) const struct sc3336_mode *mode = sc3336->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) mutex_lock(&sc3336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) mutex_unlock(&sc3336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /* format info: width/height/data type/virctual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) mutex_unlock(&sc3336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static int sc3336_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct sc3336 *sc3336 = to_sc3336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) code->code = sc3336->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static int sc3336_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (fse->code != supported_modes[0].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static int sc3336_enable_test_pattern(struct sc3336 *sc3336, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) ret = sc3336_read_reg(sc3336->client, SC3336_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) SC3336_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) val |= SC3336_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) val &= ~SC3336_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ret |= sc3336_write_reg(sc3336->client, SC3336_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) SC3336_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static int sc3336_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct sc3336 *sc3336 = to_sc3336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) const struct sc3336_mode *mode = sc3336->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (sc3336->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) fi->interval = sc3336->cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static int sc3336_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct sc3336 *sc3336 = to_sc3336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) const struct sc3336_mode *mode = sc3336->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) u32 val = 1 << (SC3336_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) val |= V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) val |= V4L2_MBUS_CSI2_CHANNEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) static void sc3336_get_module_inf(struct sc3336 *sc3336,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) strscpy(inf->base.sensor, SC3336_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) strscpy(inf->base.module, sc3336->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) strscpy(inf->base.lens, sc3336->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static long sc3336_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct sc3336 *sc3336 = to_sc3336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) sc3336_get_module_inf(sc3336, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) hdr->hdr_mode = sc3336->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) w = sc3336->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) h = sc3336->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) sc3336->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (i == ARRAY_SIZE(supported_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dev_err(&sc3336->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) w = sc3336->cur_mode->hts_def - sc3336->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) h = sc3336->cur_mode->vts_def - sc3336->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) __v4l2_ctrl_modify_range(sc3336->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) __v4l2_ctrl_modify_range(sc3336->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) SC3336_VTS_MAX - sc3336->cur_mode->height, 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) sc3336->cur_fps = sc3336->cur_mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ret = sc3336_write_reg(sc3336->client, SC3336_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) SC3336_REG_VALUE_08BIT, SC3336_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ret = sc3336_write_reg(sc3336->client, SC3336_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) SC3336_REG_VALUE_08BIT, SC3336_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static long sc3336_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ret = sc3336_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (copy_to_user(up, inf, sizeof(*inf)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ret = sc3336_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (copy_to_user(up, hdr, sizeof(*hdr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) ret = sc3336_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ret = sc3336_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ret = sc3336_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static int __sc3336_start_stream(struct sc3336 *sc3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (!sc3336->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ret = sc3336_write_array(sc3336->client, sc3336->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) ret = __v4l2_ctrl_handler_setup(&sc3336->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) if (sc3336->has_init_exp && sc3336->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ret = sc3336_ioctl(&sc3336->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) &sc3336->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) dev_err(&sc3336->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) ret = sc3336_write_reg(sc3336->client, SC3336_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) SC3336_REG_VALUE_08BIT, SC3336_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static int __sc3336_stop_stream(struct sc3336 *sc3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) sc3336->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (sc3336->is_thunderboot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) sc3336->is_first_streamoff = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) return sc3336_write_reg(sc3336->client, SC3336_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) SC3336_REG_VALUE_08BIT, SC3336_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static int __sc3336_power_on(struct sc3336 *sc3336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static int sc3336_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct sc3336 *sc3336 = to_sc3336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct i2c_client *client = sc3336->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) mutex_lock(&sc3336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (on == sc3336->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (sc3336->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) sc3336->is_thunderboot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) __sc3336_power_on(sc3336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ret = __sc3336_start_stream(sc3336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) __sc3336_stop_stream(sc3336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) sc3336->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) mutex_unlock(&sc3336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static int sc3336_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct sc3336 *sc3336 = to_sc3336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct i2c_client *client = sc3336->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) mutex_lock(&sc3336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (sc3336->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (!sc3336->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ret = sc3336_write_array(sc3336->client, sc3336_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) sc3336->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) sc3336->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) mutex_unlock(&sc3336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static inline u32 sc3336_cal_delay(u32 cycles, struct sc3336 *sc3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return DIV_ROUND_UP(cycles, sc3336->cur_mode->xvclk_freq / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static int __sc3336_power_on(struct sc3336 *sc3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) struct device *dev = &sc3336->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (!IS_ERR_OR_NULL(sc3336->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) ret = pinctrl_select_state(sc3336->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) sc3336->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ret = clk_set_rate(sc3336->xvclk, sc3336->cur_mode->xvclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) dev_warn(dev, "Failed to set xvclk rate (%dHz)\n", sc3336->cur_mode->xvclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (clk_get_rate(sc3336->xvclk) != sc3336->cur_mode->xvclk_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) dev_warn(dev, "xvclk mismatched, modes are based on %dHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) sc3336->cur_mode->xvclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ret = clk_prepare_enable(sc3336->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (sc3336->is_thunderboot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (!IS_ERR(sc3336->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) gpiod_set_value_cansleep(sc3336->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ret = regulator_bulk_enable(SC3336_NUM_SUPPLIES, sc3336->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (!IS_ERR(sc3336->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) gpiod_set_value_cansleep(sc3336->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (!IS_ERR(sc3336->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) gpiod_set_value_cansleep(sc3336->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (!IS_ERR(sc3336->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) usleep_range(6000, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) usleep_range(12000, 16000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) delay_us = sc3336_cal_delay(8192, sc3336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) clk_disable_unprepare(sc3336->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static void __sc3336_power_off(struct sc3336 *sc3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct device *dev = &sc3336->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) clk_disable_unprepare(sc3336->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (sc3336->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (sc3336->is_first_streamoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) sc3336->is_thunderboot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) sc3336->is_first_streamoff = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (!IS_ERR(sc3336->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) gpiod_set_value_cansleep(sc3336->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) clk_disable_unprepare(sc3336->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (!IS_ERR(sc3336->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) gpiod_set_value_cansleep(sc3336->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (!IS_ERR_OR_NULL(sc3336->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ret = pinctrl_select_state(sc3336->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) sc3336->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) regulator_bulk_disable(SC3336_NUM_SUPPLIES, sc3336->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static int sc3336_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) struct sc3336 *sc3336 = to_sc3336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return __sc3336_power_on(sc3336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static int sc3336_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) struct sc3336 *sc3336 = to_sc3336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) __sc3336_power_off(sc3336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static int sc3336_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct sc3336 *sc3336 = to_sc3336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) const struct sc3336_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) mutex_lock(&sc3336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) mutex_unlock(&sc3336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static int sc3336_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static const struct dev_pm_ops sc3336_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) SET_RUNTIME_PM_OPS(sc3336_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) sc3336_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static const struct v4l2_subdev_internal_ops sc3336_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) .open = sc3336_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static const struct v4l2_subdev_core_ops sc3336_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .s_power = sc3336_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .ioctl = sc3336_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .compat_ioctl32 = sc3336_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) static const struct v4l2_subdev_video_ops sc3336_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .s_stream = sc3336_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .g_frame_interval = sc3336_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static const struct v4l2_subdev_pad_ops sc3336_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .enum_mbus_code = sc3336_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .enum_frame_size = sc3336_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .enum_frame_interval = sc3336_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) .get_fmt = sc3336_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) .set_fmt = sc3336_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) .get_mbus_config = sc3336_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static const struct v4l2_subdev_ops sc3336_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) .core = &sc3336_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) .video = &sc3336_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) .pad = &sc3336_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static void sc3336_modify_fps_info(struct sc3336 *sc3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) const struct sc3336_mode *mode = sc3336->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) sc3336->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) sc3336->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static int sc3336_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct sc3336 *sc3336 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) struct sc3336, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) struct i2c_client *client = sc3336->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) max = sc3336->cur_mode->height + ctrl->val - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) __v4l2_ctrl_modify_range(sc3336->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) sc3336->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) sc3336->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) sc3336->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (sc3336->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) val = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) ret = sc3336_write_reg(sc3336->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) SC3336_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) SC3336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) SC3336_FETCH_EXP_H(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) ret |= sc3336_write_reg(sc3336->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) SC3336_REG_EXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) SC3336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) SC3336_FETCH_EXP_M(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ret |= sc3336_write_reg(sc3336->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) SC3336_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) SC3336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) SC3336_FETCH_EXP_L(val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) dev_dbg(&client->dev, "set gain 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (sc3336->cur_mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) ret = sc3336_set_gain_reg(sc3336, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) dev_dbg(&client->dev, "set vblank 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) ret = sc3336_write_reg(sc3336->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) SC3336_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) SC3336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) (ctrl->val + sc3336->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) ret |= sc3336_write_reg(sc3336->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) SC3336_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) SC3336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) (ctrl->val + sc3336->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) sc3336->cur_vts = ctrl->val + sc3336->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (sc3336->cur_vts != sc3336->cur_mode->vts_def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) sc3336_modify_fps_info(sc3336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) ret = sc3336_enable_test_pattern(sc3336, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) ret = sc3336_read_reg(sc3336->client, SC3336_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) SC3336_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ret |= sc3336_write_reg(sc3336->client, SC3336_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) SC3336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) SC3336_FETCH_MIRROR(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) ret = sc3336_read_reg(sc3336->client, SC3336_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) SC3336_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) ret |= sc3336_write_reg(sc3336->client, SC3336_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) SC3336_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) SC3336_FETCH_FLIP(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static const struct v4l2_ctrl_ops sc3336_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .s_ctrl = sc3336_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) static int sc3336_initialize_controls(struct sc3336 *sc3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) const struct sc3336_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) u64 dst_link_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) handler = &sc3336->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) mode = sc3336->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) handler->lock = &sc3336->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) sc3336->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ARRAY_SIZE(link_freq_menu_items) - 1, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (sc3336->link_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) sc3336->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) dst_link_freq = mode->link_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) dst_pixel_rate = (u32)link_freq_menu_items[mode->link_freq_idx] /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) SC3336_BITS_PER_SAMPLE * 2 * SC3336_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) sc3336->pixel_rate = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) 0, PIXEL_RATE_WITH_255M_10BIT, 1, dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) __v4l2_ctrl_s_ctrl(sc3336->link_freq, dst_link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) sc3336->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (sc3336->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) sc3336->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) sc3336->vblank = v4l2_ctrl_new_std(handler, &sc3336_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) SC3336_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) exposure_max = mode->vts_def - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) sc3336->exposure = v4l2_ctrl_new_std(handler, &sc3336_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) V4L2_CID_EXPOSURE, SC3336_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) exposure_max, SC3336_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) sc3336->anal_gain = v4l2_ctrl_new_std(handler, &sc3336_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) V4L2_CID_ANALOGUE_GAIN, SC3336_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) SC3336_GAIN_MAX, SC3336_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) SC3336_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) sc3336->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) &sc3336_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) ARRAY_SIZE(sc3336_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) 0, 0, sc3336_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) v4l2_ctrl_new_std(handler, &sc3336_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) v4l2_ctrl_new_std(handler, &sc3336_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) dev_err(&sc3336->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) sc3336->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) sc3336->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) sc3336->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) static int sc3336_check_sensor_id(struct sc3336 *sc3336,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) struct device *dev = &sc3336->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (sc3336->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) ret = sc3336_read_reg(client, SC3336_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) SC3336_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static int sc3336_configure_regulators(struct sc3336 *sc3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) for (i = 0; i < SC3336_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) sc3336->supplies[i].supply = sc3336_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return devm_regulator_bulk_get(&sc3336->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) SC3336_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) sc3336->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) static int sc3336_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) struct sc3336 *sc3336;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) int i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) sc3336 = devm_kzalloc(dev, sizeof(*sc3336), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) if (!sc3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) &sc3336->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) &sc3336->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) &sc3336->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) &sc3336->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) sc3336->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) sc3336->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) sc3336->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if (i == ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) sc3336->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) sc3336->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (IS_ERR(sc3336->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) sc3336->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) if (IS_ERR(sc3336->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) sc3336->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) if (IS_ERR(sc3336->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) sc3336->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if (!IS_ERR(sc3336->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) sc3336->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) pinctrl_lookup_state(sc3336->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) if (IS_ERR(sc3336->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) sc3336->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) pinctrl_lookup_state(sc3336->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (IS_ERR(sc3336->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) ret = sc3336_configure_regulators(sc3336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) mutex_init(&sc3336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) sd = &sc3336->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) v4l2_i2c_subdev_init(sd, client, &sc3336_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) ret = sc3336_initialize_controls(sc3336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) ret = __sc3336_power_on(sc3336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) ret = sc3336_check_sensor_id(sc3336, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) sd->internal_ops = &sc3336_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) sc3336->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) ret = media_entity_pads_init(&sd->entity, 1, &sc3336->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) if (strcmp(sc3336->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) sc3336->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) SC3336_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) __sc3336_power_off(sc3336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) v4l2_ctrl_handler_free(&sc3336->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) mutex_destroy(&sc3336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) static int sc3336_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) struct sc3336 *sc3336 = to_sc3336(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) v4l2_ctrl_handler_free(&sc3336->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) mutex_destroy(&sc3336->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) __sc3336_power_off(sc3336);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) static const struct of_device_id sc3336_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) { .compatible = "smartsens,sc3336" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) MODULE_DEVICE_TABLE(of, sc3336_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) static const struct i2c_device_id sc3336_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) { "smartsens,sc3336", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) static struct i2c_driver sc3336_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .name = SC3336_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .pm = &sc3336_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) .of_match_table = of_match_ptr(sc3336_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .probe = &sc3336_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .remove = &sc3336_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .id_table = sc3336_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) return i2c_add_driver(&sc3336_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) i2c_del_driver(&sc3336_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) subsys_initcall(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) MODULE_DESCRIPTION("smartsens sc3336 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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