^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * SC301IOT driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2022 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SC301IOT_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SC301IOT_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SC301IOT_LINK_FREQ_594 540000000// 540Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PIXEL_RATE_WITH_594M_10BIT (SC301IOT_LINK_FREQ_594 / SC301IOT_BITS_PER_SAMPLE * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 2 * SC301IOT_LANES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SC301IOT_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CHIP_ID 0xcc40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SC301IOT_REG_CHIP_ID 0x3107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SC301IOT_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SC301IOT_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SC301IOT_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SC301IOT_REG_EXPOSURE_H 0x3e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC301IOT_REG_EXPOSURE_M 0x3e01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SC301IOT_REG_EXPOSURE_L 0x3e02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SC301IOT_REG_SEXPOSURE_H 0x3e22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SC301IOT_REG_SEXPOSURE_M 0x3e04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SC301IOT_REG_SEXPOSURE_L 0x3e05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SC301IOT_EXPOSURE_MIN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SC301IOT_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SC301IOT_VTS_MIN 0x640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SC301IOT_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SC301IOT_REG_DIG_GAIN 0x3e06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SC301IOT_REG_DIG_FINE_GAIN 0x3e07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) //#define SC301IOT_REG_ANA_GAIN 0x3e08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SC301IOT_REG_ANA_GAIN 0x3e09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SC301IOT_REG_SDIG_GAIN 0x3e10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC301IOT_REG_SDIG_FINE_GAIN 0x3e11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) //#define SC301IOT_REG_SANA_GAIN 0x3e12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SC301IOT_REG_SANA_GAIN 0x3e13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SC301IOT_GAIN_MIN 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SC301IOT_GAIN_MAX (6426) //(100.416*64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SC301IOT_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SC301IOT_GAIN_DEFAULT 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SC301IOT_LGAIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SC301IOT_SGAIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SC301IOT_REG_GROUP_HOLD 0x3812
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SC301IOT_GROUP_HOLD_START 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SC301IOT_GROUP_HOLD_END 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) //#define SC301IOT_REG_HIGH_TEMP_H 0x3974
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) //#define SC301IOT_REG_HIGH_TEMP_L 0x3975
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SC301IOT_REG_TEST_PATTERN 0x4501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SC301IOT_TEST_PATTERN_BIT_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SC301IOT_REG_VTS_H 0x320e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SC301IOT_REG_VTS_L 0x320f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SC301IOT_FLIP_MIRROR_REG 0x3221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SC301IOT_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SC301IOT_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SC301IOT_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SC301IOT_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SC301IOT_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SC301IOT_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SC301IOT_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define REG_DELAY 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SC301IOT_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SC301IOT_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SC301IOT_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SC301IOT_NAME "SC301IOT"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static const char * const SC301IOT_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SC301IOT_NUM_SUPPLIES ARRAY_SIZE(SC301IOT_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct SC301IOT_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct SC301IOT {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct regulator_bulk_data supplies[SC301IOT_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct v4l2_fract cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) const struct SC301IOT_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u32 sync_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define to_SC301IOT(sd) container_of(sd, struct SC301IOT, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct regval SC301IOT_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * mipi_datarate per lane 540Mbps, 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct regval SC301IOT_linear_10_2048x1536_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x37f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x301c, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x301f, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x30b8, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3208, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3209, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x320a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x320b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x320c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x320d, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x320e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x320f, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3214, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3215, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) // {0x3223, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3253, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3274, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3301, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x3306, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3308, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x330b, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x330e, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3314, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x331e, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x331f, 0x7d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3333, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x335e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x335f, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3364, 0x5e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x337c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x337d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3390, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3391, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3392, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3393, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3394, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3395, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3396, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3397, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3398, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3399, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x339a, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x339b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x339c, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x33a2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x33ad, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x33b1, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x33b3, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x33f9, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x33fb, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x33fc, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x33fd, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x349f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x34a6, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x34a7, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x34a8, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x34a9, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x34aa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x34ab, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x34ac, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x34ad, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x34f8, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x34f9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x3630, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3631, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3632, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3633, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3637, 0x4d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3638, 0xcb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x363a, 0x8b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x363c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3640, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3641, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3670, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x3674, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3675, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3676, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3677, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x3678, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3679, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x367c, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x367d, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x367e, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x367f, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3690, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x3691, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3692, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3699, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x369a, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x369b, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x369c, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x369d, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x36a2, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x36a3, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x36ea, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x36eb, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x36ec, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x36ed, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x370f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x3714, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x3722, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x3724, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3725, 0xc1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x3728, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x3771, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3772, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3773, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x377a, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x377b, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x37fa, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x37fb, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x37fc, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x37fd, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x3905, 0x8d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x391d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3922, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x3926, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3933, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3934, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3937, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x3939, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x393a, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x39dc, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x3e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x3e01, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x3e02, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x3e03, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x3e1b, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x4407, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x440e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x5001, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x5007, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x36e9, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x37f9, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x3251, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* strong signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x3650, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x3651, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * mipi_datarate per lane 1080Mbps, HDR 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const struct regval SC301IOT_hdr_10_2048x1536_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x37f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x301c, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x301f, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x30b8, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x3208, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x3209, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x320a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x320b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x320c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x320d, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x320e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x320f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x3214, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x3215, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) // {0x3223, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x3250, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x3253, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x3274, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x3281, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x3301, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x3304, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x3306, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x3308, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x3309, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x330b, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x330e, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x3314, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x331e, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x331f, 0x91},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x3333, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x3334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x335e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x335f, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x3364, 0x5e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x337c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x337d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x3390, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x3391, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x3392, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x3393, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x3394, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x3395, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x3396, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x3397, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x3398, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x3399, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x339a, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x339b, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x339c, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x33a2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x33ad, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x33b1, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x33b3, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x33f9, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x33fb, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x33fc, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x33fd, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x349f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x34a6, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x34a7, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x34a8, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x34a9, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x34aa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x34ab, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x34ac, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x34ad, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x34f8, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x34f9, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x3630, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x3631, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x3632, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x3633, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x3637, 0x4d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x3638, 0xcb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x363a, 0x8b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x363c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x3641, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x3670, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x3674, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x3675, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x3676, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x3677, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x3678, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x3679, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x367c, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x367d, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x367e, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x367f, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x3690, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x3691, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x3692, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3699, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x369a, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x369b, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x369c, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x369d, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x36a2, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x36a3, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x36ea, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x36eb, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x36ec, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x36ed, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x370f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x3714, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x3722, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x3724, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x3725, 0xc1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x3728, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x3771, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x3772, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x3773, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x377a, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x377b, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x37fa, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x37fb, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x37fc, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x37fd, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x3905, 0x8d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x391d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x3922, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x3926, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x3933, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x3934, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x3937, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x3939, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x393a, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x39dc, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x3e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x3e01, 0xb9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x3e02, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x3e03, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x3e04, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x3e05, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x3e1b, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x3e23, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x3e24, 0xbf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x4407, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x440e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x4509, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x4816, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x5001, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x5007, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x36e9, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x37f9, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x3251, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* strong signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x3650, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x3651, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * mipi_datarate per lane 540Mbps, 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const struct regval SC301IOT_linear_10_1536x1536_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x37f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x301c, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x301f, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x30b8, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x3208, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x3209, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x320a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x320b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x320c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x320d, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x320e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x320f, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x3210, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x3214, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x3215, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) // {0x3223, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x3253, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x3274, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x3301, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x3306, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x3308, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x330b, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x330e, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x3314, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x331e, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x331f, 0x7d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x3333, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x3334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x335e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x335f, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x3364, 0x5e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x337c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x337d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x3390, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x3391, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x3392, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x3393, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x3394, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x3395, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x3396, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x3397, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x3398, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x3399, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x339a, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x339b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x339c, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x33a2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x33ad, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x33b1, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x33b3, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x33f9, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0x33fb, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {0x33fc, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0x33fd, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x349f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x34a6, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x34a7, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x34a8, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x34a9, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x34aa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {0x34ab, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {0x34ac, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0x34ad, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x34f8, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x34f9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {0x3630, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {0x3631, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {0x3632, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {0x3633, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {0x3637, 0x4d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {0x3638, 0xcb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {0x363a, 0x8b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x363c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x3640, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x3641, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {0x3670, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x3674, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x3675, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x3676, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x3677, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x3678, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x3679, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x367c, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x367d, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x367e, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x367f, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x3690, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x3691, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x3692, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x3699, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x369a, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x369b, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x369c, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x369d, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {0x36a2, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {0x36a3, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {0x36ea, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {0x36eb, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {0x36ec, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {0x36ed, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {0x370f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {0x3714, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {0x3722, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {0x3724, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {0x3725, 0xc1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {0x3728, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {0x3771, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {0x3772, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {0x3773, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {0x377a, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {0x377b, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {0x37fa, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {0x37fb, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {0x37fc, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {0x37fd, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {0x3905, 0x8d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) {0x391d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {0x3922, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {0x3926, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {0x3933, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {0x3934, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) {0x3937, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {0x3939, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {0x393a, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {0x39dc, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {0x3e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {0x3e01, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {0x3e02, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {0x3e03, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {0x3e1b, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) {0x4407, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {0x440e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {0x5001, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {0x5007, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {0x36e9, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {0x37f9, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {0x3251, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* strong signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {0x3650, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {0x3651, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * mipi_datarate per lane 1080Mbps, HDR 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static const struct regval SC301IOT_hdr_10_1536x1536_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {0x37f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {0x301c, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {0x301f, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {0x30b8, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {0x3208, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {0x3209, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {0x320a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {0x320b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {0x320c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {0x320d, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {0x320e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {0x320f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {0x3210, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {0x3214, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {0x3215, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) // {0x3223, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {0x3250, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {0x3253, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) {0x3274, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {0x3281, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {0x3301, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {0x3304, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {0x3306, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {0x3308, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) {0x3309, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {0x330b, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {0x330e, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {0x3314, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {0x331e, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {0x331f, 0x91},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {0x3333, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) {0x3334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {0x335e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {0x335f, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {0x3364, 0x5e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) {0x337c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {0x337d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {0x3390, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {0x3391, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {0x3392, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {0x3393, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {0x3394, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {0x3395, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {0x3396, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) {0x3397, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {0x3398, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {0x3399, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {0x339a, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {0x339b, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {0x339c, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {0x33a2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {0x33ad, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {0x33b1, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {0x33b3, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {0x33f9, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {0x33fb, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {0x33fc, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {0x33fd, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {0x349f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {0x34a6, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {0x34a7, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {0x34a8, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {0x34a9, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {0x34aa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {0x34ab, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {0x34ac, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) {0x34ad, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {0x34f8, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {0x34f9, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {0x3630, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {0x3631, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {0x3632, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {0x3633, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {0x3637, 0x4d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {0x3638, 0xcb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {0x363a, 0x8b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {0x363c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {0x3641, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {0x3670, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {0x3674, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {0x3675, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {0x3676, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {0x3677, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {0x3678, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {0x3679, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {0x367c, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {0x367d, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {0x367e, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {0x367f, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) {0x3690, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {0x3691, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {0x3692, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {0x3699, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {0x369a, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {0x369b, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) {0x369c, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {0x369d, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {0x36a2, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {0x36a3, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {0x36ea, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {0x36eb, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {0x36ec, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) {0x36ed, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {0x370f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {0x3714, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {0x3722, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {0x3724, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {0x3725, 0xc1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) {0x3728, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {0x3771, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) {0x3772, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {0x3773, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {0x377a, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) {0x377b, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {0x37fa, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {0x37fb, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {0x37fc, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {0x37fd, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {0x3905, 0x8d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {0x391d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {0x3922, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {0x3926, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {0x3933, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {0x3934, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {0x3937, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {0x3939, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {0x393a, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {0x39dc, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {0x3e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {0x3e01, 0xb9},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {0x3e02, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {0x3e03, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) {0x3e04, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {0x3e05, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {0x3e1b, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {0x3e23, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {0x3e24, 0xbf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) {0x4407, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {0x440e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {0x4509, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {0x4816, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {0x5001, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {0x5007, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {0x36e9, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {0x37f9, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {0x3251, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* strong signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {0x3650, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) {0x3651, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) static const struct SC301IOT_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .width = 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .height = 1536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .exp_def = 0x638,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .hts_def = 0x8ca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .vts_def = 0x640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .reg_list = SC301IOT_linear_10_2048x1536_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .width = 2048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .height = 1536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .exp_def = 0xb9c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .hts_def = 0x8ca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .vts_def = 0xc80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .reg_list = SC301IOT_hdr_10_2048x1536_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .width = 1536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .height = 1536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .exp_def = 0x96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .hts_def = 0x8ca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .vts_def = 0x640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .reg_list = SC301IOT_linear_10_1536x1536_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) .width = 1536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .height = 1536,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .exp_def = 0xb9c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .hts_def = 0x8ca,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .vts_def = 0xc80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) .reg_list = SC301IOT_hdr_10_1536x1536_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) SC301IOT_LINK_FREQ_594
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static const char * const SC301IOT_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static int SC301IOT_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) static int SC301IOT_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ret = SC301IOT_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) SC301IOT_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static int SC301IOT_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* mode: 0 = lgain 1 = sgain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) static int SC301IOT_set_gain_reg(struct SC301IOT *SC301IOT, u32 gain, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) u8 ANA_Coarse_gain_reg = 0x00, DIG_Fine_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) u32 ANA_Coarse_gain = 1024, DIG_gain_reg = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) gain = gain * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (gain <= 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) gain = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) else if (gain > SC301IOT_GAIN_MAX * 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) gain = SC301IOT_GAIN_MAX * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (gain < 1606) { // start Ana again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ANA_Coarse_gain = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ANA_Coarse_gain_reg = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) } else if (gain < 3397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ANA_Coarse_gain = 1606;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ANA_Coarse_gain_reg = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) } else if (gain < 6426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ANA_Coarse_gain = 3397;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ANA_Coarse_gain_reg = 0x48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) } else if (gain < 12853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ANA_Coarse_gain = 6426;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ANA_Coarse_gain_reg = 0x49;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) } else if (gain < 25706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ANA_Coarse_gain = 12853;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ANA_Coarse_gain_reg = 0x4b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) } else if (gain < 51412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ANA_Coarse_gain = 25706;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ANA_Coarse_gain_reg = 0x4f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ANA_Coarse_gain = 51412;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ANA_Coarse_gain_reg = 0x5f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) gain = gain * 1024 / ANA_Coarse_gain; // start Dig again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (gain <= 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) gain = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) else if (gain >= 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) gain = 2031;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) DIG_Fine_gain_reg = gain/8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (mode == SC301IOT_LGAIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ret = SC301IOT_write_reg(SC301IOT->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) SC301IOT_REG_DIG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) DIG_gain_reg & 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) ret |= SC301IOT_write_reg(SC301IOT->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) SC301IOT_REG_DIG_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) DIG_Fine_gain_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ret |= SC301IOT_write_reg(SC301IOT->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) SC301IOT_REG_ANA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) ANA_Coarse_gain_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) ret = SC301IOT_write_reg(SC301IOT->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) SC301IOT_REG_SDIG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) DIG_gain_reg & 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) ret |= SC301IOT_write_reg(SC301IOT->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) SC301IOT_REG_SDIG_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) DIG_Fine_gain_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ret |= SC301IOT_write_reg(SC301IOT->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) SC301IOT_REG_SANA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ANA_Coarse_gain_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static int SC301IOT_set_hdrae(struct SC301IOT *SC301IOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) u32 l_a_gain, m_a_gain, s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (!SC301IOT->has_init_exp && !SC301IOT->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) SC301IOT->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) SC301IOT->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) dev_dbg(&SC301IOT->client->dev, "SC301IOT don't stream, record exp for hdr!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) l_a_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) m_a_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) s_a_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) dev_dbg(&SC301IOT->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) l_exp_time, m_exp_time, s_exp_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) l_a_gain, m_a_gain, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (SC301IOT->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) //2 stagger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) l_a_gain = m_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) l_exp_time = m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) //set exposure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) //l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) //s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) l_exp_time = l_exp_time * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) s_exp_time = s_exp_time * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (l_exp_time > 2998) //(3200 - 191 - 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) l_exp_time = 2998;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (s_exp_time > 182) //(191 - 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) s_exp_time = 182;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ret = SC301IOT_write_reg(SC301IOT->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) SC301IOT_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) SC301IOT_FETCH_EXP_H(l_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ret |= SC301IOT_write_reg(SC301IOT->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) SC301IOT_REG_EXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) SC301IOT_FETCH_EXP_M(l_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ret |= SC301IOT_write_reg(SC301IOT->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) SC301IOT_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) SC301IOT_FETCH_EXP_L(l_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) ret |= SC301IOT_write_reg(SC301IOT->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) SC301IOT_REG_SEXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) SC301IOT_FETCH_EXP_M(s_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret |= SC301IOT_write_reg(SC301IOT->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) SC301IOT_REG_SEXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) SC301IOT_FETCH_EXP_L(s_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ret |= SC301IOT_set_gain_reg(SC301IOT, l_a_gain, SC301IOT_LGAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) ret |= SC301IOT_set_gain_reg(SC301IOT, s_a_gain, SC301IOT_SGAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static int SC301IOT_get_reso_dist(const struct SC301IOT_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static const struct SC301IOT_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) SC301IOT_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) dist = SC301IOT_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static int SC301IOT_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct SC301IOT *SC301IOT = to_SC301IOT(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) const struct SC301IOT_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) mutex_lock(&SC301IOT->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) mode = SC301IOT_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) mutex_unlock(&SC301IOT->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) SC301IOT->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) __v4l2_ctrl_modify_range(SC301IOT->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) __v4l2_ctrl_modify_range(SC301IOT->vblank, SC301IOT_VTS_MIN - vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) SC301IOT_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) SC301IOT->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) SC301IOT->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) mutex_unlock(&SC301IOT->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) static int SC301IOT_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct SC301IOT *SC301IOT = to_SC301IOT(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) const struct SC301IOT_mode *mode = SC301IOT->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) mutex_lock(&SC301IOT->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) mutex_unlock(&SC301IOT->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) /* format info: width/height/data type/virctual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) mutex_unlock(&SC301IOT->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static int SC301IOT_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) struct SC301IOT *SC301IOT = to_SC301IOT(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) code->code = SC301IOT->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) static int SC301IOT_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (fse->code != supported_modes[0].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static int SC301IOT_enable_test_pattern(struct SC301IOT *SC301IOT, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ret = SC301IOT_read_reg(SC301IOT->client, SC301IOT_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) SC301IOT_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) val |= SC301IOT_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) val &= ~SC301IOT_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) ret |= SC301IOT_write_reg(SC301IOT->client, SC301IOT_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) SC301IOT_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static int SC301IOT_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) struct SC301IOT *SC301IOT = to_SC301IOT(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) const struct SC301IOT_mode *mode = SC301IOT->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (SC301IOT->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) fi->interval = SC301IOT->cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) static int SC301IOT_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) struct SC301IOT *SC301IOT = to_SC301IOT(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) const struct SC301IOT_mode *mode = SC301IOT->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) u32 val = 1 << (SC301IOT_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) val |= V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) val |= V4L2_MBUS_CSI2_CHANNEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static void SC301IOT_get_module_inf(struct SC301IOT *SC301IOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) strscpy(inf->base.sensor, SC301IOT_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) strscpy(inf->base.module, SC301IOT->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) strscpy(inf->base.lens, SC301IOT->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static int SC301IOT_get_channel_info(struct SC301IOT *SC301IOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct rkmodule_channel_info *ch_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) ch_info->vc = SC301IOT->cur_mode->vc[ch_info->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) ch_info->width = SC301IOT->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) ch_info->height = SC301IOT->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) ch_info->bus_fmt = SC301IOT->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static long SC301IOT_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) struct SC301IOT *SC301IOT = to_SC301IOT(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) u32 sync_mode = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) SC301IOT_get_module_inf(SC301IOT, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) hdr->hdr_mode = SC301IOT->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) w = SC301IOT->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) h = SC301IOT->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) SC301IOT->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (i == ARRAY_SIZE(supported_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) dev_err(&SC301IOT->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) w = SC301IOT->cur_mode->hts_def - SC301IOT->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) h = SC301IOT->cur_mode->vts_def - SC301IOT->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) __v4l2_ctrl_modify_range(SC301IOT->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) __v4l2_ctrl_modify_range(SC301IOT->vblank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) SC301IOT_VTS_MIN - SC301IOT->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) SC301IOT_VTS_MAX - SC301IOT->cur_mode->height, 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) SC301IOT->cur_fps = SC301IOT->cur_mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) SC301IOT->cur_vts = SC301IOT->cur_mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) SC301IOT_set_hdrae(SC301IOT, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ret = SC301IOT_write_reg(SC301IOT->client, SC301IOT_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) SC301IOT_REG_VALUE_08BIT, SC301IOT_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) ret = SC301IOT_write_reg(SC301IOT->client, SC301IOT_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) SC301IOT_REG_VALUE_08BIT, SC301IOT_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) case RKMODULE_GET_SYNC_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) *((u32 *)arg) = SC301IOT->sync_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) case RKMODULE_SET_SYNC_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) sync_mode = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (sync_mode > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) SC301IOT->sync_mode = sync_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) dev_info(&SC301IOT->client->dev, "sync_mode = [%u]\n", SC301IOT->sync_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) ch_info = (struct rkmodule_channel_info *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) ret = SC301IOT_get_channel_info(SC301IOT, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) static long SC301IOT_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) ret = SC301IOT_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (copy_to_user(up, inf, sizeof(*inf))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (copy_from_user(cfg, up, sizeof(*cfg))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) ret = SC301IOT_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) ret = SC301IOT_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (copy_to_user(up, hdr, sizeof(*hdr))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (copy_from_user(hdr, up, sizeof(*hdr))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) ret = SC301IOT_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (copy_from_user(hdrae, up, sizeof(*hdrae))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) ret = SC301IOT_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (copy_from_user(&stream, up, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ret = SC301IOT_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (!ch_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) ret = SC301IOT_ioctl(sd, cmd, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) ret = copy_to_user(up, ch_info, sizeof(*ch_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) kfree(ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) static int SC301IOT_s_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) struct SC301IOT *SC301IOT = to_SC301IOT(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) struct device *dev = sd->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) int ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) s64 vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) u32 fps_set, current_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) fps_set = DIV_ROUND_CLOSEST(fi->interval.denominator, fi->interval.numerator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) dev_info(dev, "%s set fps = %u\n", __func__, fps_set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) mutex_lock(&SC301IOT->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) current_fps = DIV_ROUND_CLOSEST(SC301IOT->cur_mode->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) SC301IOT->cur_mode->max_fps.numerator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) vblank_def = SC301IOT->cur_mode->vts_def * current_fps / fps_set -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) SC301IOT->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if (SC301IOT->sync_mode == SLAVE_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) vblank_def -= 3; // adjust vts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) ret = __v4l2_ctrl_s_ctrl(SC301IOT->vblank, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) mutex_unlock(&SC301IOT->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) dev_err(dev, "%s __v4l2_ctrl_s_ctrl error - %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) static int __SC301IOT_start_stream(struct SC301IOT *SC301IOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) ret = SC301IOT_write_array(SC301IOT->client, SC301IOT->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) ret = __v4l2_ctrl_handler_setup(&SC301IOT->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) if (SC301IOT->has_init_exp && SC301IOT->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) ret = SC301IOT_ioctl(&SC301IOT->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) &SC301IOT->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) dev_err(&SC301IOT->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (SC301IOT->sync_mode == SLAVE_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) SC301IOT_write_reg(SC301IOT->client, 0x3222,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) SC301IOT_REG_VALUE_08BIT, 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) SC301IOT_write_reg(SC301IOT->client, 0x3223,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) SC301IOT_REG_VALUE_08BIT, 0xc8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) SC301IOT_write_reg(SC301IOT->client, 0x3225,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) SC301IOT_REG_VALUE_08BIT, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) SC301IOT_write_reg(SC301IOT->client, 0x322e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) SC301IOT_REG_VALUE_08BIT, (SC301IOT->cur_vts - 4) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) SC301IOT_write_reg(SC301IOT->client, 0x322f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) SC301IOT_REG_VALUE_08BIT, (SC301IOT->cur_vts - 4) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) } else if (SC301IOT->sync_mode == NO_SYNC_MODE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) SC301IOT_write_reg(SC301IOT->client, 0x3222,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) SC301IOT_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) SC301IOT_write_reg(SC301IOT->client, 0x3223,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) SC301IOT_REG_VALUE_08BIT, 0xd0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) SC301IOT_write_reg(SC301IOT->client, 0x3225,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) SC301IOT_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) SC301IOT_write_reg(SC301IOT->client, 0x322e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) SC301IOT_REG_VALUE_08BIT, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) SC301IOT_write_reg(SC301IOT->client, 0x322f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) SC301IOT_REG_VALUE_08BIT, 0x02);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) dev_info(&SC301IOT->client->dev, "start stream\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) return SC301IOT_write_reg(SC301IOT->client, SC301IOT_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) SC301IOT_REG_VALUE_08BIT, SC301IOT_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) static int __SC301IOT_stop_stream(struct SC301IOT *SC301IOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) SC301IOT->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) dev_info(&SC301IOT->client->dev, "stop stream\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) return SC301IOT_write_reg(SC301IOT->client, SC301IOT_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) SC301IOT_REG_VALUE_08BIT, SC301IOT_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static int SC301IOT_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) struct SC301IOT *SC301IOT = to_SC301IOT(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) struct i2c_client *client = SC301IOT->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) mutex_lock(&SC301IOT->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (on == SC301IOT->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) ret = __SC301IOT_start_stream(SC301IOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) __SC301IOT_stop_stream(SC301IOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) SC301IOT->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) mutex_unlock(&SC301IOT->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) static int SC301IOT_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) struct SC301IOT *SC301IOT = to_SC301IOT(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) struct i2c_client *client = SC301IOT->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) mutex_lock(&SC301IOT->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) if (SC301IOT->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) ret = SC301IOT_write_array(SC301IOT->client, SC301IOT_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) SC301IOT->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) SC301IOT->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) mutex_unlock(&SC301IOT->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) static inline u32 SC301IOT_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) return DIV_ROUND_UP(cycles, SC301IOT_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) static int __SC301IOT_power_on(struct SC301IOT *SC301IOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) struct device *dev = &SC301IOT->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if (!IS_ERR_OR_NULL(SC301IOT->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) ret = pinctrl_select_state(SC301IOT->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) SC301IOT->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) ret = clk_set_rate(SC301IOT->xvclk, SC301IOT_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) if (clk_get_rate(SC301IOT->xvclk) != SC301IOT_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) ret = clk_prepare_enable(SC301IOT->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) if (!IS_ERR(SC301IOT->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) gpiod_set_value_cansleep(SC301IOT->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) ret = regulator_bulk_enable(SC301IOT_NUM_SUPPLIES, SC301IOT->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (!IS_ERR(SC301IOT->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) gpiod_set_value_cansleep(SC301IOT->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) if (!IS_ERR(SC301IOT->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) gpiod_set_value_cansleep(SC301IOT->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) usleep_range(4500, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) ret = clk_set_rate(SC301IOT->xvclk, SC301IOT_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (clk_get_rate(SC301IOT->xvclk) != SC301IOT_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) ret = clk_prepare_enable(SC301IOT->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) if (!IS_ERR(SC301IOT->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) usleep_range(6000, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) usleep_range(12000, 16000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) delay_us = SC301IOT_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) clk_disable_unprepare(SC301IOT->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) static void __SC301IOT_power_off(struct SC301IOT *SC301IOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) struct device *dev = &SC301IOT->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) if (!IS_ERR(SC301IOT->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) gpiod_set_value_cansleep(SC301IOT->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) clk_disable_unprepare(SC301IOT->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (!IS_ERR(SC301IOT->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) gpiod_set_value_cansleep(SC301IOT->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (!IS_ERR_OR_NULL(SC301IOT->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) ret = pinctrl_select_state(SC301IOT->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) SC301IOT->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) regulator_bulk_disable(SC301IOT_NUM_SUPPLIES, SC301IOT->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) static int SC301IOT_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) struct SC301IOT *SC301IOT = to_SC301IOT(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) return __SC301IOT_power_on(SC301IOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) static int SC301IOT_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) struct SC301IOT *SC301IOT = to_SC301IOT(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) __SC301IOT_power_off(SC301IOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static int SC301IOT_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) struct SC301IOT *SC301IOT = to_SC301IOT(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) const struct SC301IOT_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) mutex_lock(&SC301IOT->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) mutex_unlock(&SC301IOT->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) static int SC301IOT_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static const struct dev_pm_ops SC301IOT_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) SET_RUNTIME_PM_OPS(SC301IOT_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) SC301IOT_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) static const struct v4l2_subdev_internal_ops SC301IOT_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .open = SC301IOT_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) static const struct v4l2_subdev_core_ops SC301IOT_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .s_power = SC301IOT_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .ioctl = SC301IOT_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .compat_ioctl32 = SC301IOT_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) static const struct v4l2_subdev_video_ops SC301IOT_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .s_stream = SC301IOT_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .g_frame_interval = SC301IOT_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .s_frame_interval = SC301IOT_s_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) static const struct v4l2_subdev_pad_ops SC301IOT_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .enum_mbus_code = SC301IOT_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .enum_frame_size = SC301IOT_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) .enum_frame_interval = SC301IOT_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) .get_fmt = SC301IOT_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) .set_fmt = SC301IOT_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) .get_mbus_config = SC301IOT_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) static const struct v4l2_subdev_ops SC301IOT_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) .core = &SC301IOT_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .video = &SC301IOT_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .pad = &SC301IOT_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) static void SC301IOT_modify_fps_info(struct SC301IOT *SC301IOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) const struct SC301IOT_mode *mode = SC301IOT->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) SC301IOT->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) SC301IOT->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) static int SC301IOT_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) struct SC301IOT *SC301IOT = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) struct SC301IOT, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) struct i2c_client *client = SC301IOT->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) max = SC301IOT->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) __v4l2_ctrl_modify_range(SC301IOT->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) SC301IOT->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) SC301IOT->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) SC301IOT->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) if (SC301IOT->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) ctrl->val = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) ret = SC301IOT_write_reg(SC301IOT->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) SC301IOT_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) SC301IOT_FETCH_EXP_H(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) ret |= SC301IOT_write_reg(SC301IOT->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) SC301IOT_REG_EXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) SC301IOT_FETCH_EXP_M(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) ret |= SC301IOT_write_reg(SC301IOT->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) SC301IOT_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) SC301IOT_FETCH_EXP_L(ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) if (SC301IOT->cur_mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) ret = SC301IOT_set_gain_reg(SC301IOT, ctrl->val, SC301IOT_LGAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) ret = SC301IOT_write_reg(SC301IOT->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) SC301IOT_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) (ctrl->val + SC301IOT->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) ret |= SC301IOT_write_reg(SC301IOT->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) SC301IOT_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) (ctrl->val + SC301IOT->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) SC301IOT->cur_vts = ctrl->val + SC301IOT->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) if (SC301IOT->cur_vts != SC301IOT->cur_mode->vts_def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) SC301IOT_modify_fps_info(SC301IOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) ret = SC301IOT_enable_test_pattern(SC301IOT, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) ret = SC301IOT_read_reg(SC301IOT->client, SC301IOT_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) SC301IOT_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) ret |= SC301IOT_write_reg(SC301IOT->client, SC301IOT_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) SC301IOT_FETCH_MIRROR(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) ret = SC301IOT_read_reg(SC301IOT->client, SC301IOT_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) SC301IOT_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) ret |= SC301IOT_write_reg(SC301IOT->client, SC301IOT_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) SC301IOT_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) SC301IOT_FETCH_FLIP(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) static const struct v4l2_ctrl_ops SC301IOT_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) .s_ctrl = SC301IOT_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) static int SC301IOT_initialize_controls(struct SC301IOT *SC301IOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) const struct SC301IOT_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) handler = &SC301IOT->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) mode = SC301IOT->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) handler->lock = &SC301IOT->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) 0, PIXEL_RATE_WITH_594M_10BIT, 1, PIXEL_RATE_WITH_594M_10BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) SC301IOT->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) if (SC301IOT->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) SC301IOT->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) SC301IOT->vblank = v4l2_ctrl_new_std(handler, &SC301IOT_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) V4L2_CID_VBLANK, SC301IOT_VTS_MIN - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) SC301IOT_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) exposure_max = mode->vts_def - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) SC301IOT->exposure = v4l2_ctrl_new_std(handler, &SC301IOT_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) V4L2_CID_EXPOSURE, SC301IOT_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) exposure_max, SC301IOT_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) SC301IOT->anal_gain = v4l2_ctrl_new_std(handler, &SC301IOT_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) V4L2_CID_ANALOGUE_GAIN, SC301IOT_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) SC301IOT_GAIN_MAX, SC301IOT_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) SC301IOT_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) SC301IOT->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) &SC301IOT_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) ARRAY_SIZE(SC301IOT_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) 0, 0, SC301IOT_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) v4l2_ctrl_new_std(handler, &SC301IOT_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) v4l2_ctrl_new_std(handler, &SC301IOT_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) dev_err(&SC301IOT->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) SC301IOT->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) SC301IOT->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) SC301IOT->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) SC301IOT->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) static int SC301IOT_check_sensor_id(struct SC301IOT *SC301IOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) struct device *dev = &SC301IOT->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) ret = SC301IOT_read_reg(client, SC301IOT_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) SC301IOT_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) dev_err(dev, "Unexpected chip id(0x%04x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) dev_info(dev, "Detected chip id (0x%04x)\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) static int SC301IOT_configure_regulators(struct SC301IOT *SC301IOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) for (i = 0; i < SC301IOT_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) SC301IOT->supplies[i].supply = SC301IOT_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) return devm_regulator_bulk_get(&SC301IOT->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) SC301IOT_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) SC301IOT->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) static int SC301IOT_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) struct SC301IOT *SC301IOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) const char *sync_mode_name = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) SC301IOT = devm_kzalloc(dev, sizeof(*SC301IOT), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) if (!SC301IOT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) &SC301IOT->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) &SC301IOT->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) &SC301IOT->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) &SC301IOT->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) SC301IOT->sync_mode = NO_SYNC_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) ret = of_property_read_string(node, RKMODULE_CAMERA_SYNC_MODE, &sync_mode_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) if (strcmp(sync_mode_name, RKMODULE_EXTERNAL_MASTER_MODE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) SC301IOT->sync_mode = EXTERNAL_MASTER_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) else if (strcmp(sync_mode_name, RKMODULE_INTERNAL_MASTER_MODE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) SC301IOT->sync_mode = INTERNAL_MASTER_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) else if (strcmp(sync_mode_name, RKMODULE_SLAVE_MODE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) SC301IOT->sync_mode = SLAVE_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) switch (SC301IOT->sync_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) SC301IOT->sync_mode = NO_SYNC_MODE; break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) case NO_SYNC_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) dev_info(dev, "sync_mode = [NO_SYNC_MODE]\n"); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) case EXTERNAL_MASTER_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) case INTERNAL_MASTER_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) dev_info(dev, "sync_mode = [MASTER_MODE]\n"); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) case SLAVE_MODE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) dev_info(dev, "sync_mode = [SLAVE_MODE]\n"); break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) SC301IOT->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) SC301IOT->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) if (i == ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) SC301IOT->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) SC301IOT->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) if (IS_ERR(SC301IOT->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) SC301IOT->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if (IS_ERR(SC301IOT->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) SC301IOT->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) if (IS_ERR(SC301IOT->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) SC301IOT->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) if (!IS_ERR(SC301IOT->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) SC301IOT->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) pinctrl_lookup_state(SC301IOT->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) if (IS_ERR(SC301IOT->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) SC301IOT->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) pinctrl_lookup_state(SC301IOT->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) if (IS_ERR(SC301IOT->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) ret = SC301IOT_configure_regulators(SC301IOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) mutex_init(&SC301IOT->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) sd = &SC301IOT->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) v4l2_i2c_subdev_init(sd, client, &SC301IOT_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) ret = SC301IOT_initialize_controls(SC301IOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) ret = __SC301IOT_power_on(SC301IOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) ret = SC301IOT_check_sensor_id(SC301IOT, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) sd->internal_ops = &SC301IOT_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) SC301IOT->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) ret = media_entity_pads_init(&sd->entity, 1, &SC301IOT->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) if (strcmp(SC301IOT->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) SC301IOT->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) SC301IOT_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) __SC301IOT_power_off(SC301IOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) v4l2_ctrl_handler_free(&SC301IOT->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) mutex_destroy(&SC301IOT->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) static int SC301IOT_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) struct SC301IOT *SC301IOT = to_SC301IOT(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) v4l2_ctrl_handler_free(&SC301IOT->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) mutex_destroy(&SC301IOT->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) __SC301IOT_power_off(SC301IOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) static const struct of_device_id SC301IOT_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) { .compatible = "smartsens,SC301IOT" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) MODULE_DEVICE_TABLE(of, SC301IOT_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) static const struct i2c_device_id SC301IOT_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) { "smartsens,SC301IOT", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) static struct i2c_driver SC301IOT_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) .name = SC301IOT_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) .pm = &SC301IOT_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) .of_match_table = of_match_ptr(SC301IOT_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) .probe = &SC301IOT_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .remove = &SC301IOT_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .id_table = SC301IOT_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) return i2c_add_driver(&SC301IOT_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) i2c_del_driver(&SC301IOT_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) MODULE_DESCRIPTION("smartsens SC301IOT sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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