^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sc2310 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version,adjust sc2310.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X01 add set flip ctrl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X02 1.fixed time limit error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2.fixed gain conversion function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * 3.fixed test pattern error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * 4.add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) //#define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MIPI_FREQ_186M 186000000 //371.25Mbps/lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MIPI_FREQ_380M 380000000 //760Mbps/lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SC2310_MAX_PIXEL_RATE (MIPI_FREQ_380M * 2 / 10 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SC2310_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CHIP_ID 0x2311
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SC2310_REG_CHIP_ID 0x3107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC2310_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SC2310_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SC2310_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SC2310_EXPOSURE_MIN 2// two lines long exp min
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SC2310_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SC2310_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) //long exposure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SC2310_REG_EXP_LONG_H 0x3e00 //[3:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SC2310_REG_EXP_LONG_M 0x3e01 //[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SC2310_REG_EXP_LONG_L 0x3e02 //[7:4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) //short exposure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SC2310_REG_EXP_SF_H 0x3e04 //[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC2310_REG_EXP_SF_L 0x3e05 //[7:4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) //long frame and normal gain reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SC2310_REG_AGAIN 0x3e08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SC2310_REG_AGAIN_FINE 0x3e09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SC2310_REG_DGAIN 0x3e06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SC2310_REG_DGAIN_FINE 0x3e07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) //short fram gain reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SC2310_SF_REG_AGAIN 0x3e12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SC2310_SF_REG_AGAIN_FINE 0x3e13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SC2310_SF_REG_DGAIN 0x3e10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SC2310_SF_REG_DGAIN_FINE 0x3e11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SC2310_GAIN_MIN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SC2310_GAIN_MAX (44 * 32 * 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SC2310_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SC2310_GAIN_DEFAULT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) //group hold
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SC2310_GROUP_UPDATE_ADDRESS 0x3812
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SC2310_GROUP_UPDATE_START_DATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SC2310_GROUP_UPDATE_LAUNCH 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SC2310_SOFTWARE_RESET_REG 0x0103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SC2310_REG_TEST_PATTERN 0x4501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SC2310_TEST_PATTERN_ENABLE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SC2310_REG_VTS 0x320e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SC2310_FLIP_REG 0x3221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SC2310_FLIP_MASK 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SC2310_MIRROR_MASK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SC2310_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SC2310_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SC2310_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SC2310_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define LONG_FRAME_MAX_EXP 4297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SHORT_FRAME_MAX_EXP 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SC2310_NAME "sc2310"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static const char * const sc2310_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SC2310_NUM_SUPPLIES ARRAY_SIZE(sc2310_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct sc2310_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 mipi_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct sc2310 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct regulator_bulk_data supplies[SC2310_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct v4l2_fract cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const struct sc2310_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define to_sc2310(sd) container_of(sd, struct sc2310, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * Xclk 24Mhz linear 1920*1080 30fps 37.125Mbps/lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static const struct regval sc2310_linear10bit_1920x1080_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3001, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x3018, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x3019, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x301c, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x301f, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3031, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3037, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3038, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x303f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3200, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3201, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3202, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3203, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3204, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3205, 0x8b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3206, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3207, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3208, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3209, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x320a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x320b, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x320c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x320d, 0x4c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3210, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3211, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3212, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3213, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3301, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3302, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3303, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3306, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3308, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3309, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x330b, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x330e, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3314, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x331b, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x331e, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x331f, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3320, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3324, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3325, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3326, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3333, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x333d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3341, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3343, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3364, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x3366, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3367, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3368, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3369, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x336a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x336b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x336c, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x337f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x3380, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x33aa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x33b6, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x33b7, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x33b8, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x33b9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x33ba, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x33bb, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x33bc, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x33bd, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x33be, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x33bf, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x360f, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3621, 0xac},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3622, 0xe6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3623, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3624, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3630, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x3631, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3632, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3633, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3634, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x3635, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3636, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3637, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3638, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x363b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x363c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x363d, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x3640, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x366e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3670, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3671, 0xf6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x3672, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3673, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3674, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3675, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x3676, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x3677, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x3678, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x3679, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x367a, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x367b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x367c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x367d, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x367e, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x367f, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x3696, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x3697, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x3698, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x36a0, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x36a1, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x36ea, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x36eb, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x36ec, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x36ed, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x36fa, 0xf8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x36fb, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x3907, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x3908, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x391e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x391f, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3933, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x3934, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3940, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3941, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3942, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x3943, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x3e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x3e01, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x3e02, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x3e03, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x3e06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x3e07, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x3e08, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x3e09, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x3e0e, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x3e14, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x3e1e, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x3e25, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x3e26, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x3f00, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x3f04, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x3f05, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x3f08, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x4500, 0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x4501, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x4509, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x4603, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x4809, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x4837, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x5000, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x5780, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x5781, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x5782, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x5783, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x5784, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x5785, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x5786, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x5787, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x5788, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x57a0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x57a1, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x57a2, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x57a3, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x57a4, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x6000, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x6002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x36e9, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x36f9, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * Xclk 24Mhz hdr 2to1 STAGGER 1920*1080 30fps 760Mbps/lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static __maybe_unused const struct regval sc2310_hdr10bit_1920x1080_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) //{0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x303f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x36e9, 0xa6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x36f9, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x4509, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x337f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x3368, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x3369, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x336a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x336b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x3367, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x3326, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x3631, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x3018, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x3031, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x3001, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x4603, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x3640, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x3907, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x3908, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x3320, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x57a4, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x3333, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x331b, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x3334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x3302, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x36eb, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x36ec, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x3f08, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x4501, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x3309, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x331f, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x3308, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x3366, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x33aa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x391e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x391f, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x3634, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x4500, 0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x3623, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x3f00, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x336c, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x3933, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x3934, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x3940, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x3941, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x3942, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x3943, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x3624, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x3621, 0xac},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x3222, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x3901, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x363b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x363c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x363d, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x3324, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x3325, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x333d, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x3314, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x3e14, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x3e1e, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x3e0e, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x3364, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x33b6, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x33b7, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x33b8, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x33b9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x33ba, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x33bb, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x33bc, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x33bd, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x33be, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x33bf, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x360f, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x367a, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x367b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x3671, 0xf6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x3672, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x3673, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x366e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x367c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x367d, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x3674, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x3675, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x3676, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x367e, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x367f, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x3677, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x3678, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x3679, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x36a0, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x36a1, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x3696, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x3697, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x3698, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x301c, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x3037, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x3038, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x3632, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x4809, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x3625, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x3670, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x369e, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x369f, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x3693, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x3694, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x3695, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x5000, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x5780, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x57a0, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x57a1, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x57a2, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x57a3, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x5781, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x5782, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x5783, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x5784, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x5785, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x5786, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x5787, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x5788, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x3637, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x3638, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x3200, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x3201, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x3202, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x3203, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x3204, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x3205, 0x8b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x3206, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x3207, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x3208, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x3209, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x320a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x320b, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x3211, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x3213, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x3380, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x3341, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x3343, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x3e25, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x3e26, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x391d, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x36ea, 0x2d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x36ed, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x36fa, 0x6a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x36fb, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x320c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x320d, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x3636, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x3f04, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x3f05, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x4837, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x331e, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x3303, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x330b, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x3306, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x330e, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x4816, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x3220, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x4602, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x33c0, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x6000, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x6002, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x320e, 0x0a},//{0x320e, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x320f, 0x66},//{0x320f, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x3e00, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x3e01, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x3e02, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x3e04, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x3e05, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x3e23, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x3e24, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x3e03, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x3e06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x3e07, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x3e08, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x3e09, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x3622, 0xf6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x3633, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x3630, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x3301, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x363a, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x3635, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x36e9, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x36f9, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * The width and height must be configured to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * the same as the current output resolution of the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * The input width of the isp needs to be 16 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * The input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * If the width or height does not meet the alignment rules,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * you can configure the cropping parameters with the following function to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * crop out the appropriate resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * struct v4l2_subdev_pad_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * .get_selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static const struct sc2310_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* linear modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .exp_def = 0x048c / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .hts_def = 0x044c * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .vts_def = 0x0465,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .reg_list = sc2310_linear10bit_1920x1080_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* 2 to 1 hdr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) .exp_def = 0x103e / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .hts_def = 0x0476 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .vts_def = 0x0a66,//0x08aa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .reg_list = sc2310_hdr10bit_1920x1080_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static const s64 link_freq_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) MIPI_FREQ_186M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) MIPI_FREQ_380M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const char * const sc2310_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) "Vertical Color Bar Type 1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int sc2310_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) static int sc2310_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ret |= sc2310_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) SC2310_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static int sc2310_read_reg(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static int sc2310_get_reso_dist(const struct sc2310_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static const struct sc2310_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) sc2310_find_best_fit(struct sc2310 *sc2310, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) for (i = 0; i < sc2310->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dist = sc2310_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) (supported_modes[i].bus_fmt == framefmt->code)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static void sc2310_change_mode(struct sc2310 *sc2310, const struct sc2310_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) sc2310->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) sc2310->cur_vts = sc2310->cur_mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dev_info(&sc2310->client->dev, "set fmt: cur_mode: %dx%d, hdr: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) mode->width, mode->height, mode->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static int sc2310_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct sc2310 *sc2310 = to_sc2310(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) const struct sc2310_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) mutex_lock(&sc2310->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) mode = sc2310_find_best_fit(sc2310, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) mutex_unlock(&sc2310->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) sc2310_change_mode(sc2310, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) __v4l2_ctrl_modify_range(sc2310->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) __v4l2_ctrl_modify_range(sc2310->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) SC2310_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) __v4l2_ctrl_s_ctrl(sc2310->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) mode->bpp * 2 * SC2310_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) __v4l2_ctrl_s_ctrl_int64(sc2310->pixel_rate, pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) sc2310->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) sc2310->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) mutex_unlock(&sc2310->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int sc2310_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct sc2310 *sc2310 = to_sc2310(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) const struct sc2310_mode *mode = sc2310->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) mutex_lock(&sc2310->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) mutex_unlock(&sc2310->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) mutex_unlock(&sc2310->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int sc2310_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct sc2310 *sc2310 = to_sc2310(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) code->code = sc2310->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int sc2310_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct sc2310 *sc2310 = to_sc2310(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (fse->index >= sc2310->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (fse->code != supported_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static int sc2310_enable_test_pattern(struct sc2310 *sc2310, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ret = sc2310_read_reg(sc2310->client, SC2310_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) SC2310_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) val |= SC2310_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) val &= ~SC2310_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ret |= sc2310_write_reg(sc2310->client, SC2310_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) SC2310_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static int sc2310_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct sc2310 *sc2310 = to_sc2310(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) const struct sc2310_mode *mode = sc2310->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (sc2310->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) fi->interval = sc2310->cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static int sc2310_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct sc2310 *sc2310 = to_sc2310(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) const struct sc2310_mode *mode = sc2310->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) val = 1 << (SC2310_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) val = 1 << (SC2310_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) static void sc2310_get_module_inf(struct sc2310 *sc2310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) strlcpy(inf->base.sensor, SC2310_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) strlcpy(inf->base.module, sc2310->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) strlcpy(inf->base.lens, sc2310->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static void sc2310_get_gain_reg(u32 val, u32 *again_reg, u32 *again_fine_reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) u32 *dgain_reg, u32 *dgain_fine_reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) u8 u8Reg0x3e09 = 0x40, u8Reg0x3e08 = 0x03, u8Reg0x3e07 = 0x80, u8Reg0x3e06 = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) u32 aCoarseGain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) u32 aFineGain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) u32 dCoarseGain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) u32 dFineGain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) u32 again = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) u32 dgain = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (val <= 2764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) again = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) dgain = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) again = 2764;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) dgain = val * 128 / again;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) //again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (again <= 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) //a_gain < 2.72x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) for (aCoarseGain = 1; aCoarseGain <= 2; aCoarseGain = aCoarseGain * 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) //1,2,4,8,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (again < (64 * 2 * aCoarseGain))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) aFineGain = again / aCoarseGain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) for (aCoarseGain = 1; aCoarseGain <= 8; aCoarseGain = aCoarseGain * 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) //1,2,4,8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (again < (64 * 2 * aCoarseGain * 272 / 100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) aFineGain = 100 * again / aCoarseGain / 272;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) for ( ; aCoarseGain >= 2; aCoarseGain = aCoarseGain / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) u8Reg0x3e08 = (u8Reg0x3e08 << 1) | 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) u8Reg0x3e09 = aFineGain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) //dcg = 2.72 --> 2.72*1024=2785.28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) u8Reg0x3e08 = (again > 174) ? (u8Reg0x3e08 | 0x20) : (u8Reg0x3e08 & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) //------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) //dgain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) for (dCoarseGain = 1; dCoarseGain <= 16; dCoarseGain = dCoarseGain * 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) //1,2,4,8,16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (dgain < (256 * dCoarseGain))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dFineGain = dgain / dCoarseGain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) for ( ; dCoarseGain >= 2; dCoarseGain = dCoarseGain / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) u8Reg0x3e06 = (u8Reg0x3e06 << 1) | 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) u8Reg0x3e07 = dFineGain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) *again_reg = u8Reg0x3e08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) *again_fine_reg = u8Reg0x3e09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) *dgain_reg = u8Reg0x3e06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) *dgain_fine_reg = u8Reg0x3e07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static int sc2310_set_hdrae(struct sc2310 *sc2310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct i2c_client *client = sc2310->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) u32 l_a_gain, m_a_gain, s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) u32 l_again, l_again_fine, l_dgain, l_dgain_fine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) u32 s_again, s_again_fine, s_dgain, s_dgain_fine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (!sc2310->has_init_exp && !sc2310->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) sc2310->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) sc2310->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) dev_dbg(&client->dev, "sc2310 is not streaming, save hdr ae!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) l_a_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) m_a_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) s_a_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) dev_dbg(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) l_exp_time, m_exp_time, s_exp_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) l_a_gain, m_a_gain, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (sc2310->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) l_a_gain = m_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) l_exp_time = m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) sc2310_get_gain_reg(l_a_gain, &l_again, &l_again_fine, &l_dgain, &l_dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) sc2310_get_gain_reg(s_a_gain, &s_again, &s_again_fine, &s_dgain, &s_dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) l_exp_time = l_exp_time << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) s_exp_time = s_exp_time << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (l_exp_time > LONG_FRAME_MAX_EXP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) l_exp_time = LONG_FRAME_MAX_EXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (s_exp_time > SHORT_FRAME_MAX_EXP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) s_exp_time = SHORT_FRAME_MAX_EXP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) SC2310_REG_EXP_LONG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) (l_exp_time << 4 & 0XF0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) SC2310_REG_EXP_LONG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) (l_exp_time >> 4 & 0XFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) SC2310_REG_EXP_LONG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) (l_exp_time >> 12 & 0X0F));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) SC2310_REG_AGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) l_again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) SC2310_REG_AGAIN_FINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) l_again_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) SC2310_REG_DGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) l_dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) SC2310_REG_DGAIN_FINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) l_dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) SC2310_REG_EXP_SF_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) (s_exp_time << 4 & 0XF0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) SC2310_REG_EXP_SF_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) (s_exp_time >> 4 & 0XFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) SC2310_SF_REG_AGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) s_again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) SC2310_SF_REG_AGAIN_FINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) s_again_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) SC2310_SF_REG_DGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) s_dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) SC2310_SF_REG_DGAIN_FINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) s_dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static int sc2310_get_channel_info(struct sc2310 *sc2310, struct rkmodule_channel_info *ch_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ch_info->vc = sc2310->cur_mode->vc[ch_info->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ch_info->width = sc2310->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ch_info->height = sc2310->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ch_info->bus_fmt = sc2310->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static long sc2310_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct sc2310 *sc2310 = to_sc2310(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct rkmodule_hdr_cfg *hdr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) const struct sc2310_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) u32 i, h, w, stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) ret = sc2310_set_hdrae(sc2310, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (sc2310->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) ret = sc2310_write_array(sc2310->client, sc2310->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) w = sc2310->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) h = sc2310->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) for (i = 0; i < sc2310->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) supported_modes[i].hdr_mode == hdr_cfg->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) sc2310_change_mode(sc2310, &supported_modes[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (i == sc2310->cfg_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) dev_err(&sc2310->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) hdr_cfg->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) mode = sc2310->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) w = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) h = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) __v4l2_ctrl_modify_range(sc2310->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) __v4l2_ctrl_modify_range(sc2310->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) SC2310_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) __v4l2_ctrl_s_ctrl(sc2310->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) mode->bpp * 2 * SC2310_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) __v4l2_ctrl_s_ctrl_int64(sc2310->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) sc2310->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) sc2310->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) dev_info(&sc2310->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) "sensor mode: %d\n", mode->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) sc2310_get_module_inf(sc2310, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) hdr_cfg->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) hdr_cfg->hdr_mode = sc2310->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ret = sc2310_write_reg(sc2310->client, SC2310_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) SC2310_REG_VALUE_08BIT, SC2310_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ret = sc2310_write_reg(sc2310->client, SC2310_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) SC2310_REG_VALUE_08BIT, SC2310_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ch_info = (struct rkmodule_channel_info *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ret = sc2310_get_channel_info(sc2310, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) static long sc2310_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) u32 cg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ret = sc2310_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (copy_to_user(up, inf, sizeof(*inf))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (copy_from_user(cfg, up, sizeof(*cfg))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ret = sc2310_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) ret = sc2310_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (copy_to_user(up, hdr, sizeof(*hdr))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if (copy_from_user(hdr, up, sizeof(*hdr))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ret = sc2310_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (copy_from_user(hdrae, up, sizeof(*hdrae))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) ret = sc2310_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) case RKMODULE_SET_CONVERSION_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (copy_from_user(&cg, up, sizeof(cg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ret = sc2310_ioctl(sd, cmd, &cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (copy_from_user(&stream, up, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) ret = sc2310_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (!ch_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) ret = sc2310_ioctl(sd, cmd, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ret = copy_to_user(up, ch_info, sizeof(*ch_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) kfree(ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static int __sc2310_start_stream(struct sc2310 *sc2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ret = sc2310_write_array(sc2310->client, sc2310->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) ret = __v4l2_ctrl_handler_setup(&sc2310->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (sc2310->has_init_exp && sc2310->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ret = sc2310_ioctl(&sc2310->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) &sc2310->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) dev_err(&sc2310->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) return sc2310_write_reg(sc2310->client, SC2310_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) SC2310_REG_VALUE_08BIT, SC2310_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) static int __sc2310_stop_stream(struct sc2310 *sc2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) sc2310->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return sc2310_write_reg(sc2310->client, SC2310_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) SC2310_REG_VALUE_08BIT, SC2310_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static int sc2310_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) struct sc2310 *sc2310 = to_sc2310(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct i2c_client *client = sc2310->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) mutex_lock(&sc2310->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (on == sc2310->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) ret = __sc2310_start_stream(sc2310);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) __sc2310_stop_stream(sc2310);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) sc2310->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) mutex_unlock(&sc2310->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) static int sc2310_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) struct sc2310 *sc2310 = to_sc2310(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) struct i2c_client *client = sc2310->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) mutex_lock(&sc2310->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (sc2310->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) SC2310_SOFTWARE_RESET_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) 0x303f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) sc2310->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) sc2310->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) mutex_unlock(&sc2310->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) static int __sc2310_power_on(struct sc2310 *sc2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) struct device *dev = &sc2310->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (!IS_ERR_OR_NULL(sc2310->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) ret = pinctrl_select_state(sc2310->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) sc2310->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) ret = clk_set_rate(sc2310->xvclk, SC2310_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (clk_get_rate(sc2310->xvclk) != SC2310_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) ret = clk_prepare_enable(sc2310->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (!IS_ERR(sc2310->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) gpiod_set_value_cansleep(sc2310->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) ret = regulator_bulk_enable(SC2310_NUM_SUPPLIES, sc2310->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (!IS_ERR(sc2310->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) gpiod_set_value_cansleep(sc2310->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) if (!IS_ERR(sc2310->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) gpiod_set_value_cansleep(sc2310->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) usleep_range(2000, 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) clk_disable_unprepare(sc2310->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) static void __sc2310_power_off(struct sc2310 *sc2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) struct device *dev = &sc2310->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (!IS_ERR(sc2310->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) gpiod_set_value_cansleep(sc2310->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) clk_disable_unprepare(sc2310->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (!IS_ERR(sc2310->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) gpiod_set_value_cansleep(sc2310->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (!IS_ERR_OR_NULL(sc2310->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ret = pinctrl_select_state(sc2310->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) sc2310->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) regulator_bulk_disable(SC2310_NUM_SUPPLIES, sc2310->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) static int sc2310_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) struct sc2310 *sc2310 = to_sc2310(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) return __sc2310_power_on(sc2310);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) static int sc2310_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) struct sc2310 *sc2310 = to_sc2310(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) __sc2310_power_off(sc2310);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) static int sc2310_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) struct sc2310 *sc2310 = to_sc2310(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) const struct sc2310_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) mutex_lock(&sc2310->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) mutex_unlock(&sc2310->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) static int sc2310_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) struct sc2310 *sc2310 = to_sc2310(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (fie->index >= sc2310->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) static const struct dev_pm_ops sc2310_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) SET_RUNTIME_PM_OPS(sc2310_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) sc2310_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static const struct v4l2_subdev_internal_ops sc2310_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .open = sc2310_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) static const struct v4l2_subdev_core_ops sc2310_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .s_power = sc2310_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .ioctl = sc2310_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .compat_ioctl32 = sc2310_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) static const struct v4l2_subdev_video_ops sc2310_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .s_stream = sc2310_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .g_frame_interval = sc2310_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static const struct v4l2_subdev_pad_ops sc2310_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .enum_mbus_code = sc2310_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .enum_frame_size = sc2310_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .enum_frame_interval = sc2310_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .get_fmt = sc2310_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .set_fmt = sc2310_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .get_mbus_config = sc2310_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) static const struct v4l2_subdev_ops sc2310_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .core = &sc2310_core_ops, /* v4l2_subdev_core_ops sc2310_core_ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .video = &sc2310_video_ops, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .pad = &sc2310_pad_ops, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) static void sc2310_modify_fps_info(struct sc2310 *sc2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) const struct sc2310_mode *mode = sc2310->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) sc2310->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) sc2310->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) static int sc2310_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) struct sc2310 *sc2310 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) struct sc2310, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) struct i2c_client *client = sc2310->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) u32 again, again_fine, dgain, dgain_fine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) max = sc2310->cur_mode->height + ctrl->val - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) __v4l2_ctrl_modify_range(sc2310->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) sc2310->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) sc2310->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) sc2310->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) if (sc2310->cur_mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) goto out_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) val = ctrl->val << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) ret = sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) SC2310_REG_EXP_LONG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) (val << 4 & 0XF0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) SC2310_REG_EXP_LONG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) (val >> 4 & 0XFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) SC2310_REG_EXP_LONG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) (val >> 12 & 0X0F));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) dev_dbg(&client->dev, "set exposure 0x%x\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (sc2310->cur_mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) goto out_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) sc2310_get_gain_reg(ctrl->val, &again, &again_fine, &dgain, &dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) dev_dbg(&client->dev, "recv:%d set again 0x%x, again_fine 0x%x, set dgain 0x%x, dgain_fine 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) ctrl->val, again, again_fine, dgain, dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) SC2310_REG_AGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) SC2310_REG_AGAIN_FINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) again_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) SC2310_REG_DGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) ret |= sc2310_write_reg(sc2310->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) SC2310_REG_DGAIN_FINE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) SC2310_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) ret = sc2310_write_reg(sc2310->client, SC2310_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) SC2310_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) ctrl->val + sc2310->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) sc2310->cur_vts = ctrl->val + sc2310->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (sc2310->cur_vts != sc2310->cur_mode->vts_def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) sc2310_modify_fps_info(sc2310);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) dev_dbg(&client->dev, "set vblank 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) ret = sc2310_enable_test_pattern(sc2310, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) ret = sc2310_read_reg(sc2310->client, SC2310_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) SC2310_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) val |= SC2310_MIRROR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) val &= ~SC2310_MIRROR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) ret |= sc2310_write_reg(sc2310->client, SC2310_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) SC2310_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) ret = sc2310_read_reg(sc2310->client, SC2310_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) SC2310_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) val |= SC2310_FLIP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) val &= ~SC2310_FLIP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) ret |= sc2310_write_reg(sc2310->client, SC2310_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) SC2310_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) out_ctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) static const struct v4l2_ctrl_ops sc2310_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .s_ctrl = sc2310_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) static int sc2310_initialize_controls(struct sc2310 *sc2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) const struct sc2310_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) handler = &sc2310->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) mode = sc2310->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) handler->lock = &sc2310->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) sc2310->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) ARRAY_SIZE(link_freq_items) - 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) link_freq_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) __v4l2_ctrl_s_ctrl(sc2310->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * SC2310_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) sc2310->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) V4L2_CID_PIXEL_RATE, 0, SC2310_MAX_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) 1, pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) sc2310->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) if (sc2310->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) sc2310->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) sc2310->vblank = v4l2_ctrl_new_std(handler, &sc2310_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) SC2310_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) exposure_max = mode->vts_def - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) sc2310->exposure = v4l2_ctrl_new_std(handler, &sc2310_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) V4L2_CID_EXPOSURE, SC2310_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) exposure_max, SC2310_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) sc2310->anal_gain = v4l2_ctrl_new_std(handler, &sc2310_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) V4L2_CID_ANALOGUE_GAIN, SC2310_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) SC2310_GAIN_MAX, SC2310_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) SC2310_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) sc2310->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) &sc2310_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) ARRAY_SIZE(sc2310_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) 0, 0, sc2310_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) v4l2_ctrl_new_std(handler, &sc2310_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) v4l2_ctrl_new_std(handler, &sc2310_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) dev_err(&sc2310->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) sc2310->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) sc2310->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) sc2310->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) sc2310->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static int sc2310_check_sensor_id(struct sc2310 *sc2310,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) struct device *dev = &sc2310->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) ret = sc2310_read_reg(client, SC2310_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) SC2310_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) dev_info(dev, "Detected SC%04x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) static int sc2310_configure_regulators(struct sc2310 *sc2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) for (i = 0; i < SC2310_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) sc2310->supplies[i].supply = sc2310_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) return devm_regulator_bulk_get(&sc2310->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) SC2310_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) sc2310->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) static int sc2310_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) struct sc2310 *sc2310;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) sc2310 = devm_kzalloc(dev, sizeof(*sc2310), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) if (!sc2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) &sc2310->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) &sc2310->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) &sc2310->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) &sc2310->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) hdr_mode = NO_HDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) dev_warn(dev, " Get hdr mode failed! no hdr default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) sc2310->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) for (i = 0; i < sc2310->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) sc2310->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) sc2310->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) sc2310->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) if (IS_ERR(sc2310->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) sc2310->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (IS_ERR(sc2310->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) sc2310->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (IS_ERR(sc2310->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) sc2310->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) if (!IS_ERR(sc2310->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) sc2310->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) pinctrl_lookup_state(sc2310->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) if (IS_ERR(sc2310->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) sc2310->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) pinctrl_lookup_state(sc2310->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if (IS_ERR(sc2310->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) ret = sc2310_configure_regulators(sc2310);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) mutex_init(&sc2310->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) sd = &sc2310->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) v4l2_i2c_subdev_init(sd, client, &sc2310_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) ret = sc2310_initialize_controls(sc2310);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) ret = __sc2310_power_on(sc2310);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) ret = sc2310_check_sensor_id(sc2310, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) sd->internal_ops = &sc2310_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) sc2310->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) ret = media_entity_pads_init(&sd->entity, 1, &sc2310->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) if (strcmp(sc2310->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) sc2310->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) SC2310_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) #ifdef USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) add_sysfs_interfaces(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) __sc2310_power_off(sc2310);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) v4l2_ctrl_handler_free(&sc2310->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) mutex_destroy(&sc2310->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) static int sc2310_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) struct sc2310 *sc2310 = to_sc2310(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) v4l2_ctrl_handler_free(&sc2310->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) mutex_destroy(&sc2310->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) __sc2310_power_off(sc2310);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) static const struct of_device_id sc2310_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) { .compatible = "smartsens,sc2310" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) MODULE_DEVICE_TABLE(of, sc2310_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) static const struct i2c_device_id sc2310_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) { "smartsens,sc2310", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) static struct i2c_driver sc2310_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) .name = SC2310_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) .pm = &sc2310_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) .of_match_table = of_match_ptr(sc2310_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) .probe = &sc2310_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) .remove = &sc2310_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) .id_table = sc2310_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) module_i2c_driver(sc2310_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) return i2c_add_driver(&sc2310_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) i2c_del_driver(&sc2310_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) MODULE_DESCRIPTION("Smartsens sc2310 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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