^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sc230ai driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) //#define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "../platform/rockchip/isp/rkisp_tb_helper.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SC230AI_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SC230AI_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SC230AI_LINK_FREQ_185 92812500// 185.625Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SC230AI_LINK_FREQ_371 185625000// 371.25Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PIXEL_RATE_WITH_185M_10BIT (SC230AI_LINK_FREQ_185 * 2 * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) SC230AI_LANES / SC230AI_BITS_PER_SAMPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PIXEL_RATE_WITH_371M_10BIT (SC230AI_LINK_FREQ_371 * 2 * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) SC230AI_LANES / SC230AI_BITS_PER_SAMPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SC230AI_XVCLK_FREQ 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CHIP_ID 0xcb34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SC230AI_REG_CHIP_ID 0x3107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC230AI_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SC230AI_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SC230AI_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SC230AI_REG_EXPOSURE_H 0x3e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SC230AI_REG_EXPOSURE_M 0x3e01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SC230AI_REG_EXPOSURE_L 0x3e02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SC230AI_REG_SEXPOSURE_H 0x3e22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SC230AI_REG_SEXPOSURE_M 0x3e04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SC230AI_REG_SEXPOSURE_L 0x3e05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SC230AI_EXPOSURE_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SC230AI_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SC230AI_EXPOSURE_LIN_MAX (2 * 0x465 - 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SC230AI_EXPOSURE_HDR_MAX_S (2 * 0x465 - 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SC230AI_EXPOSURE_HDR_MAX_L (2 * 0x465 - 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC230AI_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SC230AI_REG_DIG_GAIN 0x3e06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SC230AI_REG_DIG_FINE_GAIN 0x3e07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SC230AI_REG_ANA_GAIN 0x3e09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SC230AI_REG_SDIG_GAIN 0x3e10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SC230AI_REG_SDIG_FINE_GAIN 0x3e11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SC230AI_REG_SANA_GAIN 0x3e12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SC230AI_REG_SANA_FINE_GAIN 0x3e13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SC230AI_GAIN_MIN 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SC230AI_GAIN_MAX 1722628 //108.512*15.875*1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SC230AI_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SC230AI_GAIN_DEFAULT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SC230AI_LGAIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SC230AI_SGAIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SC230AI_REG_GROUP_HOLD 0x3812
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SC230AI_GROUP_HOLD_START 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SC230AI_GROUP_HOLD_END 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SC230AI_REG_HIGH_TEMP_H 0x3974
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SC230AI_REG_HIGH_TEMP_L 0x3975
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SC230AI_REG_TEST_PATTERN 0x4501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SC230AI_TEST_PATTERN_BIT_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SC230AI_REG_VTS_H 0x320e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SC230AI_REG_VTS_L 0x320f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SC230AI_FLIP_MIRROR_REG 0x3221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SC230AI_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SC230AI_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SC230AI_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SC230AI_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SC230AI_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SC230AI_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SC230AI_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define REG_DELAY 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SC230AI_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SC230AI_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SC230AI_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SC230AI_NAME "sc230ai"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const char * const sc230ai_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SC230AI_NUM_SUPPLIES ARRAY_SIZE(sc230ai_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct sc230ai_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 mipi_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct sc230ai {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct regulator_bulk_data supplies[SC230AI_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct v4l2_fract cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) const struct sc230ai_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) bool is_thunderboot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) bool is_first_streamoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define to_sc230ai(sd) container_of(sd, struct sc230ai, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * Xclk 27Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static const struct regval sc230ai_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const struct regval sc230ai_linear_10_640x480_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x37f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x301f, 0x2d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3200, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3201, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3202, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3203, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3204, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3205, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3206, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3207, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3208, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3209, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x320a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x320b, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x320e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x320f, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3210, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3211, 0xa2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3212, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3213, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3215, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3220, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3301, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3304, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3306, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3308, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3309, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x330b, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x331e, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x331f, 0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3333, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x335d, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x335e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x335f, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3364, 0x5e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x337c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x337d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3390, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x3391, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3392, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3393, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3394, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3395, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3396, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3397, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x3398, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x3399, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x339a, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x339b, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x339c, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x33a2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x33af, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x33b1, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x33b3, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x33b9, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x33f9, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x33fb, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x33fc, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x33fd, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x349f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x34a6, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x34a7, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x34a8, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x34a9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x34aa, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x34ab, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x34ac, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x34ad, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x34f8, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x34f9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3630, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3633, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x3637, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x363b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3670, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x3674, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x3675, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3676, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x367c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x367d, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3690, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3691, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3692, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x369c, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x369d, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x36ae, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x36af, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x36b0, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x36b1, 0x9b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x36b2, 0xb7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x36d0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x36ea, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x36eb, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x36ec, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x36ed, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x370f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3722, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x3728, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x37b0, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x37b1, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x37b2, 0x97},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x37b3, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x37b4, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x37fa, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x37fb, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x37fc, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x37fd, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x3901, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x3902, 0xc5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3904, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x3907, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3908, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3909, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x390a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x391f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x3933, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x3934, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x3940, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x3941, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x3942, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x3943, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x3e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x3e01, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x3e02, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x440e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x450d, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x4819, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x481b, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x481d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x481f, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x4821, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x4823, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x4825, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x4827, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x4829, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x5000, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x5010, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x5787, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x5788, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x5789, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x578a, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x578b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x578c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x5790, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x5791, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x5792, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x5793, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x5794, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x5795, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x5799, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x57ad, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x5900, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x5901, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x5ae0, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x5ae1, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x5ae2, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x5ae3, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x5ae4, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x5ae5, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x5ae6, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x5ae7, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x5ae8, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x5ae9, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x5aea, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x5aeb, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x5aec, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x5aed, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x5af4, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x5af5, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x5af6, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x5af7, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x5af8, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x5af9, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x5afa, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x5afb, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x5afc, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x5afd, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x5afe, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x5aff, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x36e9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x37f9, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Xclk 27Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * max_framerate 25fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * mipi_datarate per lane 371.25Mbps, 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct regval sc230ai_linear_10_1920x1080_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x37f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x301f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x320e, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x320f, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x3301, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x3304, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x3306, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x3308, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x3309, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x330a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x330b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x3314, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x331e, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x331f, 0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x3333, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x3334, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x335d, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x335e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x335f, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x3364, 0x5e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x337c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x337d, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x3390, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x3391, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x3392, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x3393, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x3394, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x3395, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x3396, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x3397, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x3398, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x3399, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x339a, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x339b, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x339c, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x33a2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x33ad, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x33af, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x33b1, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x33b3, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x33b9, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x33f9, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x33fb, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x33fc, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x33fd, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x349f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x34a6, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x34a7, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x34a8, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x34a9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x34aa, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x34ab, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x34ac, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x34ad, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x34f8, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x34f9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x3630, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x3632, 0x54},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x3633, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x363b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x363c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x3670, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x3674, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x3675, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x3676, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x367c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x367d, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x3690, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x3691, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x3692, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x369c, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x369d, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x36ae, 0x4b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x36af, 0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x36b0, 0x87},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x36b1, 0x9b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x36b2, 0xb7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x36d0, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x3722, 0x97},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x3724, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x3728, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x3901, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x3902, 0xc5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x3904, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x3907, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x3908, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x3909, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x390a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x3933, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x3934, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x3940, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x3941, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x3942, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x3943, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x3e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x3e01, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x3e02, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x440e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x450d, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x5010, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x5787, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x5788, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x5789, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x578a, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x578b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x578c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x5790, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x5791, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x5792, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x5793, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x5794, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x5795, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x5799, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x57ad, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x5ae0, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x5ae1, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x5ae2, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x5ae3, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x5ae4, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x5ae5, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x5ae6, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x5ae7, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x5ae8, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x5ae9, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x5aea, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x5aeb, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x5aec, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x5aed, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x5af4, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x5af5, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x5af6, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x5af7, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x5af8, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x5af9, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x5afa, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x5afb, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x5afc, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x5afd, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x5afe, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x5aff, 0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x36e9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x37f9, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) //{0x0100, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static const struct sc230ai_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .denominator = 250000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .exp_def = 0x0460,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .hts_def = 0x44C * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .vts_def = 0x0546,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .reg_list = sc230ai_linear_10_1920x1080_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .denominator = 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .exp_def = 0x0232 - 9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .hts_def = 0x96 * 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .vts_def = 0x0232,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .reg_list = sc230ai_linear_10_640x480_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) .mipi_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) SC230AI_LINK_FREQ_185,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) SC230AI_LINK_FREQ_371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static const char * const sc230ai_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int sc230ai_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int sc230ai_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ret = sc230ai_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) SC230AI_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int sc230ai_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static int sc230ai_get_gain_reg(struct sc230ai *sc230ai, u32 *again, u32 *dgain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) u32 *dgain_fine, u32 total_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (total_gain < SC230AI_GAIN_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) total_gain = SC230AI_GAIN_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) else if (total_gain > SC230AI_GAIN_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) total_gain = SC230AI_GAIN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (total_gain < 2000) { /* 1 ~ 2 gain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) *again = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) *dgain_fine = total_gain * 128 / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) } else if (total_gain < 3391) { /* 2 ~ 3.391 gain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) *again = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) *dgain_fine = total_gain * 128 / 1000 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) } else if (total_gain < 3391 * 2) { /* 3.391 ~ 6.782 gain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) *again = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) *dgain_fine = total_gain * 128 / 3391;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) } else if (total_gain < 3391 * 4) { /* 6.782 ~ 13.564 gain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) *again = 0x48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) *dgain_fine = total_gain * 128 / 3391 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) } else if (total_gain < 3391 * 8) { /* 13.564 ~ 27.128 gain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) *again = 0x49;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) *dgain_fine = total_gain * 128 / 3391 / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) } else if (total_gain < 3391 * 16) { /* 27.128 ~ 54.256 gain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) *again = 0x4b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) *dgain_fine = total_gain * 128 / 3391 / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) } else if (total_gain < 3391 * 32) { /* 54.256 ~ 108.512 gain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) *again = 0x4f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) *dgain_fine = total_gain * 128 / 3391 / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) } else if (total_gain < 3391 * 64) { /* 108.512 ~ 217.024 gain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) *again = 0x5f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) *dgain = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) *dgain_fine = total_gain * 128 / 3391 / 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) } else if (total_gain < 3391 * 128) { /* 217.024 ~ 434.048 gain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) *again = 0x5f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) *dgain = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) *dgain_fine = total_gain * 128 / 3391 / 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) } else if (total_gain < 3391 * 256) { /* 434.048 ~ 868.096 gain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) *again = 0x5f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) *dgain = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) *dgain_fine = total_gain * 128 / 3391 / 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) } else if (total_gain < 3391 * 512) { /* 868.096 ~ 1736.192 gain*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) *again = 0x5f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) *dgain = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) *dgain_fine = total_gain * 128 / 3391 / 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static int sc230ai_set_hdrae(struct sc230ai *sc230ai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static int sc230ai_get_reso_dist(const struct sc230ai_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static const struct sc230ai_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) sc230ai_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) dist = sc230ai_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static int sc230ai_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct sc230ai *sc230ai = to_sc230ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) const struct sc230ai_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) mutex_lock(&sc230ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) mode = sc230ai_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) mutex_unlock(&sc230ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) sc230ai->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) __v4l2_ctrl_modify_range(sc230ai->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) __v4l2_ctrl_modify_range(sc230ai->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) SC230AI_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) __v4l2_ctrl_s_ctrl(sc230ai->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) pixel_rate = (u32)link_freq_menu_items[mode->mipi_freq_idx] /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) mode->bpp * 2 * SC230AI_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) __v4l2_ctrl_s_ctrl_int64(sc230ai->pixel_rate, pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) sc230ai->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) mutex_unlock(&sc230ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static int sc230ai_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct sc230ai *sc230ai = to_sc230ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) const struct sc230ai_mode *mode = sc230ai->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) mutex_lock(&sc230ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) mutex_unlock(&sc230ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* format info: width/height/data type/virctual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) mutex_unlock(&sc230ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int sc230ai_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct sc230ai *sc230ai = to_sc230ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) code->code = sc230ai->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) static int sc230ai_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (fse->code != supported_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static int sc230ai_enable_test_pattern(struct sc230ai *sc230ai, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = sc230ai_read_reg(sc230ai->client, SC230AI_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) SC230AI_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) val |= SC230AI_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) val &= ~SC230AI_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ret |= sc230ai_write_reg(sc230ai->client, SC230AI_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) SC230AI_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static int sc230ai_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct sc230ai *sc230ai = to_sc230ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) const struct sc230ai_mode *mode = sc230ai->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (sc230ai->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) fi->interval = sc230ai->cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) static int sc230ai_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct sc230ai *sc230ai = to_sc230ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) const struct sc230ai_mode *mode = sc230ai->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) u32 val = 1 << (SC230AI_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) val |= V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) val |= V4L2_MBUS_CSI2_CHANNEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static void sc230ai_get_module_inf(struct sc230ai *sc230ai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) strscpy(inf->base.sensor, SC230AI_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) strscpy(inf->base.module, sc230ai->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) strscpy(inf->base.lens, sc230ai->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static long sc230ai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct sc230ai *sc230ai = to_sc230ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) sc230ai_get_module_inf(sc230ai, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) hdr->hdr_mode = sc230ai->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) w = sc230ai->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) h = sc230ai->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) sc230ai->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (i == ARRAY_SIZE(supported_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dev_err(&sc230ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) w = sc230ai->cur_mode->hts_def - sc230ai->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) h = sc230ai->cur_mode->vts_def - sc230ai->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) __v4l2_ctrl_modify_range(sc230ai->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) __v4l2_ctrl_modify_range(sc230ai->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) SC230AI_VTS_MAX - sc230ai->cur_mode->height, 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) sc230ai->cur_fps = sc230ai->cur_mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) sc230ai_set_hdrae(sc230ai, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ret = sc230ai_write_reg(sc230ai->client, SC230AI_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) SC230AI_REG_VALUE_08BIT, SC230AI_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ret = sc230ai_write_reg(sc230ai->client, SC230AI_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) SC230AI_REG_VALUE_08BIT, SC230AI_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static long sc230ai_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ret = sc230ai_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ret = sc230ai_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (copy_from_user(hdr, up, sizeof(*hdr))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ret = sc230ai_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (copy_from_user(hdrae, up, sizeof(*hdrae))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ret = sc230ai_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (copy_from_user(&stream, up, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) ret = sc230ai_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static int __sc230ai_start_stream(struct sc230ai *sc230ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (!sc230ai->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) ret = sc230ai_write_array(sc230ai->client, sc230ai->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) ret = __v4l2_ctrl_handler_setup(&sc230ai->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (sc230ai->has_init_exp && sc230ai->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ret = sc230ai_ioctl(&sc230ai->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) &sc230ai->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) dev_err(&sc230ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return sc230ai_write_reg(sc230ai->client, SC230AI_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) SC230AI_REG_VALUE_08BIT, SC230AI_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) static int __sc230ai_stop_stream(struct sc230ai *sc230ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) sc230ai->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (sc230ai->is_thunderboot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) sc230ai->is_first_streamoff = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return sc230ai_write_reg(sc230ai->client, SC230AI_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) SC230AI_REG_VALUE_08BIT, SC230AI_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static int __sc230ai_power_on(struct sc230ai *sc230ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static int sc230ai_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct sc230ai *sc230ai = to_sc230ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct i2c_client *client = sc230ai->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) mutex_lock(&sc230ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (on == sc230ai->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (sc230ai->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) sc230ai->is_thunderboot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) __sc230ai_power_on(sc230ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ret = __sc230ai_start_stream(sc230ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) __sc230ai_stop_stream(sc230ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) sc230ai->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) mutex_unlock(&sc230ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) static int sc230ai_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct sc230ai *sc230ai = to_sc230ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct i2c_client *client = sc230ai->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) mutex_lock(&sc230ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (sc230ai->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (!sc230ai->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) ret = sc230ai_write_array(sc230ai->client, sc230ai_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) sc230ai->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) sc230ai->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) mutex_unlock(&sc230ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) static inline u32 sc230ai_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) return DIV_ROUND_UP(cycles, SC230AI_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static int __sc230ai_power_on(struct sc230ai *sc230ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) struct device *dev = &sc230ai->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (!IS_ERR_OR_NULL(sc230ai->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) ret = pinctrl_select_state(sc230ai->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) sc230ai->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) ret = clk_set_rate(sc230ai->xvclk, SC230AI_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (clk_get_rate(sc230ai->xvclk) != SC230AI_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) ret = clk_prepare_enable(sc230ai->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (sc230ai->is_thunderboot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (!IS_ERR(sc230ai->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) gpiod_set_value_cansleep(sc230ai->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ret = regulator_bulk_enable(SC230AI_NUM_SUPPLIES, sc230ai->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (!IS_ERR(sc230ai->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) gpiod_set_value_cansleep(sc230ai->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (!IS_ERR(sc230ai->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) gpiod_set_value_cansleep(sc230ai->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (!IS_ERR(sc230ai->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) usleep_range(6000, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) usleep_range(12000, 16000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) delay_us = sc230ai_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) clk_disable_unprepare(sc230ai->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static void __sc230ai_power_off(struct sc230ai *sc230ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) struct device *dev = &sc230ai->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) clk_disable_unprepare(sc230ai->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (sc230ai->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (sc230ai->is_first_streamoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) sc230ai->is_thunderboot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) sc230ai->is_first_streamoff = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (!IS_ERR(sc230ai->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) gpiod_set_value_cansleep(sc230ai->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (!IS_ERR(sc230ai->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) gpiod_set_value_cansleep(sc230ai->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (!IS_ERR_OR_NULL(sc230ai->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) ret = pinctrl_select_state(sc230ai->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) sc230ai->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) regulator_bulk_disable(SC230AI_NUM_SUPPLIES, sc230ai->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static int sc230ai_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) struct sc230ai *sc230ai = to_sc230ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return __sc230ai_power_on(sc230ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static int sc230ai_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) struct sc230ai *sc230ai = to_sc230ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) __sc230ai_power_off(sc230ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static int sc230ai_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct sc230ai *sc230ai = to_sc230ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) const struct sc230ai_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) mutex_lock(&sc230ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) mutex_unlock(&sc230ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) static int sc230ai_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static const struct dev_pm_ops sc230ai_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) SET_RUNTIME_PM_OPS(sc230ai_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) sc230ai_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static const struct v4l2_subdev_internal_ops sc230ai_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .open = sc230ai_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static const struct v4l2_subdev_core_ops sc230ai_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .s_power = sc230ai_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .ioctl = sc230ai_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .compat_ioctl32 = sc230ai_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) static const struct v4l2_subdev_video_ops sc230ai_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) .s_stream = sc230ai_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) .g_frame_interval = sc230ai_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) static const struct v4l2_subdev_pad_ops sc230ai_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .enum_mbus_code = sc230ai_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .enum_frame_size = sc230ai_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .enum_frame_interval = sc230ai_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) .get_fmt = sc230ai_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) .set_fmt = sc230ai_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) .get_mbus_config = sc230ai_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) static const struct v4l2_subdev_ops sc230ai_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) .core = &sc230ai_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) .video = &sc230ai_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) .pad = &sc230ai_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static void sc230ai_modify_fps_info(struct sc230ai *sc230ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) const struct sc230ai_mode *mode = sc230ai->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) sc230ai->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) sc230ai->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) static int sc230ai_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) struct sc230ai *sc230ai = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) struct sc230ai, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) struct i2c_client *client = sc230ai->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) u32 again = 0, dgain = 0, dgain_fine = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) s32 temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) max = sc230ai->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) __v4l2_ctrl_modify_range(sc230ai->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) sc230ai->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) sc230ai->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) sc230ai->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) dev_dbg(&client->dev, "set exposure value 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (sc230ai->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) temp = ctrl->val * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) ret = sc230ai_write_reg(sc230ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) SC230AI_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) SC230AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) SC230AI_FETCH_EXP_H(temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) ret |= sc230ai_write_reg(sc230ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) SC230AI_REG_EXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) SC230AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) SC230AI_FETCH_EXP_M(temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) ret |= sc230ai_write_reg(sc230ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) SC230AI_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) SC230AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) SC230AI_FETCH_EXP_L(temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (sc230ai->cur_mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) sc230ai_get_gain_reg(sc230ai, &again, &dgain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) &dgain_fine, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) dev_dbg(&client->dev, "gain %d, ag 0x%x, dg 0x%x, dg_f 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) ctrl->val, again, dgain, dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) ret = sc230ai_write_reg(sc230ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) SC230AI_REG_ANA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) SC230AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) again);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) ret |= sc230ai_write_reg(sc230ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) SC230AI_REG_DIG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) SC230AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) ret |= sc230ai_write_reg(sc230ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) SC230AI_REG_DIG_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) SC230AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) dev_dbg(&client->dev, "set blank value 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) ret = sc230ai_write_reg(sc230ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) SC230AI_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) SC230AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) (ctrl->val + sc230ai->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) ret |= sc230ai_write_reg(sc230ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) SC230AI_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) SC230AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) (ctrl->val + sc230ai->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) sc230ai->cur_vts = ctrl->val + sc230ai->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (sc230ai->cur_vts != sc230ai->cur_mode->vts_def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) sc230ai_modify_fps_info(sc230ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) ret = sc230ai_enable_test_pattern(sc230ai, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ret = sc230ai_read_reg(sc230ai->client, SC230AI_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) SC230AI_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) ret |= sc230ai_write_reg(sc230ai->client, SC230AI_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) SC230AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) SC230AI_FETCH_MIRROR(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) ret = sc230ai_read_reg(sc230ai->client, SC230AI_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) SC230AI_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) ret |= sc230ai_write_reg(sc230ai->client, SC230AI_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) SC230AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) SC230AI_FETCH_FLIP(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) static const struct v4l2_ctrl_ops sc230ai_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .s_ctrl = sc230ai_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) static int sc230ai_initialize_controls(struct sc230ai *sc230ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) const struct sc230ai_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) handler = &sc230ai->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) mode = sc230ai->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) handler->lock = &sc230ai->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) sc230ai->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) ARRAY_SIZE(link_freq_menu_items) - 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) __v4l2_ctrl_s_ctrl(sc230ai->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (mode->mipi_freq_idx == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) dst_pixel_rate = PIXEL_RATE_WITH_371M_10BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) else if (mode->mipi_freq_idx == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) dst_pixel_rate = PIXEL_RATE_WITH_371M_10BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) sc230ai->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) V4L2_CID_PIXEL_RATE, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) PIXEL_RATE_WITH_371M_10BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) 1, dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) sc230ai->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (sc230ai->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) sc230ai->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) sc230ai->vblank = v4l2_ctrl_new_std(handler, &sc230ai_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) SC230AI_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) exposure_max = SC230AI_EXPOSURE_LIN_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) sc230ai->exposure = v4l2_ctrl_new_std(handler, &sc230ai_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) V4L2_CID_EXPOSURE, SC230AI_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) exposure_max, SC230AI_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) sc230ai->anal_gain = v4l2_ctrl_new_std(handler, &sc230ai_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) V4L2_CID_ANALOGUE_GAIN, SC230AI_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) SC230AI_GAIN_MAX, SC230AI_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) SC230AI_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) sc230ai->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) &sc230ai_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) ARRAY_SIZE(sc230ai_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) 0, 0, sc230ai_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) v4l2_ctrl_new_std(handler, &sc230ai_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) v4l2_ctrl_new_std(handler, &sc230ai_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) dev_err(&sc230ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) sc230ai->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) sc230ai->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) sc230ai->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static int sc230ai_check_sensor_id(struct sc230ai *sc230ai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) struct device *dev = &sc230ai->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) if (sc230ai->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) ret = sc230ai_read_reg(client, SC230AI_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) SC230AI_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) static int sc230ai_configure_regulators(struct sc230ai *sc230ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) for (i = 0; i < SC230AI_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) sc230ai->supplies[i].supply = sc230ai_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) return devm_regulator_bulk_get(&sc230ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) SC230AI_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) sc230ai->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static int sc230ai_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) struct sc230ai *sc230ai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) sc230ai = devm_kzalloc(dev, sizeof(*sc230ai), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) if (!sc230ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) &sc230ai->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) &sc230ai->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) &sc230ai->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) &sc230ai->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) sc230ai->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) sc230ai->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) sc230ai->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if (i == ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) sc230ai->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) sc230ai->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (IS_ERR(sc230ai->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) sc230ai->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (IS_ERR(sc230ai->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) sc230ai->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (IS_ERR(sc230ai->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) sc230ai->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if (!IS_ERR(sc230ai->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) sc230ai->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) pinctrl_lookup_state(sc230ai->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) if (IS_ERR(sc230ai->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) sc230ai->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) pinctrl_lookup_state(sc230ai->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) if (IS_ERR(sc230ai->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) ret = sc230ai_configure_regulators(sc230ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) mutex_init(&sc230ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) sd = &sc230ai->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) v4l2_i2c_subdev_init(sd, client, &sc230ai_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) ret = sc230ai_initialize_controls(sc230ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) ret = __sc230ai_power_on(sc230ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) ret = sc230ai_check_sensor_id(sc230ai, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) sd->internal_ops = &sc230ai_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) sc230ai->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) ret = media_entity_pads_init(&sd->entity, 1, &sc230ai->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (strcmp(sc230ai->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) sc230ai->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) SC230AI_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) __sc230ai_power_off(sc230ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) v4l2_ctrl_handler_free(&sc230ai->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) mutex_destroy(&sc230ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) static int sc230ai_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) struct sc230ai *sc230ai = to_sc230ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) v4l2_ctrl_handler_free(&sc230ai->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) mutex_destroy(&sc230ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) __sc230ai_power_off(sc230ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) static const struct of_device_id sc230ai_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) { .compatible = "smartsens,sc230ai" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) MODULE_DEVICE_TABLE(of, sc230ai_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) static const struct i2c_device_id sc230ai_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) { "smartsens,sc230ai", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) static struct i2c_driver sc230ai_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .name = SC230AI_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .pm = &sc230ai_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .of_match_table = of_match_ptr(sc230ai_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .probe = &sc230ai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .remove = &sc230ai_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .id_table = sc230ai_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) return i2c_add_driver(&sc230ai_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) i2c_del_driver(&sc230ai_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) subsys_initcall(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) MODULE_DESCRIPTION("smartsens sc230ai sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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