^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sc2239 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X01 add quick stream support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) //#define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SC2239_LANES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SC2239_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SC2239_LINK_FREQ 371250000 // 742.5Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SC2239_PIXEL_RATE (SC2239_LINK_FREQ * 2 * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) SC2239_LANES / SC2239_BITS_PER_SAMPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SC2239_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CHIP_ID 0xcb10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SC2239_REG_CHIP_ID 0x3107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SC2239_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SC2239_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SC2239_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SC2239_REG_EXPOSURE 0x3e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SC2239_EXPOSURE_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC2239_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SC2239_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SC2239_REG_COARSE_AGAIN 0x3e08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SC2239_REG_FINE_AGAIN 0x3e09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ANALOG_GAIN_MIN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ANALOG_GAIN_MAX 0x1F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ANALOG_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ANALOG_GAIN_DEFAULT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SC4238_GROUP_UPDATE_ADDRESS 0x3812
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SC4238_GROUP_UPDATE_START_DATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SC4238_GROUP_UPDATE_END_DATA 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SC2239_REG_TEST_PATTERN 0x4501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC2239_TEST_PATTERN_BIT_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SC2239_REG_VTS 0x320e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DELAY_MS 0xEEEE /* Array delay token */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SC2239_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SC2239_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SC2239_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PIX_FORMAT MEDIA_BUS_FMT_SBGGR10_1X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SC2239_NAME "sc2239"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const char * const sc2239_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SC2239_NUM_SUPPLIES ARRAY_SIZE(sc2239_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct sc2239_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct sc2239 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct regulator_bulk_data supplies[SC2239_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct v4l2_fract cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) const struct sc2239_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 old_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define to_sc2239(sd) container_of(sd, struct sc2239, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * mipi_datarate per lane 742.5Mbps, 1 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const struct regval sc2239_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0x301f, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0x3038, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0x3253, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0x3301, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0x3304, 0xa8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0x3306, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x3308, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x3309, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0x330a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x330b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x331e, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x331f, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x3333, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x3364, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x3390, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x3391, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x3392, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x3393, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x3394, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x3395, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x33af, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x360f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x3630, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x3634, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x3637, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x363c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x3670, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x3671, 0xc2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x3672, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x3673, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x3677, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x3678, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x3679, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x367a, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x367b, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x367e, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x367f, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x3690, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x3691, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x3692, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x369c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x369d, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x36ea, 0x75},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x36ed, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x36fa, 0x75},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x36fb, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x36fc, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x36fd, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3904, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3908, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3933, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3934, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3940, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3941, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3942, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3943, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3944, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3945, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3e01, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3e02, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x4509, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x4800, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x4819, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x481b, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x481d, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x4821, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x4823, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x5000, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x5780, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x5781, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x5782, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x5783, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x5784, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x5785, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x5786, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x5787, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x5788, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x5789, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x578a, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x36e9, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x36f9, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {DELAY_MS, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * mipi_datarate per lane 742.5Mbps, 1lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static const struct regval sc2239_1920x1080_regs_1lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static const struct sc2239_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .exp_def = 0x0400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .hts_def = 0x44C * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .vts_def = 0x0465,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .reg_list = sc2239_1920x1080_regs_1lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static const char * const sc2239_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) SC2239_LINK_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int sc2239_write_reg(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u16 reg, u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ret = i2c_master_send(client, buf, len + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (ret != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) static int sc2239_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int delay_ms = 0, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) if (regs[i].addr == DELAY_MS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) delay_ms = regs[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dev_info(&client->dev, "delay(%d) ms !\n", delay_ms);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) usleep_range(1000 * delay_ms, 1000 * delay_ms + 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ret = sc2239_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) SC2239_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int sc2239_read_reg(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u16 reg, unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static int sc2239_get_reso_dist(const struct sc2239_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static const struct sc2239_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) sc2239_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dist = sc2239_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static int sc2239_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct sc2239 *sc2239 = to_sc2239(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) const struct sc2239_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) mutex_lock(&sc2239->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) mode = sc2239_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) fmt->format.code = PIX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) mutex_unlock(&sc2239->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) sc2239->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) __v4l2_ctrl_modify_range(sc2239->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) __v4l2_ctrl_modify_range(sc2239->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) SC2239_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) sc2239->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) sc2239->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) mutex_unlock(&sc2239->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int sc2239_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct sc2239 *sc2239 = to_sc2239(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) const struct sc2239_mode *mode = sc2239->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) mutex_lock(&sc2239->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) mutex_unlock(&sc2239->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) fmt->format.code = PIX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) mutex_unlock(&sc2239->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static int sc2239_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) code->code = PIX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static int sc2239_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (fse->code != PIX_FORMAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static int sc2239_enable_test_pattern(struct sc2239 *sc2239, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) ret = sc2239_read_reg(sc2239->client, SC2239_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) SC2239_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) val |= SC2239_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) val &= ~SC2239_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret |= sc2239_write_reg(sc2239->client, SC2239_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) SC2239_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static void sc2239_get_module_inf(struct sc2239 *sc2239,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) strlcpy(inf->base.sensor, SC2239_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) strlcpy(inf->base.module, sc2239->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) strlcpy(inf->base.lens, sc2239->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static long sc2239_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct sc2239 *sc2239 = to_sc2239(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) sc2239_get_module_inf(sc2239, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) ret = sc2239_write_reg(sc2239->client, SC2239_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) SC2239_REG_VALUE_08BIT, SC2239_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ret = sc2239_write_reg(sc2239->client, SC2239_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) SC2239_REG_VALUE_08BIT, SC2239_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static long sc2239_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u32 stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ret = sc2239_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ret = sc2239_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ret = sc2239_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int sc2239_set_ctrl_gain(struct sc2239 *sc2239, u32 a_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u32 coarse_again, fine_again, fine_again_reg, coarse_again_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u32 switch_value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if ( a_gain != sc2239->old_gain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (a_gain < 0x40) { /*1x ~ 2x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) fine_again = a_gain - 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) coarse_again = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) fine_again_reg = ((0x01 << 5) & 0x20) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) (fine_again & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) coarse_again_reg = coarse_again & 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) switch_value = 0x64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) } else if (a_gain < 0x80) { /*2x ~ 4x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) fine_again = (a_gain >> 1) - 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) coarse_again = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) fine_again_reg = ((0x01 << 5) & 0x20) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) (fine_again & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) coarse_again_reg = coarse_again & 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) switch_value = 0x64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) } else if (a_gain < 0x100) { /*4x ~ 8x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) fine_again = (a_gain >> 2) - 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) coarse_again = 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) fine_again_reg = ((0x01 << 5) & 0x20) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) (fine_again & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) coarse_again_reg = coarse_again & 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) switch_value = 0x44;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) } else { /*8x ~ 16x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) fine_again = (a_gain >> 3) - 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) coarse_again = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) fine_again_reg = ((0x01 << 5) & 0x20) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) (fine_again & 0x1f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) coarse_again_reg = coarse_again & 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) switch_value = 0x24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ret = sc2239_write_reg(sc2239->client, 0x3634,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) SC2239_REG_VALUE_08BIT, switch_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) ret |= sc2239_write_reg(sc2239->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) SC2239_REG_COARSE_AGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) SC2239_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) coarse_again_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ret |= sc2239_write_reg(sc2239->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) SC2239_REG_FINE_AGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) SC2239_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) fine_again_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) sc2239->old_gain = a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static int __sc2239_start_stream(struct sc2239 *sc2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ret = sc2239_write_array(sc2239->client, sc2239->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) mutex_unlock(&sc2239->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ret = v4l2_ctrl_handler_setup(&sc2239->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) mutex_lock(&sc2239->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return sc2239_write_reg(sc2239->client, SC2239_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) SC2239_REG_VALUE_08BIT, SC2239_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static int __sc2239_stop_stream(struct sc2239 *sc2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return sc2239_write_reg(sc2239->client, SC2239_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) SC2239_REG_VALUE_08BIT, SC2239_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int sc2239_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct sc2239 *sc2239 = to_sc2239(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct i2c_client *client = sc2239->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) sc2239->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) sc2239->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) DIV_ROUND_CLOSEST(sc2239->cur_mode->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) sc2239->cur_mode->max_fps.numerator));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) mutex_lock(&sc2239->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (on == sc2239->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) ret = __sc2239_start_stream(sc2239);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) __sc2239_stop_stream(sc2239);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) sc2239->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) mutex_unlock(&sc2239->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int sc2239_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct sc2239 *sc2239 = to_sc2239(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) const struct sc2239_mode *mode = sc2239->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (sc2239->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) fi->interval = sc2239->cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int sc2239_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct sc2239 *sc2239 = to_sc2239(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct i2c_client *client = sc2239->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) mutex_lock(&sc2239->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (sc2239->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ret = sc2239_write_array(sc2239->client, sc2239_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) sc2239->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) sc2239->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) mutex_unlock(&sc2239->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static inline u32 sc2239_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return DIV_ROUND_UP(cycles, SC2239_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static int __sc2239_power_on(struct sc2239 *sc2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct device *dev = &sc2239->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ret = clk_set_rate(sc2239->xvclk, SC2239_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (clk_get_rate(sc2239->xvclk) != SC2239_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = clk_prepare_enable(sc2239->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (!IS_ERR(sc2239->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) gpiod_set_value_cansleep(sc2239->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) ret = regulator_bulk_enable(SC2239_NUM_SUPPLIES, sc2239->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (!IS_ERR(sc2239->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) gpiod_set_value_cansleep(sc2239->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (!IS_ERR(sc2239->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) gpiod_set_value_cansleep(sc2239->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) delay_us = sc2239_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) clk_disable_unprepare(sc2239->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static void __sc2239_power_off(struct sc2239 *sc2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (!IS_ERR(sc2239->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) gpiod_set_value_cansleep(sc2239->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) clk_disable_unprepare(sc2239->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (!IS_ERR(sc2239->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) gpiod_set_value_cansleep(sc2239->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) regulator_bulk_disable(SC2239_NUM_SUPPLIES, sc2239->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static int sc2239_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct sc2239 *sc2239 = to_sc2239(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return __sc2239_power_on(sc2239);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static int sc2239_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct sc2239 *sc2239 = to_sc2239(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) __sc2239_power_off(sc2239);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int sc2239_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct sc2239 *sc2239 = to_sc2239(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) const struct sc2239_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) mutex_lock(&sc2239->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) try_fmt->code = PIX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) mutex_unlock(&sc2239->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static int sc2239_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u32 val = 1 << (SC2239_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static int sc2239_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (fie->code != PIX_FORMAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static const struct dev_pm_ops sc2239_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) SET_RUNTIME_PM_OPS(sc2239_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) sc2239_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static const struct v4l2_subdev_internal_ops sc2239_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .open = sc2239_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static const struct v4l2_subdev_core_ops sc2239_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) .s_power = sc2239_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) .ioctl = sc2239_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) .compat_ioctl32 = sc2239_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static const struct v4l2_subdev_video_ops sc2239_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) .s_stream = sc2239_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .g_frame_interval = sc2239_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static const struct v4l2_subdev_pad_ops sc2239_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .enum_mbus_code = sc2239_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) .enum_frame_size = sc2239_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) .enum_frame_interval = sc2239_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) .get_fmt = sc2239_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) .set_fmt = sc2239_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .get_mbus_config = sc2239_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static const struct v4l2_subdev_ops sc2239_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) .core = &sc2239_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .video = &sc2239_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .pad = &sc2239_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static void sc2239_modify_fps_info(struct sc2239 *sc2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) const struct sc2239_mode *mode = sc2239->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) sc2239->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) sc2239->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static int sc2239_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct sc2239 *sc2239 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) struct sc2239, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct i2c_client *client = sc2239->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) dev_dbg(&client->dev, "ctrl->id(0x%x) val 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) max = sc2239->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) __v4l2_ctrl_modify_range(sc2239->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) sc2239->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) sc2239->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) sc2239->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ret = sc2239_write_reg(sc2239->client, SC2239_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) SC2239_REG_VALUE_24BIT, ctrl->val << 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dev_dbg(&client->dev, "set exposure 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ret = sc2239_set_ctrl_gain(sc2239, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) dev_dbg(&client->dev, "set analog gain 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ret = sc2239_write_reg(sc2239->client, SC2239_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) SC2239_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ctrl->val + sc2239->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) sc2239->cur_vts = ctrl->val + sc2239->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (sc2239->cur_vts != sc2239->cur_mode->vts_def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) sc2239_modify_fps_info(sc2239);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ret = sc2239_enable_test_pattern(sc2239, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static const struct v4l2_ctrl_ops sc2239_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .s_ctrl = sc2239_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static int sc2239_initialize_controls(struct sc2239 *sc2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) const struct sc2239_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) handler = &sc2239->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) mode = sc2239->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) handler->lock = &sc2239->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) 0, SC2239_PIXEL_RATE, 1, SC2239_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) sc2239->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (sc2239->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) sc2239->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) sc2239->vblank = v4l2_ctrl_new_std(handler, &sc2239_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) SC2239_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) sc2239->exposure = v4l2_ctrl_new_std(handler, &sc2239_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) V4L2_CID_EXPOSURE, SC2239_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) exposure_max, SC2239_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) sc2239->anal_gain = v4l2_ctrl_new_std(handler, &sc2239_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) ANALOG_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) sc2239->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) &sc2239_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ARRAY_SIZE(sc2239_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) 0, 0, sc2239_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) dev_err(&sc2239->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) sc2239->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) sc2239->old_gain = ANALOG_GAIN_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) sc2239->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) sc2239->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static int sc2239_check_sensor_id(struct sc2239 *sc2239,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct device *dev = &sc2239->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) ret = sc2239_read_reg(client, SC2239_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) SC2239_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) dev_info(dev, "Detected SC2239 CHIP ID = 0x%04x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static int sc2239_configure_regulators(struct sc2239 *sc2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) for (i = 0; i < SC2239_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) sc2239->supplies[i].supply = sc2239_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return devm_regulator_bulk_get(&sc2239->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) SC2239_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) sc2239->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static int sc2239_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct sc2239 *sc2239;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) sc2239 = devm_kzalloc(dev, sizeof(*sc2239), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (!sc2239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) &sc2239->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) &sc2239->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) &sc2239->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) &sc2239->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) sc2239->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) sc2239->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) sc2239->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (IS_ERR(sc2239->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) sc2239->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (IS_ERR(sc2239->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) sc2239->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (IS_ERR(sc2239->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ret = sc2239_configure_regulators(sc2239);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) mutex_init(&sc2239->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) sd = &sc2239->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) v4l2_i2c_subdev_init(sd, client, &sc2239_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ret = sc2239_initialize_controls(sc2239);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ret = __sc2239_power_on(sc2239);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ret = sc2239_check_sensor_id(sc2239, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) sd->internal_ops = &sc2239_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) sc2239->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ret = media_entity_pads_init(&sd->entity, 1, &sc2239->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (strcmp(sc2239->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) sc2239->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) SC2239_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) __sc2239_power_off(sc2239);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) v4l2_ctrl_handler_free(&sc2239->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) mutex_destroy(&sc2239->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) static int sc2239_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) struct sc2239 *sc2239 = to_sc2239(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) v4l2_ctrl_handler_free(&sc2239->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) mutex_destroy(&sc2239->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) __sc2239_power_off(sc2239);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) static const struct of_device_id sc2239_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) { .compatible = "smartsens,sc2239" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) MODULE_DEVICE_TABLE(of, sc2239_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static const struct i2c_device_id sc2239_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) { "smartsens,sc2239", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) static struct i2c_driver sc2239_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .name = SC2239_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .pm = &sc2239_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .of_match_table = of_match_ptr(sc2239_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .probe = &sc2239_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .remove = &sc2239_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .id_table = sc2239_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return i2c_add_driver(&sc2239_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) i2c_del_driver(&sc2239_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) MODULE_DESCRIPTION("Smartsens sc2239 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) MODULE_AUTHOR("zack.zeng");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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