^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sc2232 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version,adjust sc2232.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MIPI_FREQ_186M 186000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SC2232_MAX_PIXEL_RATE (MIPI_FREQ_186M * 2 / 10 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SC2232_XVCLK_FREQ 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CHIP_ID 0x2238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SC2232_REG_CHIP_ID 0x3107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SC2232_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SC2232_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SC2232_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SC2232_EXPOSURE_MIN 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SC2232_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SC2232_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SC2232_REG_EXP_LONG_H 0x3e00 //[3:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC2232_REG_EXP_LONG_M 0x3e01 //[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SC2232_REG_EXP_LONG_L 0x3e02 //[7:4]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SC2232_REG_AGAIN 0x3e08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SC2232_REG_AGAIN_FINE 0x3e09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SC2232_REG_DGAIN 0x3e06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SC2232_REG_DGAIN_FINE 0x3e07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SC2232_GAIN_MIN 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SC2232_GAIN_MAX 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SC2232_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SC2232_GAIN_DEFAULT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SC2232_SOFTWARE_RESET_REG 0x0103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SC2232_REG_VTS 0x320e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SC2232_REG_HTS 0x320c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SC2232_FLIP_REG 0x3221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SC2232_FLIP_MASK 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SC2232_MIRROR_MASK 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SC2232_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SC2232_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SC2232_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SC2232_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SC2232_NAME "sc2232"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const char * const sc2232_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SC2232_NUM_SUPPLIES ARRAY_SIZE(sc2232_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct sc2232_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 mipi_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct sc2232 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct regulator_bulk_data supplies[SC2232_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct v4l2_fract cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const struct sc2232_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define to_sc2232(sd) container_of(sd, struct sc2232, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static const struct regval sc2232_linear10bit_1920x1080_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0x0103,0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x0100,0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x3034,0x81},//pll2 bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x3039,0xa2},//pll1 bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x3624,0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x337f,0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x3368,0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x3369,0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x336a,0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x336b,0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x3367,0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x330e,0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x3366,0x7c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x3302,0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x3907,0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x3902,0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x3908,0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x335e,0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x335f,0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x337c,0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x337d,0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x33a0,0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x3633,0x4f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x3622,0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x3631,0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x366e,0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x3326,0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x3303,0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x3638,0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x3636,0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x3625,0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x331b,0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x3333,0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x3635,0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x363c,0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x3038,0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3639,0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x3621,0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x3211,0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x3320,0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x331e,0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3620,0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3309,0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x331f,0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3308,0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3f00,0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3802,0x01}, //0x01 for over 2fps update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x33aa,0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3677,0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3678,0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3679,0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x367e,0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x367f,0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3670,0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3690,0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3691,0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3692,0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x369c,0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x369d,0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x360f,0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3671,0xc6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3672,0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3673,0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x367a,0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x367b,0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x320c,0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x320d,0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x320e,0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x320f,0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3f04,0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3f05,0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3235,0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3236,0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3222,0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3901,0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3905,0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3e1e,0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3900,0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x391d,0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x391e,0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3641,0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3213,0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3614,0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x363a,0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3630,0x9c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3306,0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x330b,0xcd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3018,0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3031,0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3037,0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3001,0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x4603,0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x4827,0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x301c,0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x4809,0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x3314,0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x303c,0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x4837,0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3933,0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3934,0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3940,0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3942,0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3943,0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3960,0xba},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x3961,0xae},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x3966,0xba},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3980,0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3981,0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3982,0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3903,0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3984,0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3985,0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x3986,0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3987,0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3988,0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3989,0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x398a,0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x398b,0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x398c,0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x398d,0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x398e,0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x398f,0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3990,0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x3991,0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x3992,0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3993,0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3994,0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x3995,0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3996,0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3997,0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3998,0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x3999,0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x399a,0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x399b,0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x399c,0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x399d,0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x399e,0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x399f,0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x3637,0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x363b,0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x366f,0x2c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x5000,0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x5780,0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x5781,0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x5782,0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x5783,0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x5784,0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x5785,0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x5786,0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x5787,0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x5788,0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x57a0,0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x57a1,0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x57a2,0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x57a3,0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x395e,0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x3962,0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3e00,0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x3e01,0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3e02,0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3e03,0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3e06,0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x3e07,0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x3e08,0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x3e09,0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x3301,0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x3632,0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x3034,0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x3039,0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x0100,0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * The width and height must be configured to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * the same as the current output resolution of the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * The input width of the isp needs to be 16 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * The input height of the isp needs to be 8 aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * If the width or height does not meet the alignment rules,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * you can configure the cropping parameters with the following function to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * crop out the appropriate resolution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * struct v4l2_subdev_pad_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * .get_selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const struct sc2232_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* linear modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .exp_def = 0x0463,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) .hts_def = 0x0898 * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) .vts_def = 0x0465,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) .reg_list = sc2232_linear10bit_1920x1080_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) .mipi_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static const s64 link_freq_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) MIPI_FREQ_186M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static int sc2232_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int sc2232_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) ret |= sc2232_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) SC2232_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int sc2232_read_reg(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int sc2232_get_reso_dist(const struct sc2232_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static const struct sc2232_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) sc2232_find_best_fit(struct sc2232 *sc2232, struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) for (i = 0; i < sc2232->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dist = sc2232_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if ((cur_best_fit_dist == -1 || dist <= cur_best_fit_dist) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) (supported_modes[i].bus_fmt == framefmt->code)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static void sc2232_change_mode(struct sc2232 *sc2232, const struct sc2232_mode *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) sc2232->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) sc2232->cur_vts = sc2232->cur_mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_info(&sc2232->client->dev, "set fmt: cur_mode: %dx%d, hdr: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) mode->width, mode->height, mode->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static int sc2232_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct sc2232 *sc2232 = to_sc2232(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) const struct sc2232_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) mutex_lock(&sc2232->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) mode = sc2232_find_best_fit(sc2232, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) mutex_unlock(&sc2232->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) sc2232_change_mode(sc2232, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) __v4l2_ctrl_modify_range(sc2232->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) __v4l2_ctrl_modify_range(sc2232->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) SC2232_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) __v4l2_ctrl_s_ctrl(sc2232->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) mode->bpp * 2 * SC2232_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) __v4l2_ctrl_s_ctrl_int64(sc2232->pixel_rate, pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) sc2232->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) sc2232->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) mutex_unlock(&sc2232->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int sc2232_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct sc2232 *sc2232 = to_sc2232(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) const struct sc2232_mode *mode = sc2232->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) mutex_lock(&sc2232->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) mutex_unlock(&sc2232->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) mutex_unlock(&sc2232->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static int sc2232_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct sc2232 *sc2232 = to_sc2232(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) code->code = sc2232->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static int sc2232_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) struct sc2232 *sc2232 = to_sc2232(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (fse->index >= sc2232->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) if (fse->code != supported_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) static int sc2232_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct sc2232 *sc2232 = to_sc2232(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) const struct sc2232_mode *mode = sc2232->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (sc2232->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) fi->interval = sc2232->cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static int sc2232_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct sc2232 *sc2232 = to_sc2232(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) const struct sc2232_mode *mode = sc2232->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) val = 1 << (SC2232_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (mode->hdr_mode == HDR_X2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) val = 1 << (SC2232_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static void sc2232_get_module_inf(struct sc2232 *sc2232,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) strlcpy(inf->base.sensor, SC2232_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) strlcpy(inf->base.module, sc2232->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) strlcpy(inf->base.lens, sc2232->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int sc2232_set_gain(struct sc2232 *sc2232, u32 total_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) u32 again = 0, again_fine = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u32 dgain = 0, dgain_fine = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 step = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (total_gain < 0x80) {/* 1x gain ~ 2x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) step = (total_gain - 0x40) >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) again = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) again_fine = step + 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dgain = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) dgain_fine = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ret |= sc2232_write_reg(sc2232->client, 0x3301, SC2232_REG_VALUE_08BIT, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ret |= sc2232_write_reg(sc2232->client, 0x3632, SC2232_REG_VALUE_08BIT, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) } else if (total_gain < 0x100) {/* 2x gain ~ 4x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) step = (total_gain - 0x80) >> 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) again = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) again_fine = step + 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dgain = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) dgain_fine = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ret |= sc2232_write_reg(sc2232->client, 0x3301, SC2232_REG_VALUE_08BIT, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ret |= sc2232_write_reg(sc2232->client, 0x3632, SC2232_REG_VALUE_08BIT, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) } else if (total_gain < 0x200) {/* 4x gain ~ 8x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) step = (total_gain - 0x100) >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) again = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) again_fine = step + 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) dgain = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dgain_fine = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ret |= sc2232_write_reg(sc2232->client, 0x3301, SC2232_REG_VALUE_08BIT, 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ret |= sc2232_write_reg(sc2232->client, 0x3632, SC2232_REG_VALUE_08BIT, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) } else if (total_gain < 0x400) {/* 8x gain ~ 16x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) step = (total_gain - 0x200) >> 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) again = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) again_fine = step + 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dgain = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dgain_fine = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ret |= sc2232_write_reg(sc2232->client, 0x3301, SC2232_REG_VALUE_08BIT, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ret |= sc2232_write_reg(sc2232->client, 0x3632, SC2232_REG_VALUE_08BIT, 0x08);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) } else if (total_gain < 0x800) { /* 16x gain ~ 32x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) step = (total_gain - 0x400) >> 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) again = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) again_fine = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) dgain = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) dgain_fine = step * 8 + 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ret |= sc2232_write_reg(sc2232->client, 0x3301, SC2232_REG_VALUE_08BIT, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ret |= sc2232_write_reg(sc2232->client, 0x3632, SC2232_REG_VALUE_08BIT, 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) } else if (total_gain < 0x1000) { /* 32x gain ~ 64x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) step = (total_gain - 0x800) >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) again = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) again_fine = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dgain = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dgain_fine = step * 8 + 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ret |= sc2232_write_reg(sc2232->client, 0x3301, SC2232_REG_VALUE_08BIT, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ret |= sc2232_write_reg(sc2232->client, 0x3632, SC2232_REG_VALUE_08BIT, 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) } else if (total_gain < 0x2000) { /* 64x gain ~ 128x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) step = (total_gain - 0x1000) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) again = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) again_fine = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) dgain = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dgain_fine = step * 8 + 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ret |= sc2232_write_reg(sc2232->client, 0x3301, SC2232_REG_VALUE_08BIT, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ret |= sc2232_write_reg(sc2232->client, 0x3632, SC2232_REG_VALUE_08BIT, 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) } else if (total_gain <= 0x4000) { /* 128x gain ~ 256x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) step = (total_gain - 0x2000) >> 9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) step = (step >= 16) ? 0xf : step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) again = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) again_fine = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) dgain = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dgain_fine = step * 8 + 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret |= sc2232_write_reg(sc2232->client, 0x3301, SC2232_REG_VALUE_08BIT, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ret |= sc2232_write_reg(sc2232->client, 0x3632, SC2232_REG_VALUE_08BIT, 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret |= sc2232_write_reg(sc2232->client, 0x3812, SC2232_REG_VALUE_08BIT, 0x30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_dbg(&sc2232->client->dev, "total_gain:%d again 0x%x, again_fine 0x%x, dgain 0x%x, dgain_fine 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) total_gain, again, again_fine, dgain, dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ret |= sc2232_read_reg(sc2232->client, SC2232_REG_AGAIN,SC2232_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ret |= sc2232_write_reg(sc2232->client, SC2232_REG_AGAIN,SC2232_REG_VALUE_08BIT, (val & 0xE3) | (again << 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) ret |= sc2232_read_reg(sc2232->client, SC2232_REG_DGAIN,SC2232_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret |= sc2232_write_reg(sc2232->client, SC2232_REG_DGAIN,SC2232_REG_VALUE_08BIT,(val & 0xF0) | dgain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ret |= sc2232_write_reg(sc2232->client, SC2232_REG_AGAIN_FINE, SC2232_REG_VALUE_08BIT, again_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ret |= sc2232_write_reg(sc2232->client, SC2232_REG_DGAIN_FINE, SC2232_REG_VALUE_08BIT, dgain_fine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static long sc2232_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct sc2232 *sc2232 = to_sc2232(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct rkmodule_hdr_cfg *hdr_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) u32 stream;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) sc2232_get_module_inf(sc2232, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) hdr_cfg = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) hdr_cfg->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) hdr_cfg->hdr_mode = sc2232->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) ret = sc2232_write_reg(sc2232->client, SC2232_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) SC2232_REG_VALUE_08BIT, SC2232_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) ret = sc2232_write_reg(sc2232->client, SC2232_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) SC2232_REG_VALUE_08BIT, SC2232_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static long sc2232_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) u32 cg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret = sc2232_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ret = sc2232_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) ret = sc2232_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) ret = sc2232_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) ret = sc2232_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) case RKMODULE_SET_CONVERSION_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ret = copy_from_user(&cg, up, sizeof(cg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ret = sc2232_ioctl(sd, cmd, &cg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) ret = sc2232_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) static int __sc2232_start_stream(struct sc2232 *sc2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ret = sc2232_write_array(sc2232->client, sc2232->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ret = __v4l2_ctrl_handler_setup(&sc2232->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (sc2232->has_init_exp && sc2232->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ret = sc2232_ioctl(&sc2232->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) &sc2232->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) dev_err(&sc2232->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return sc2232_write_reg(sc2232->client, SC2232_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) SC2232_REG_VALUE_08BIT, SC2232_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static int __sc2232_stop_stream(struct sc2232 *sc2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) sc2232->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return sc2232_write_reg(sc2232->client, SC2232_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) SC2232_REG_VALUE_08BIT, SC2232_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static int sc2232_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct sc2232 *sc2232 = to_sc2232(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct i2c_client *client = sc2232->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) mutex_lock(&sc2232->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (on == sc2232->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) ret = __sc2232_start_stream(sc2232);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) __sc2232_stop_stream(sc2232);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) sc2232->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) mutex_unlock(&sc2232->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static int sc2232_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct sc2232 *sc2232 = to_sc2232(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct i2c_client *client = sc2232->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) mutex_lock(&sc2232->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (sc2232->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ret |= sc2232_write_reg(sc2232->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) SC2232_SOFTWARE_RESET_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) SC2232_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) 0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) sc2232->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) sc2232->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) mutex_unlock(&sc2232->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static int __sc2232_power_on(struct sc2232 *sc2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct device *dev = &sc2232->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (!IS_ERR_OR_NULL(sc2232->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) ret = pinctrl_select_state(sc2232->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) sc2232->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ret = clk_set_rate(sc2232->xvclk, SC2232_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) dev_warn(dev, "Failed to set xvclk rate (27MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (clk_get_rate(sc2232->xvclk) != SC2232_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dev_warn(dev, "xvclk mismatched, modes are based on 27MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ret = clk_prepare_enable(sc2232->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (!IS_ERR(sc2232->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) gpiod_set_value_cansleep(sc2232->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ret = regulator_bulk_enable(SC2232_NUM_SUPPLIES, sc2232->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (!IS_ERR(sc2232->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) gpiod_set_value_cansleep(sc2232->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) if (!IS_ERR(sc2232->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) gpiod_set_value_cansleep(sc2232->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) usleep_range(2000, 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) clk_disable_unprepare(sc2232->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static void __sc2232_power_off(struct sc2232 *sc2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct device *dev = &sc2232->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (!IS_ERR(sc2232->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) gpiod_set_value_cansleep(sc2232->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) clk_disable_unprepare(sc2232->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (!IS_ERR(sc2232->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) gpiod_set_value_cansleep(sc2232->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (!IS_ERR_OR_NULL(sc2232->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ret = pinctrl_select_state(sc2232->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) sc2232->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) regulator_bulk_disable(SC2232_NUM_SUPPLIES, sc2232->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static int sc2232_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) struct sc2232 *sc2232 = to_sc2232(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return __sc2232_power_on(sc2232);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static int sc2232_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct sc2232 *sc2232 = to_sc2232(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) __sc2232_power_off(sc2232);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static int sc2232_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct sc2232 *sc2232 = to_sc2232(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) const struct sc2232_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) mutex_lock(&sc2232->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) mutex_unlock(&sc2232->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static int sc2232_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct sc2232 *sc2232 = to_sc2232(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (fie->index >= sc2232->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static const struct dev_pm_ops sc2232_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) SET_RUNTIME_PM_OPS(sc2232_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) sc2232_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static const struct v4l2_subdev_internal_ops sc2232_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .open = sc2232_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static const struct v4l2_subdev_core_ops sc2232_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) .s_power = sc2232_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .ioctl = sc2232_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .compat_ioctl32 = sc2232_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static const struct v4l2_subdev_video_ops sc2232_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .s_stream = sc2232_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .g_frame_interval = sc2232_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static const struct v4l2_subdev_pad_ops sc2232_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .enum_mbus_code = sc2232_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) .enum_frame_size = sc2232_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .enum_frame_interval = sc2232_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) .get_fmt = sc2232_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .set_fmt = sc2232_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .get_mbus_config = sc2232_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static const struct v4l2_subdev_ops sc2232_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .core = &sc2232_core_ops, /* v4l2_subdev_core_ops sc2232_core_ops */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .video = &sc2232_video_ops, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .pad = &sc2232_pad_ops, /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static void sc2232_modify_fps_info(struct sc2232 *sc2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) const struct sc2232_mode *mode = sc2232->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) sc2232->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) sc2232->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static int sc2232_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) struct sc2232 *sc2232 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct sc2232, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct i2c_client *client = sc2232->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) max = sc2232->cur_mode->height + ctrl->val - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) __v4l2_ctrl_modify_range(sc2232->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) sc2232->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) sc2232->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) sc2232->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (sc2232->cur_mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) val = ctrl->val << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ret = sc2232_write_reg(sc2232->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) SC2232_REG_EXP_LONG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) SC2232_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) (val << 4 & 0XF0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ret |= sc2232_write_reg(sc2232->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) SC2232_REG_EXP_LONG_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) SC2232_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) (val >> 4 & 0XFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) ret |= sc2232_write_reg(sc2232->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) SC2232_REG_EXP_LONG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) SC2232_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) (val >> 12 & 0X0F));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) dev_dbg(&client->dev, "set exposure 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (sc2232->cur_mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ret = sc2232_set_gain(sc2232, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ret = sc2232_write_reg(sc2232->client, SC2232_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) SC2232_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) ctrl->val + sc2232->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) sc2232->cur_vts = ctrl->val + sc2232->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (sc2232->cur_vts != sc2232->cur_mode->vts_def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) sc2232_modify_fps_info(sc2232);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) dev_dbg(&client->dev, "set vblank 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ret = sc2232_read_reg(sc2232->client, SC2232_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) SC2232_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) val |= SC2232_MIRROR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) val &= ~SC2232_MIRROR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ret |= sc2232_write_reg(sc2232->client, SC2232_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) SC2232_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ret = sc2232_read_reg(sc2232->client, SC2232_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) SC2232_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) val |= SC2232_FLIP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) val &= ~SC2232_FLIP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) ret |= sc2232_write_reg(sc2232->client, SC2232_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) SC2232_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static const struct v4l2_ctrl_ops sc2232_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .s_ctrl = sc2232_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) static int sc2232_initialize_controls(struct sc2232 *sc2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) const struct sc2232_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) handler = &sc2232->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) mode = sc2232->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) handler->lock = &sc2232->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) sc2232->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) ARRAY_SIZE(link_freq_items) - 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) link_freq_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) __v4l2_ctrl_s_ctrl(sc2232->link_freq, mode->mipi_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) pixel_rate = (u32)link_freq_items[mode->mipi_freq_idx] / mode->bpp * 2 * SC2232_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) sc2232->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) V4L2_CID_PIXEL_RATE, 0, SC2232_MAX_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) 1, pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) sc2232->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (sc2232->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) sc2232->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) sc2232->vblank = v4l2_ctrl_new_std(handler, &sc2232_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) SC2232_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) exposure_max = mode->vts_def - 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) sc2232->exposure = v4l2_ctrl_new_std(handler, &sc2232_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) V4L2_CID_EXPOSURE, SC2232_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) exposure_max, SC2232_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) sc2232->anal_gain = v4l2_ctrl_new_std(handler, &sc2232_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) V4L2_CID_ANALOGUE_GAIN, SC2232_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) SC2232_GAIN_MAX, SC2232_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) SC2232_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) v4l2_ctrl_new_std(handler, &sc2232_ctrl_ops, V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) v4l2_ctrl_new_std(handler, &sc2232_ctrl_ops, V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) dev_err(&sc2232->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) sc2232->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) sc2232->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) sc2232->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) sc2232->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) static int sc2232_check_sensor_id(struct sc2232 *sc2232,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) struct device *dev = &sc2232->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) ret = sc2232_read_reg(client, SC2232_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) SC2232_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) dev_info(dev, "Detected SC%04x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static int sc2232_configure_regulators(struct sc2232 *sc2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) for (i = 0; i < SC2232_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) sc2232->supplies[i].supply = sc2232_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return devm_regulator_bulk_get(&sc2232->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) SC2232_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) sc2232->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static int sc2232_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) struct sc2232 *sc2232;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) sc2232 = devm_kzalloc(dev, sizeof(*sc2232), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (!sc2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) &sc2232->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) &sc2232->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) &sc2232->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) &sc2232->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) ret = of_property_read_u32(node, OF_CAMERA_HDR_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) hdr_mode = NO_HDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) dev_warn(dev, " Get hdr mode failed! no hdr default\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) sc2232->cfg_num = ARRAY_SIZE(supported_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) for (i = 0; i < sc2232->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) sc2232->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) sc2232->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) sc2232->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (IS_ERR(sc2232->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) sc2232->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) if (IS_ERR(sc2232->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) sc2232->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (IS_ERR(sc2232->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) sc2232->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (!IS_ERR(sc2232->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) sc2232->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) pinctrl_lookup_state(sc2232->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (IS_ERR(sc2232->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) sc2232->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) pinctrl_lookup_state(sc2232->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (IS_ERR(sc2232->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) ret = sc2232_configure_regulators(sc2232);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) mutex_init(&sc2232->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) sd = &sc2232->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) v4l2_i2c_subdev_init(sd, client, &sc2232_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) ret = sc2232_initialize_controls(sc2232);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ret = __sc2232_power_on(sc2232);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) ret = sc2232_check_sensor_id(sc2232, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) sd->internal_ops = &sc2232_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) sc2232->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) ret = media_entity_pads_init(&sd->entity, 1, &sc2232->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) if (strcmp(sc2232->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) sc2232->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) SC2232_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) #ifdef USED_SYS_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) add_sysfs_interfaces(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) __sc2232_power_off(sc2232);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) v4l2_ctrl_handler_free(&sc2232->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) mutex_destroy(&sc2232->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) static int sc2232_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct sc2232 *sc2232 = to_sc2232(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) v4l2_ctrl_handler_free(&sc2232->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) mutex_destroy(&sc2232->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) __sc2232_power_off(sc2232);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) static const struct of_device_id sc2232_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) { .compatible = "smartsens,sc2232" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) MODULE_DEVICE_TABLE(of, sc2232_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) static const struct i2c_device_id sc2232_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) { "smartsens,sc2232", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) static struct i2c_driver sc2232_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .name = SC2232_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .pm = &sc2232_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) .of_match_table = of_match_ptr(sc2232_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .probe = &sc2232_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .remove = &sc2232_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .id_table = sc2232_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) #ifdef CONFIG_ROCKCHIP_THUNDER_BOOT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) module_i2c_driver(sc2232_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) return i2c_add_driver(&sc2232_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) i2c_del_driver(&sc2232_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) MODULE_DESCRIPTION("Smartsens sc2232 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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