^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sc200ai driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 fix gain range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X04 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X05 add quick stream on/off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * V0.0X01.0X06 fix set vflip/hflip failed bug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * V0.0X01.0X07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * 1. fix set double times exposue value failed issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * 2. add some debug info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include "../platform/rockchip/isp/rkisp_tb_helper.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SC200AI_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SC200AI_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SC200AI_LINK_FREQ_371 371250000// 742.5Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PIXEL_RATE_WITH_371M_10BIT (SC200AI_LINK_FREQ_371 * 2 * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) SC200AI_LANES / SC200AI_BITS_PER_SAMPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SC200AI_XVCLK_FREQ 27000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CHIP_ID 0xcb1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SC200AI_REG_CHIP_ID 0x3107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SC200AI_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SC200AI_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SC200AI_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SC200AI_REG_EXPOSURE_H 0x3e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SC200AI_REG_EXPOSURE_M 0x3e01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SC200AI_REG_EXPOSURE_L 0x3e02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SC200AI_REG_SEXPOSURE_H 0x3e22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SC200AI_REG_SEXPOSURE_M 0x3e04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SC200AI_REG_SEXPOSURE_L 0x3e05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SC200AI_EXPOSURE_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC200AI_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SC200AI_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SC200AI_REG_DIG_GAIN 0x3e06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SC200AI_REG_DIG_FINE_GAIN 0x3e07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SC200AI_REG_ANA_GAIN 0x3e08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SC200AI_REG_ANA_FINE_GAIN 0x3e09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SC200AI_REG_SDIG_GAIN 0x3e10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SC200AI_REG_SDIG_FINE_GAIN 0x3e11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SC200AI_REG_SANA_GAIN 0x3e12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SC200AI_REG_SANA_FINE_GAIN 0x3e13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SC200AI_GAIN_MIN 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SC200AI_GAIN_MAX (54 * 32 * 64) //53.975*31.75*64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SC200AI_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SC200AI_GAIN_DEFAULT 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SC200AI_LGAIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SC200AI_SGAIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SC200AI_REG_GROUP_HOLD 0x3812
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SC200AI_GROUP_HOLD_START 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SC200AI_GROUP_HOLD_END 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SC200AI_REG_HIGH_TEMP_H 0x3974
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SC200AI_REG_HIGH_TEMP_L 0x3975
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SC200AI_REG_TEST_PATTERN 0x4501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SC200AI_TEST_PATTERN_BIT_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SC200AI_REG_VTS_H 0x320e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SC200AI_REG_VTS_L 0x320f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SC200AI_FLIP_MIRROR_REG 0x3221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SC200AI_FETCH_EXP_H(VAL) (((VAL) >> 12) & 0xF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SC200AI_FETCH_EXP_M(VAL) (((VAL) >> 4) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SC200AI_FETCH_EXP_L(VAL) (((VAL) & 0xF) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SC200AI_FETCH_AGAIN_H(VAL) (((VAL) >> 8) & 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SC200AI_FETCH_AGAIN_L(VAL) ((VAL) & 0xFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SC200AI_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x06 : VAL & 0xf9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SC200AI_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x60 : VAL & 0x9f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define REG_DELAY 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SC200AI_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SC200AI_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SC200AI_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SC200AI_NAME "sc200ai"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const char * const sc200ai_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define SC200AI_NUM_SUPPLIES ARRAY_SIZE(sc200ai_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct sc200ai_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct sc200ai {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct regulator_bulk_data supplies[SC200AI_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct v4l2_fract cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) const struct sc200ai_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) bool is_thunderboot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) bool is_first_streamoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define to_sc200ai(sd) container_of(sd, struct sc200ai, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct regval sc200ai_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * max_framerate 60fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * mipi_datarate per lane 1008Mbps, 4lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static const struct regval sc200ai_linear_10_1920x1080_60fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x301f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3243, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3248, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3249, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3253, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3271, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3301, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3302, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x3303, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3304, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3306, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3308, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3309, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x330b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x330d, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x330e, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x330f, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3310, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x331c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x331e, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x331f, 0x61},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3320, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3333, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x334c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3356, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3364, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3390, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3391, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3392, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3393, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3394, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3395, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3396, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3397, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3398, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3399, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x339a, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x339b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x339c, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x33ac, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x33ae, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x33af, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3621, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x3622, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x3630, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x3637, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x363a, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x363b, 0xc6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x363c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3670, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3674, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3675, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3676, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x367c, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x367d, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x3690, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3691, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3692, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x369c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x369d, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x36eb, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x36ec, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x36fd, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3901, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3904, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3908, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x391f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3e01, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3e02, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3e16, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x3e17, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3f09, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x4819, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x481b, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x481d, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x481f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x4821, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x4823, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x4825, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x4827, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x4829, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x5787, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x5788, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x578a, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x578b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x5790, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x5791, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x5792, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x5793, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x5794, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x5795, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x5799, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x57c7, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x57c8, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x57ca, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x57cb, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x57d1, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x57d4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x57d9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x59e0, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x59e1, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x59e2, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x59e3, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x59e4, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x59e5, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x59e6, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x59e7, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x59e8, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x59e9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x59ea, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x59eb, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x59ec, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x59ed, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x59ee, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x59ef, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x59f4, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x59f5, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x59f6, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x59f7, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x59f8, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x59f9, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x59fa, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x59fb, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x59fc, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x59fd, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x59fe, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x59ff, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x36e9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x36f9, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Xclk 27Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * mipi_datarate per lane 371.25Mbps, 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct regval sc200ai_linear_10_1920x1080_30fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x301f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) //HTS=1100*2=2200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x320c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x320d, 0x4c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) //VTS=1125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x320e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x320f, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x3243, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x3248, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x3249, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x3253, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x3271, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x3301, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x3304, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x3306, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x330b, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x330f, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x331e, 0x39},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x3333, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x3621, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x3622, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x3637, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x363a, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x363b, 0xc6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x363c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x3670, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x3674, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x3675, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x3676, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x367c, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x367d, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x3690, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x3691, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x3692, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x369c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x369d, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x3901, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x3904, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x3908, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x391d, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x391f, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x3e01, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x3e02, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x3e16, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x3e17, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x3f09, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x5787, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x5788, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x578a, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x578b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x5790, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x5791, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x5792, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x5793, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x5794, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x5795, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x5799, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x57c7, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x57c8, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x57ca, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x57cb, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x57d1, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x57d4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x57d9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x59e0, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x59e1, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x59e2, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x59e3, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x59e4, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x59e5, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x59e6, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x59e7, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x59e8, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x59e9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x59ea, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x59eb, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x59ec, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x59ed, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x59ee, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x59ef, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x59f4, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x59f5, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x59f6, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x59f7, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x59f8, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x59f9, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x59fa, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x59fb, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x59fc, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x59fd, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x59fe, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x59ff, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x36e9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x36f9, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * Xclk 27Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * mipi_datarate per lane 742.5Mbps, HDR 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static const struct regval sc200ai_hdr_10_1920x1080_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x301f, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) //HTS=1100*2=2200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x320c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x320d, 0x4c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) //VTS =2252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x320e, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x320f, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x3220, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x3243, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x3248, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x3249, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x3250, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x3253, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x3271, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x3301, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x3302, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x3303, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x3304, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x3306, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x3308, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x3309, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x330b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {0x330d, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {0x330e, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) {0x330f, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x3310, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x331c, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x331e, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x331f, 0x61},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x3320, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x3333, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x3347, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x334c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x3356, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x3364, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x336c, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x3390, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x3391, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x3392, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x3393, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x3394, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x3395, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x3396, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x3397, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x3398, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x3399, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x339a, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x339b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x339c, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x33ac, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x33ae, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x33af, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x3621, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x3622, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x3630, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x3637, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x363a, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x363b, 0xc6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x363c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x3670, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x3674, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x3675, 0x76},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x3676, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x367c, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x367d, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x3690, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x3691, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x3692, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x369c, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x369d, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x36eb, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x36ec, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {0x36fd, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {0x3901, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {0x3904, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x3908, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x391f, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x3e00, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x3e01, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x3e02, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x3e04, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x3e05, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x3e06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x3e07, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x3e08, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x3e09, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x3e10, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x3e11, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x3e12, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x3e13, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x3e16, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {0x3e17, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {0x3e23, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {0x3e24, 0x9e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {0x3f09, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {0x4816, 0xb1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {0x4819, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {0x481b, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {0x481d, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {0x481f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {0x4821, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) {0x4823, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {0x4825, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {0x4827, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {0x4829, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {0x5787, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {0x5788, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {0x578a, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {0x578b, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {0x5790, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {0x5791, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) {0x5792, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {0x5793, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {0x5794, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {0x5795, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {0x5799, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {0x57c7, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {0x57c8, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {0x57ca, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {0x57cb, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {0x57d1, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {0x57d4, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {0x57d9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {0x59e0, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {0x59e1, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) {0x59e2, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {0x59e3, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {0x59e4, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {0x59e5, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {0x59e6, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {0x59e7, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {0x59e8, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {0x59e9, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {0x59ea, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {0x59eb, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {0x59ec, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {0x59ed, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {0x59ee, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {0x59ef, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {0x59f4, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {0x59f5, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {0x59f6, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) {0x59f7, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {0x59f8, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) {0x59f9, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {0x59fa, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {0x59fb, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {0x59fc, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {0x59fd, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {0x59fe, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {0x59ff, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {0x36e9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {0x36f9, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) static const struct sc200ai_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .exp_def = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) .hts_def = 0x44C * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) .vts_def = 0x0465,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .reg_list = sc200ai_linear_10_1920x1080_30fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) .exp_def = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) .hts_def = 0x44C * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) .vts_def = 0x0465,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) .reg_list = sc200ai_linear_10_1920x1080_60fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .exp_def = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .hts_def = 0x44C * 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) .vts_def = 0x08CC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) .reg_list = sc200ai_hdr_10_1920x1080_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) SC200AI_LINK_FREQ_371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static const char * const sc200ai_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static int sc200ai_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static int sc200ai_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ret = sc200ai_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) SC200AI_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static int sc200ai_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* mode: 0 = lgain 1 = sgain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static int sc200ai_set_gain_reg(struct sc200ai *sc200ai, u32 gain, int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) u8 Coarse_gain = 1, DIG_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) u32 Dcg_gainx100 = 1, ANA_Fine_gainx64 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u8 Coarse_gain_reg = 0, DIG_gain_reg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u8 ANA_Fine_gain_reg = 0x20, DIG_Fine_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) gain = gain * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (gain <= 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) gain = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) else if (gain > SC200AI_GAIN_MAX * 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) gain = SC200AI_GAIN_MAX * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (gain < 2 * 1024) { // start again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) Dcg_gainx100 = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) Coarse_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) DIG_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) Coarse_gain_reg = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) DIG_gain_reg = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) DIG_Fine_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) } else if (gain <= 3456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) Dcg_gainx100 = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) Coarse_gain = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) DIG_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) Coarse_gain_reg = 0x07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) DIG_gain_reg = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) DIG_Fine_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) } else if (gain <= 6908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) Dcg_gainx100 = 340;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) Coarse_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) DIG_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) Coarse_gain_reg = 0x23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) DIG_gain_reg = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) DIG_Fine_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) } else if (gain <= 13817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) Dcg_gainx100 = 340;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) Coarse_gain = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) DIG_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) Coarse_gain_reg = 0x27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) DIG_gain_reg = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) DIG_Fine_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) } else if (gain <= 27635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) Dcg_gainx100 = 340;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) Coarse_gain = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) DIG_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) Coarse_gain_reg = 0x2f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) DIG_gain_reg = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) DIG_Fine_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) } else if (gain <= 55270) { // end again
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) Dcg_gainx100 = 340;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) Coarse_gain = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) DIG_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) Coarse_gain_reg = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) DIG_gain_reg = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) DIG_Fine_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) } else if (gain < 55270 * 2) { // start dgain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) Dcg_gainx100 = 340;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) Coarse_gain = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) DIG_gain = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ANA_Fine_gainx64 = 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) Coarse_gain_reg = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) DIG_gain_reg = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ANA_Fine_gain_reg = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) } else if (gain < 55270 * 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) Dcg_gainx100 = 340;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) Coarse_gain = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) DIG_gain = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ANA_Fine_gainx64 = 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) Coarse_gain_reg = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) DIG_gain_reg = 0x1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ANA_Fine_gain_reg = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) } else if (gain < 55270 * 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) Dcg_gainx100 = 340;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) Coarse_gain = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) DIG_gain = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ANA_Fine_gainx64 = 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) Coarse_gain_reg = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) DIG_gain_reg = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ANA_Fine_gain_reg = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) } else if (gain < 55270 * 16) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) Dcg_gainx100 = 340;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) Coarse_gain = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) DIG_gain = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ANA_Fine_gainx64 = 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) Coarse_gain_reg = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) DIG_gain_reg = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) ANA_Fine_gain_reg = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) } else if (gain <= 1754822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) Dcg_gainx100 = 340;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) Coarse_gain = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) DIG_gain = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) ANA_Fine_gainx64 = 127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) Coarse_gain_reg = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) DIG_gain_reg = 0xF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ANA_Fine_gain_reg = 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (gain < 3456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ANA_Fine_gain_reg = abs(100 * gain / (Dcg_gainx100 * Coarse_gain) / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) else if (gain == 3456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ANA_Fine_gain_reg = 0x6C;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) else if (gain < 55270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ANA_Fine_gain_reg = abs(100 * gain / (Dcg_gainx100 * Coarse_gain) / 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) DIG_Fine_gain_reg = abs(800 * gain / (Dcg_gainx100 * Coarse_gain *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) DIG_gain) / ANA_Fine_gainx64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (mode == SC200AI_LGAIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ret = sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) SC200AI_REG_DIG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) DIG_gain_reg & 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ret |= sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) SC200AI_REG_DIG_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) DIG_Fine_gain_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ret |= sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) SC200AI_REG_ANA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) Coarse_gain_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) ret |= sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) SC200AI_REG_ANA_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ANA_Fine_gain_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) SC200AI_REG_SDIG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) DIG_gain_reg & 0xF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ret |= sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) SC200AI_REG_SDIG_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) DIG_Fine_gain_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ret |= sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) SC200AI_REG_SANA_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) Coarse_gain_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ret |= sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) SC200AI_REG_SANA_FINE_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ANA_Fine_gain_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (gain <= 20 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) ret |= sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) 0x5799,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) else if (gain >= 30 * 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ret |= sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) 0x5799,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) 0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) static int sc200ai_set_hdrae(struct sc200ai *sc200ai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) u32 l_exp_time, m_exp_time, s_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) u32 l_a_gain, m_a_gain, s_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (!sc200ai->has_init_exp && !sc200ai->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) sc200ai->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) sc200ai->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dev_dbg(&sc200ai->client->dev, "sc200ai don't stream, record exp for hdr!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) l_exp_time = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) m_exp_time = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) s_exp_time = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) l_a_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) m_a_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) s_a_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) dev_dbg(&sc200ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) l_exp_time, m_exp_time, s_exp_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) l_a_gain, m_a_gain, s_a_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (sc200ai->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) //2 stagger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) l_a_gain = m_a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) l_exp_time = m_exp_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) //set exposure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) l_exp_time = l_exp_time * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) s_exp_time = s_exp_time * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (l_exp_time > 4362) //(2250 - 64 - 5) * 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) l_exp_time = 4362;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (s_exp_time > 404) //(64 - 5) * 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) s_exp_time = 404;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ret = sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) SC200AI_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) SC200AI_FETCH_EXP_H(l_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) ret |= sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) SC200AI_REG_EXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) SC200AI_FETCH_EXP_M(l_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ret |= sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) SC200AI_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) SC200AI_FETCH_EXP_L(l_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ret |= sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) SC200AI_REG_SEXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) SC200AI_FETCH_EXP_M(s_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ret |= sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) SC200AI_REG_SEXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) SC200AI_FETCH_EXP_L(s_exp_time));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) ret |= sc200ai_set_gain_reg(sc200ai, l_a_gain, SC200AI_LGAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) ret |= sc200ai_set_gain_reg(sc200ai, s_a_gain, SC200AI_SGAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static int sc200ai_get_reso_dist(const struct sc200ai_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static const struct sc200ai_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) sc200ai_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) dist = sc200ai_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) static int sc200ai_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct sc200ai *sc200ai = to_sc200ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) const struct sc200ai_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) mutex_lock(&sc200ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) mode = sc200ai_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) mutex_unlock(&sc200ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) sc200ai->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) __v4l2_ctrl_modify_range(sc200ai->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) __v4l2_ctrl_modify_range(sc200ai->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) SC200AI_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) sc200ai->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) sc200ai->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) mutex_unlock(&sc200ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static int sc200ai_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct sc200ai *sc200ai = to_sc200ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) const struct sc200ai_mode *mode = sc200ai->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) mutex_lock(&sc200ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) mutex_unlock(&sc200ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* format info: width/height/data type/virctual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) mutex_unlock(&sc200ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static int sc200ai_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct sc200ai *sc200ai = to_sc200ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) code->code = sc200ai->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static int sc200ai_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (fse->code != supported_modes[0].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static int sc200ai_enable_test_pattern(struct sc200ai *sc200ai, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ret = sc200ai_read_reg(sc200ai->client, SC200AI_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) SC200AI_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) val |= SC200AI_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) val &= ~SC200AI_TEST_PATTERN_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) ret |= sc200ai_write_reg(sc200ai->client, SC200AI_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) SC200AI_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) static int sc200ai_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct sc200ai *sc200ai = to_sc200ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) const struct sc200ai_mode *mode = sc200ai->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (sc200ai->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) fi->interval = sc200ai->cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static int sc200ai_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct sc200ai *sc200ai = to_sc200ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) const struct sc200ai_mode *mode = sc200ai->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) u32 val = 1 << (SC200AI_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) val |= V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) val |= V4L2_MBUS_CSI2_CHANNEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static void sc200ai_get_module_inf(struct sc200ai *sc200ai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) strlcpy(inf->base.sensor, SC200AI_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) strlcpy(inf->base.module, sc200ai->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) strlcpy(inf->base.lens, sc200ai->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static int sc200ai_get_channel_info(struct sc200ai *sc200ai, struct rkmodule_channel_info *ch_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (ch_info->index < PAD0 || ch_info->index >= PAD_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ch_info->vc = sc200ai->cur_mode->vc[ch_info->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ch_info->width = sc200ai->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ch_info->height = sc200ai->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ch_info->bus_fmt = sc200ai->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static long sc200ai_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct sc200ai *sc200ai = to_sc200ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) sc200ai_get_module_inf(sc200ai, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) hdr->hdr_mode = sc200ai->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) w = sc200ai->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) h = sc200ai->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) sc200ai->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (i == ARRAY_SIZE(supported_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) dev_err(&sc200ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) w = sc200ai->cur_mode->hts_def - sc200ai->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) h = sc200ai->cur_mode->vts_def - sc200ai->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) __v4l2_ctrl_modify_range(sc200ai->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) __v4l2_ctrl_modify_range(sc200ai->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) SC200AI_VTS_MAX - sc200ai->cur_mode->height, 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) sc200ai->cur_fps = sc200ai->cur_mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) sc200ai->cur_vts = sc200ai->cur_mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) sc200ai_set_hdrae(sc200ai, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ret = sc200ai_write_reg(sc200ai->client, SC200AI_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) SC200AI_REG_VALUE_08BIT, SC200AI_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) ret = sc200ai_write_reg(sc200ai->client, SC200AI_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) SC200AI_REG_VALUE_08BIT, SC200AI_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) ch_info = (struct rkmodule_channel_info *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) ret = sc200ai_get_channel_info(sc200ai, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) static long sc200ai_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) struct rkmodule_channel_info *ch_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) ret = sc200ai_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) ret = sc200ai_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) ret = sc200ai_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) ret = sc200ai_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) ret = sc200ai_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ret = sc200ai_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) case RKMODULE_GET_CHANNEL_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ch_info = kzalloc(sizeof(*ch_info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (!ch_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) ret = sc200ai_ioctl(sd, cmd, ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) ret = copy_to_user(up, ch_info, sizeof(*ch_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) kfree(ch_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static int __sc200ai_start_stream(struct sc200ai *sc200ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) dev_info(&sc200ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) "%dx%d@%d, mode %d, vts 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) sc200ai->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) sc200ai->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) sc200ai->cur_fps.denominator / sc200ai->cur_fps.numerator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) sc200ai->cur_mode->hdr_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) sc200ai->cur_vts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (!sc200ai->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) ret = sc200ai_write_array(sc200ai->client, sc200ai->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ret = __v4l2_ctrl_handler_setup(&sc200ai->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (sc200ai->has_init_exp && sc200ai->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) ret = sc200ai_ioctl(&sc200ai->subdev, PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) &sc200ai->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) dev_err(&sc200ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) return sc200ai_write_reg(sc200ai->client, SC200AI_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) SC200AI_REG_VALUE_08BIT, SC200AI_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static int __sc200ai_stop_stream(struct sc200ai *sc200ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) sc200ai->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) if (sc200ai->is_thunderboot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) sc200ai->is_first_streamoff = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) return sc200ai_write_reg(sc200ai->client, SC200AI_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) SC200AI_REG_VALUE_08BIT, SC200AI_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static int __sc200ai_power_on(struct sc200ai *sc200ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static int sc200ai_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) struct sc200ai *sc200ai = to_sc200ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) struct i2c_client *client = sc200ai->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) mutex_lock(&sc200ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (on == sc200ai->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (sc200ai->is_thunderboot && rkisp_tb_get_state() == RKISP_TB_NG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) sc200ai->is_thunderboot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) __sc200ai_power_on(sc200ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) ret = __sc200ai_start_stream(sc200ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) __sc200ai_stop_stream(sc200ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) sc200ai->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) mutex_unlock(&sc200ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) static int sc200ai_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) struct sc200ai *sc200ai = to_sc200ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) struct i2c_client *client = sc200ai->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) mutex_lock(&sc200ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (sc200ai->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (!sc200ai->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) ret = sc200ai_write_array(sc200ai->client, sc200ai_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) sc200ai->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) sc200ai->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) mutex_unlock(&sc200ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) static inline u32 sc200ai_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) return DIV_ROUND_UP(cycles, SC200AI_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) static int __sc200ai_power_on(struct sc200ai *sc200ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) struct device *dev = &sc200ai->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (!IS_ERR_OR_NULL(sc200ai->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) ret = pinctrl_select_state(sc200ai->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) sc200ai->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) ret = clk_set_rate(sc200ai->xvclk, SC200AI_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) if (clk_get_rate(sc200ai->xvclk) != SC200AI_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) ret = clk_prepare_enable(sc200ai->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (sc200ai->is_thunderboot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (!IS_ERR(sc200ai->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) gpiod_set_value_cansleep(sc200ai->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) ret = regulator_bulk_enable(SC200AI_NUM_SUPPLIES, sc200ai->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) if (!IS_ERR(sc200ai->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) gpiod_set_value_cansleep(sc200ai->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) if (!IS_ERR(sc200ai->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) gpiod_set_value_cansleep(sc200ai->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (!IS_ERR(sc200ai->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) usleep_range(6000, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) usleep_range(12000, 16000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) delay_us = sc200ai_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) clk_disable_unprepare(sc200ai->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) static void __sc200ai_power_off(struct sc200ai *sc200ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) struct device *dev = &sc200ai->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) clk_disable_unprepare(sc200ai->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (sc200ai->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) if (sc200ai->is_first_streamoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) sc200ai->is_thunderboot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) sc200ai->is_first_streamoff = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (!IS_ERR(sc200ai->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) gpiod_set_value_cansleep(sc200ai->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) clk_disable_unprepare(sc200ai->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) if (!IS_ERR(sc200ai->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) gpiod_set_value_cansleep(sc200ai->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (!IS_ERR_OR_NULL(sc200ai->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) ret = pinctrl_select_state(sc200ai->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) sc200ai->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) regulator_bulk_disable(SC200AI_NUM_SUPPLIES, sc200ai->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) static int sc200ai_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) struct sc200ai *sc200ai = to_sc200ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) return __sc200ai_power_on(sc200ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) static int sc200ai_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) struct sc200ai *sc200ai = to_sc200ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) __sc200ai_power_off(sc200ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) static int sc200ai_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) struct sc200ai *sc200ai = to_sc200ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) const struct sc200ai_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) mutex_lock(&sc200ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) mutex_unlock(&sc200ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) static int sc200ai_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) static const struct dev_pm_ops sc200ai_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) SET_RUNTIME_PM_OPS(sc200ai_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) sc200ai_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) static const struct v4l2_subdev_internal_ops sc200ai_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .open = sc200ai_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) static const struct v4l2_subdev_core_ops sc200ai_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .s_power = sc200ai_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .ioctl = sc200ai_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .compat_ioctl32 = sc200ai_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) static const struct v4l2_subdev_video_ops sc200ai_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .s_stream = sc200ai_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .g_frame_interval = sc200ai_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) static const struct v4l2_subdev_pad_ops sc200ai_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .enum_mbus_code = sc200ai_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .enum_frame_size = sc200ai_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .enum_frame_interval = sc200ai_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .get_fmt = sc200ai_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .set_fmt = sc200ai_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .get_mbus_config = sc200ai_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) static const struct v4l2_subdev_ops sc200ai_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) .core = &sc200ai_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .video = &sc200ai_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .pad = &sc200ai_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static void sc200ai_modify_fps_info(struct sc200ai *sc200ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) const struct sc200ai_mode *mode = sc200ai->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) sc200ai->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) sc200ai->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) static int sc200ai_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) struct sc200ai *sc200ai = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) struct sc200ai, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) struct i2c_client *client = sc200ai->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) s32 temp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) max = sc200ai->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) __v4l2_ctrl_modify_range(sc200ai->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) sc200ai->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) sc200ai->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) sc200ai->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) dev_dbg(&client->dev, "set exposure value 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (sc200ai->cur_mode->hdr_mode == NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) temp = ctrl->val * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) ret = sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) SC200AI_REG_EXPOSURE_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) SC200AI_FETCH_EXP_H(temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) ret |= sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) SC200AI_REG_EXPOSURE_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) SC200AI_FETCH_EXP_M(temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) ret |= sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) SC200AI_REG_EXPOSURE_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) SC200AI_FETCH_EXP_L(temp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) dev_dbg(&client->dev, "set gain value 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) if (sc200ai->cur_mode->hdr_mode == NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) ret = sc200ai_set_gain_reg(sc200ai, ctrl->val, SC200AI_LGAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) dev_dbg(&client->dev, "set blank value 0x%x\n", ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) ret = sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) SC200AI_REG_VTS_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) (ctrl->val + sc200ai->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) ret |= sc200ai_write_reg(sc200ai->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) SC200AI_REG_VTS_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) (ctrl->val + sc200ai->cur_mode->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) sc200ai->cur_vts = ctrl->val + sc200ai->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) if (sc200ai->cur_vts != sc200ai->cur_mode->vts_def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) sc200ai_modify_fps_info(sc200ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) ret = sc200ai_enable_test_pattern(sc200ai, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) ret = sc200ai_read_reg(sc200ai->client, SC200AI_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) SC200AI_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) ret |= sc200ai_write_reg(sc200ai->client, SC200AI_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) SC200AI_FETCH_MIRROR(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) ret = sc200ai_read_reg(sc200ai->client, SC200AI_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) SC200AI_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) ret |= sc200ai_write_reg(sc200ai->client, SC200AI_FLIP_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) SC200AI_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) SC200AI_FETCH_FLIP(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) static const struct v4l2_ctrl_ops sc200ai_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) .s_ctrl = sc200ai_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) static int sc200ai_initialize_controls(struct sc200ai *sc200ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) const struct sc200ai_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) handler = &sc200ai->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) mode = sc200ai->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) handler->lock = &sc200ai->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) 0, PIXEL_RATE_WITH_371M_10BIT, 1, PIXEL_RATE_WITH_371M_10BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) sc200ai->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (sc200ai->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) sc200ai->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) sc200ai->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) sc200ai->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) sc200ai->vblank = v4l2_ctrl_new_std(handler, &sc200ai_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) SC200AI_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) exposure_max = 2 * mode->vts_def - 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) sc200ai->exposure = v4l2_ctrl_new_std(handler, &sc200ai_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) V4L2_CID_EXPOSURE, SC200AI_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) exposure_max, SC200AI_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) sc200ai->anal_gain = v4l2_ctrl_new_std(handler, &sc200ai_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) V4L2_CID_ANALOGUE_GAIN, SC200AI_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) SC200AI_GAIN_MAX, SC200AI_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) SC200AI_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) sc200ai->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) &sc200ai_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) ARRAY_SIZE(sc200ai_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) 0, 0, sc200ai_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) v4l2_ctrl_new_std(handler, &sc200ai_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) v4l2_ctrl_new_std(handler, &sc200ai_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) dev_err(&sc200ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) sc200ai->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) sc200ai->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) static int sc200ai_check_sensor_id(struct sc200ai *sc200ai,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) struct device *dev = &sc200ai->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) if (sc200ai->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) ret = sc200ai_read_reg(client, SC200AI_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) SC200AI_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) static int sc200ai_configure_regulators(struct sc200ai *sc200ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) for (i = 0; i < SC200AI_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) sc200ai->supplies[i].supply = sc200ai_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) return devm_regulator_bulk_get(&sc200ai->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) SC200AI_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) sc200ai->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) #ifdef CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) static u32 rk_cam_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) static u32 rk_cam_w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) static u32 rk_cam_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) static u32 rk_cam_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) static int __init __maybe_unused rk_cam_hdr_setup(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) unsigned long val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) ret = kstrtoul(str, 0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) rk_cam_hdr = (u32)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) pr_err("get rk_cam_hdr fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) static int __init __maybe_unused rk_cam_w_setup(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) unsigned long val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) ret = kstrtoul(str, 0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) rk_cam_w = (u32)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) pr_err("get rk_cam_w fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) static int __init __maybe_unused rk_cam_h_setup(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) unsigned long val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) ret = kstrtoul(str, 0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) rk_cam_h = (u32)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) pr_err("get rk_cam_h fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) static int __init __maybe_unused rk_cam_fps_setup(char *str)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) unsigned long val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) ret = kstrtoul(str, 0, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) rk_cam_fps = (u32)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) pr_err("get rk_cam_fps fail\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) __setup("rk_cam_hdr=", rk_cam_hdr_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) __setup("rk_cam_w=", rk_cam_w_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) __setup("rk_cam_h=", rk_cam_h_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) __setup("rk_cam_fps=", rk_cam_fps_setup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) static void find_terminal_resolution(struct sc200ai *sc200ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) const struct sc200ai_mode *mode = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) const struct sc200ai_mode *fit_mode = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) u32 cur_fps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) u32 dst_fps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) u32 tmp_fps = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (rk_cam_w == 0 || rk_cam_h == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) rk_cam_fps == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) goto err_find_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) dst_fps = rk_cam_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) cur_fps = mode->max_fps.denominator / mode->max_fps.numerator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (mode->width == rk_cam_w && mode->height == rk_cam_h &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) mode->hdr_mode == rk_cam_hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) if (cur_fps == dst_fps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) sc200ai->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) if (cur_fps >= dst_fps) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) if (fit_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) tmp_fps = fit_mode->max_fps.denominator / fit_mode->max_fps.numerator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if (tmp_fps - dst_fps > cur_fps - dst_fps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) fit_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) fit_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) if (fit_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) sc200ai->cur_mode = fit_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) err_find_res:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) dev_err(&sc200ai->client->dev, "not match %dx%d@%dfps mode %d\n!",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) rk_cam_w, rk_cam_h, dst_fps, rk_cam_hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) sc200ai->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) static void find_terminal_resolution(struct sc200ai *sc200ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) u32 hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) struct device_node *node = sc200ai->client->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) sc200ai->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) if (i == ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) sc200ai->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) static int sc200ai_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) struct sc200ai *sc200ai;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) sc200ai = devm_kzalloc(dev, sizeof(*sc200ai), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) if (!sc200ai)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) &sc200ai->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) &sc200ai->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) &sc200ai->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) &sc200ai->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) sc200ai->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) sc200ai->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) find_terminal_resolution(sc200ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) sc200ai->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) if (IS_ERR(sc200ai->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) sc200ai->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) if (IS_ERR(sc200ai->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) sc200ai->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) if (IS_ERR(sc200ai->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) sc200ai->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) if (!IS_ERR(sc200ai->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) sc200ai->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) pinctrl_lookup_state(sc200ai->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) if (IS_ERR(sc200ai->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) sc200ai->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) pinctrl_lookup_state(sc200ai->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) if (IS_ERR(sc200ai->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) ret = sc200ai_configure_regulators(sc200ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) mutex_init(&sc200ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) sd = &sc200ai->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) v4l2_i2c_subdev_init(sd, client, &sc200ai_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) ret = sc200ai_initialize_controls(sc200ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) ret = __sc200ai_power_on(sc200ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) ret = sc200ai_check_sensor_id(sc200ai, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) sd->internal_ops = &sc200ai_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) sc200ai->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) ret = media_entity_pads_init(&sd->entity, 1, &sc200ai->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) if (strcmp(sc200ai->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) sc200ai->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) SC200AI_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) __sc200ai_power_off(sc200ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) v4l2_ctrl_handler_free(&sc200ai->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) mutex_destroy(&sc200ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) static int sc200ai_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) struct sc200ai *sc200ai = to_sc200ai(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) v4l2_ctrl_handler_free(&sc200ai->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) mutex_destroy(&sc200ai->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) __sc200ai_power_off(sc200ai);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) static const struct of_device_id sc200ai_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) { .compatible = "smartsens,sc200ai" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) MODULE_DEVICE_TABLE(of, sc200ai_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) static const struct i2c_device_id sc200ai_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) { "smartsens,sc200ai", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) static struct i2c_driver sc200ai_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) .name = SC200AI_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) .pm = &sc200ai_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) .of_match_table = of_match_ptr(sc200ai_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) .probe = &sc200ai_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .remove = &sc200ai_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .id_table = sc200ai_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) return i2c_add_driver(&sc200ai_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) i2c_del_driver(&sc200ai_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) #if defined(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP) && !defined(CONFIG_INITCALL_ASYNC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) subsys_initcall(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) MODULE_DESCRIPTION("smartsens sc200ai sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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