^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sc132gs driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * V0.1.0: MIPI is ok.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X03 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X04 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X05 add function g_mbus_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X06 add function reset gpio control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * V0.0X01.0X06 add 2-lane mode as default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MIPI_FREQ_180M 180000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MIPI_FREQ_360M 360000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PIXEL_RATE_WITH_180M (MIPI_FREQ_180M * 2 / 10 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PIXEL_RATE_WITH_360M (MIPI_FREQ_360M * 2 / 8 * 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SC132GS_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CHIP_ID 0x0132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SC132GS_REG_CHIP_ID 0x3107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SC132GS_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SC132GS_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SC132GS_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SC132GS_REG_EXPOSURE 0x3e01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SC132GS_EXPOSURE_MIN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SC132GS_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SC132GS_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SC132GS_REG_COARSE_AGAIN 0x3e08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SC132GS_REG_FINE_AGAIN 0x3e09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ANALOG_GAIN_MIN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ANALOG_GAIN_MAX 0x391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ANALOG_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ANALOG_GAIN_DEFAULT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SC132GS_REG_TEST_PATTERN 0x4501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SC132GS_TEST_PATTERN_ENABLE 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC132GS_TEST_PATTERN_DISABLE 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SC132GS_REG_VTS 0x320e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SC132GS_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SC132GS_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SC132GS_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SC132GS_NAME "sc132gs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) static const char * const sc132gs_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SC132GS_NUM_SUPPLIES ARRAY_SIZE(sc132gs_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) LINK_FREQ_180M_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) LINK_FREQ_360M_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct sc132gs_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 link_freq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u64 pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct sc132gs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct regulator_bulk_data supplies[SC132GS_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct v4l2_fract cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const struct sc132gs_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define to_sc132gs(sd) container_of(sd, struct sc132gs, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * Pclk 90Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * linelength 1696(0x06a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * framelength 2122(0x084a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * grabwindow_width 1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * grabwindow_height 1280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * mipi 1 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * mipi_datarate per lane 720Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static const struct regval sc132gs_1lane_8bit_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) //PLL bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x3018, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x3019, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x301a, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x3031, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x3032, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x3038, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x3207, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x320c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x320d, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x320e, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x320f, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x3250, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x3251, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x3252, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x3253, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x3254, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x3255, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x3306, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x330b, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x330f, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x3314, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3315, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x3317, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x331f, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x3364, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3385, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3387, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3389, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x33ab, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x33ac, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x33b1, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x33b2, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x33f8, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x33fa, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3409, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x34f0, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x34f1, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x34f2, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3622, 0xf5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3630, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3631, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3632, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3633, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x3638, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3639, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x363b, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x363c, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x363d, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x36ea, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x36fa, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x36fb, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x36fd, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3900, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3901, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3902, 0xc5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3904, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3908, 0x91},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x391e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3e01, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3e02, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3e09, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3e0e, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3e14, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3e1e, 0x7c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3e26, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x4418, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x4503, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x4837, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x5000, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x540c, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x550f, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x5780, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x5784, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x5785, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x5787, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x5788, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x5789, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x578a, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x578b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x578c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x5790, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x5791, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x5792, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x5793, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x5794, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x5795, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x5799, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3037, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) //PLL set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x36e9, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x36f9, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x0100, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * Pclk 72Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * linelength 1696(0x06a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * framelength 2122(0x084a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * grabwindow_width 1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * grabwindow_height 1280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * mipi 2 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * mipi_datarate per lane 360Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static const struct regval sc132gs_2lane_10bit_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) //PLL bypass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x3018, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x3019, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x301a, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x3031, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x3032, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x3038, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x3207, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x320c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x320d, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x320e, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x320f, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x3250, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3251, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x3252, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x3253, 0x5b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3254, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3255, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x3306, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x330a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x330b, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x330f, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x3314, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x3315, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x3317, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x331f, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3364, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x3385, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3387, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3389, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x33ab, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x33ac, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x33b1, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x33b2, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x33f8, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x33fa, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x3409, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x34f0, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x34f1, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x34f2, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x3622, 0xf5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x3630, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x3631, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x3632, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x3633, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x3638, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x3639, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x363b, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x363c, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x363d, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x36ea, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x36fa, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x36fb, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x36fd, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x3900, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x3901, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x3902, 0xc5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x3904, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x3908, 0x91},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x391e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x3e01, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x3e02, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x3e09, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x3e0e, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x3e14, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x3e1e, 0x7c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x3e26, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x4418, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x4503, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x4837, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x5000, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x540c, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x550f, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x5780, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x5784, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x5785, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x5787, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x5788, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x5789, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x578a, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x578b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x578c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x5790, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x5791, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x5792, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x5793, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x5794, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x5795, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x5799, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) //flip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) //{0x3221, (0x3 << 5)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) //mirror
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x3221, (0x3 << 1)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) //flip & mirror
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) //{0x3221, ((0x3 << 1)|(0x3 << 5))},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) //PLL set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x36e9, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x36f9, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static const struct sc132gs_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .width = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) .height = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) .exp_def = 0x0148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) .hts_def = 0x06a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .vts_def = 0x084a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) .link_freq_index = LINK_FREQ_180M_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) .pixel_rate = PIXEL_RATE_WITH_180M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) .reg_list = sc132gs_2lane_10bit_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) .lanes = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .bus_fmt = MEDIA_BUS_FMT_Y10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .width = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .height = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) .exp_def = 0x0148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .hts_def = 0x06a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .vts_def = 0x084a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .link_freq_index = LINK_FREQ_360M_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .pixel_rate = PIXEL_RATE_WITH_360M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .reg_list = sc132gs_1lane_8bit_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) .lanes = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .bus_fmt = MEDIA_BUS_FMT_Y8_1X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const char * const sc132gs_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MIPI_FREQ_180M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) MIPI_FREQ_360M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int sc132gs_write_reg(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u16 reg, u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) ret = i2c_master_send(client, buf, len + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (ret != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int sc132gs_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) ret = sc132gs_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) SC132GS_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int sc132gs_read_reg(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u16 reg, unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static int sc132gs_get_reso_dist(const struct sc132gs_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const struct sc132gs_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) sc132gs_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dist = sc132gs_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) (supported_modes[i].bus_fmt == framefmt->code)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int sc132gs_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) struct sc132gs *sc132gs = to_sc132gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) const struct sc132gs_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) mutex_lock(&sc132gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) mode = sc132gs_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) mutex_unlock(&sc132gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) sc132gs->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) __v4l2_ctrl_modify_range(sc132gs->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) __v4l2_ctrl_modify_range(sc132gs->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) SC132GS_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) __v4l2_ctrl_s_ctrl_int64(sc132gs->pixel_rate, mode->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) __v4l2_ctrl_s_ctrl(sc132gs->link_freq, mode->link_freq_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) sc132gs->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) sc132gs->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) mutex_unlock(&sc132gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int sc132gs_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct sc132gs *sc132gs = to_sc132gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) const struct sc132gs_mode *mode = sc132gs->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) mutex_lock(&sc132gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) mutex_unlock(&sc132gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) mutex_unlock(&sc132gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int sc132gs_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct sc132gs *sc132gs = to_sc132gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) code->code = sc132gs->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static int sc132gs_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (fse->code != supported_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int sc132gs_enable_test_pattern(struct sc132gs *sc132gs, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) val = (pattern - 1) | SC132GS_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) val = SC132GS_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return sc132gs_write_reg(sc132gs->client, SC132GS_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) SC132GS_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) static void sc132gs_get_module_inf(struct sc132gs *sc132gs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) strlcpy(inf->base.sensor, SC132GS_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) strlcpy(inf->base.module, sc132gs->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) strlcpy(inf->base.lens, sc132gs->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static long sc132gs_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct sc132gs *sc132gs = to_sc132gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) sc132gs_get_module_inf(sc132gs, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ret = sc132gs_write_reg(sc132gs->client, SC132GS_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) SC132GS_REG_VALUE_08BIT, SC132GS_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ret = sc132gs_write_reg(sc132gs->client, SC132GS_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) SC132GS_REG_VALUE_08BIT, SC132GS_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static long sc132gs_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ret = sc132gs_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (copy_from_user(&stream, up, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ret = sc132gs_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static int sc132gs_set_ctrl_gain(struct sc132gs *sc132gs, u32 a_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) u32 coarse_again, fine_again, fine_again_reg, coarse_again_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (a_gain < 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) a_gain = 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) if (a_gain > 0x391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) a_gain = 0x391;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (a_gain < 0x3a) {/*1x~1.813*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) fine_again = a_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) coarse_again = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) fine_again_reg = fine_again & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) coarse_again_reg = coarse_again & 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (fine_again_reg >= 0x39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) fine_again_reg = 0x39;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) } else if (a_gain < 0x72) {/*1.813~3.568x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) fine_again = (a_gain - 0x3a) * 1000 / 1755 + 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) coarse_again = 0x23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (fine_again > 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) fine_again = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) fine_again_reg = fine_again & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) coarse_again_reg = coarse_again & 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) } else if (a_gain < 0xe8) { /*3.568x~7.250x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) fine_again = (a_gain - 0x72) * 1000 / 3682 + 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) coarse_again = 0x27;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (fine_again > 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) fine_again = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) fine_again_reg = fine_again & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) coarse_again_reg = coarse_again & 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) } else if (a_gain < 0x1d0) { /*7.250x~14.5x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) fine_again = (a_gain - 0xe8) * 100 / 725 + 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) coarse_again = 0x2f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (fine_again > 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) fine_again = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) fine_again_reg = fine_again & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) coarse_again_reg = coarse_again & 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) } else { /*14.5x~28.547*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) fine_again = (a_gain - 0x1d0) * 1000 / 14047 + 0x20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) coarse_again = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (fine_again > 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) fine_again = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) fine_again_reg = fine_again & 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) coarse_again_reg = coarse_again & 0x3F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) ret |= sc132gs_write_reg(sc132gs->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) SC132GS_REG_COARSE_AGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) SC132GS_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) coarse_again_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ret |= sc132gs_write_reg(sc132gs->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) SC132GS_REG_FINE_AGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) SC132GS_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) fine_again_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int __sc132gs_start_stream(struct sc132gs *sc132gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ret = sc132gs_write_array(sc132gs->client, sc132gs->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) mutex_unlock(&sc132gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ret = v4l2_ctrl_handler_setup(&sc132gs->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) mutex_lock(&sc132gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return sc132gs_write_reg(sc132gs->client, SC132GS_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) SC132GS_REG_VALUE_08BIT, SC132GS_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static int __sc132gs_stop_stream(struct sc132gs *sc132gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return sc132gs_write_reg(sc132gs->client, SC132GS_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) SC132GS_REG_VALUE_08BIT, SC132GS_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static int sc132gs_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct sc132gs *sc132gs = to_sc132gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct i2c_client *client = sc132gs->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) unsigned int fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) mutex_lock(&sc132gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (on == sc132gs->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) fps = DIV_ROUND_CLOSEST(sc132gs->cur_mode->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) sc132gs->cur_mode->max_fps.numerator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dev_info(&sc132gs->client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) sc132gs->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) sc132gs->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) fps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ret = __sc132gs_start_stream(sc132gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) __sc132gs_stop_stream(sc132gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) sc132gs->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) mutex_unlock(&sc132gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static int sc132gs_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct sc132gs *sc132gs = to_sc132gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct i2c_client *client = sc132gs->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) mutex_lock(&sc132gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (sc132gs->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) sc132gs->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) sc132gs->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) mutex_unlock(&sc132gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static int sc132gs_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct sc132gs *sc132gs = to_sc132gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) const struct sc132gs_mode *mode = sc132gs->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (sc132gs->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) fi->interval = sc132gs->cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static inline u32 sc132gs_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return DIV_ROUND_UP(cycles, SC132GS_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static int __sc132gs_power_on(struct sc132gs *sc132gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct device *dev = &sc132gs->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (!IS_ERR_OR_NULL(sc132gs->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ret = pinctrl_select_state(sc132gs->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) sc132gs->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ret = clk_set_rate(sc132gs->xvclk, SC132GS_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (clk_get_rate(sc132gs->xvclk) != SC132GS_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ret = clk_prepare_enable(sc132gs->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ret = regulator_bulk_enable(SC132GS_NUM_SUPPLIES, sc132gs->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (!IS_ERR(sc132gs->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) gpiod_set_value_cansleep(sc132gs->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (!IS_ERR(sc132gs->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) gpiod_set_value_cansleep(sc132gs->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (!IS_ERR(sc132gs->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) gpiod_set_value_cansleep(sc132gs->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) delay_us = sc132gs_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) clk_disable_unprepare(sc132gs->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static void __sc132gs_power_off(struct sc132gs *sc132gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (!IS_ERR(sc132gs->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) gpiod_set_value_cansleep(sc132gs->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (!IS_ERR(sc132gs->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) gpiod_set_value_cansleep(sc132gs->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) clk_disable_unprepare(sc132gs->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (!IS_ERR_OR_NULL(sc132gs->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ret = pinctrl_select_state(sc132gs->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) sc132gs->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) dev_dbg(&sc132gs->client->dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) regulator_bulk_disable(SC132GS_NUM_SUPPLIES, sc132gs->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static int sc132gs_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct sc132gs *sc132gs = to_sc132gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return __sc132gs_power_on(sc132gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static int sc132gs_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct sc132gs *sc132gs = to_sc132gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) __sc132gs_power_off(sc132gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static int sc132gs_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct sc132gs *sc132gs = to_sc132gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) const struct sc132gs_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) mutex_lock(&sc132gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) mutex_unlock(&sc132gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static int sc132gs_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static int sc132gs_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct sc132gs *sc132gs = to_sc132gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) val = 1 << (sc132gs->cur_mode->lanes - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static const struct dev_pm_ops sc132gs_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) SET_RUNTIME_PM_OPS(sc132gs_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) sc132gs_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static const struct v4l2_subdev_internal_ops sc132gs_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .open = sc132gs_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static const struct v4l2_subdev_core_ops sc132gs_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .s_power = sc132gs_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) .ioctl = sc132gs_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) .compat_ioctl32 = sc132gs_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static const struct v4l2_subdev_video_ops sc132gs_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .s_stream = sc132gs_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .g_frame_interval = sc132gs_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static const struct v4l2_subdev_pad_ops sc132gs_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .enum_mbus_code = sc132gs_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .enum_frame_size = sc132gs_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) .enum_frame_interval = sc132gs_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) .get_fmt = sc132gs_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) .set_fmt = sc132gs_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) .get_mbus_config = sc132gs_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static const struct v4l2_subdev_ops sc132gs_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .core = &sc132gs_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .video = &sc132gs_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .pad = &sc132gs_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) static void sc132gs_modify_fps_info(struct sc132gs *sc132gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) const struct sc132gs_mode *mode = sc132gs->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) sc132gs->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) sc132gs->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) static int sc132gs_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct sc132gs *sc132gs = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct sc132gs, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct i2c_client *client = sc132gs->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) max = sc132gs->cur_mode->height + ctrl->val - 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) __v4l2_ctrl_modify_range(sc132gs->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) sc132gs->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) sc132gs->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) sc132gs->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret = sc132gs_write_reg(sc132gs->client, SC132GS_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) SC132GS_REG_VALUE_16BIT, ctrl->val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) ret = sc132gs_set_ctrl_gain(sc132gs, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) ret = sc132gs_write_reg(sc132gs->client, SC132GS_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) SC132GS_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) ctrl->val + sc132gs->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) sc132gs->cur_vts = ctrl->val + sc132gs->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) if (sc132gs->cur_vts != sc132gs->cur_mode->vts_def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) sc132gs_modify_fps_info(sc132gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ret = sc132gs_enable_test_pattern(sc132gs, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) static const struct v4l2_ctrl_ops sc132gs_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .s_ctrl = sc132gs_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static int sc132gs_initialize_controls(struct sc132gs *sc132gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) const struct sc132gs_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) handler = &sc132gs->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) mode = sc132gs->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) handler->lock = &sc132gs->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) sc132gs->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ARRAY_SIZE(link_freq_menu_items) - 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) sc132gs->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) 0, PIXEL_RATE_WITH_360M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) 1, mode->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) __v4l2_ctrl_s_ctrl(sc132gs->link_freq, mode->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) sc132gs->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (sc132gs->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) sc132gs->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) sc132gs->vblank = v4l2_ctrl_new_std(handler, &sc132gs_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) SC132GS_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) exposure_max = mode->vts_def - 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) sc132gs->exposure = v4l2_ctrl_new_std(handler, &sc132gs_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) V4L2_CID_EXPOSURE, SC132GS_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) exposure_max, SC132GS_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) sc132gs->anal_gain = v4l2_ctrl_new_std(handler, &sc132gs_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) ANALOG_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) sc132gs->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) &sc132gs_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) ARRAY_SIZE(sc132gs_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) 0, 0, sc132gs_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dev_err(&sc132gs->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) sc132gs->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) sc132gs->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) sc132gs->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static int sc132gs_check_sensor_id(struct sc132gs *sc132gs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) struct device *dev = &sc132gs->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) ret = sc132gs_read_reg(client, SC132GS_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) SC132GS_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) dev_info(dev, "Detected SC132GS CHIP ID = 0x%04x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static int sc132gs_configure_regulators(struct sc132gs *sc132gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) for (i = 0; i < SC132GS_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) sc132gs->supplies[i].supply = sc132gs_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) return devm_regulator_bulk_get(&sc132gs->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) SC132GS_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) sc132gs->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) static int sc132gs_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) struct sc132gs *sc132gs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) sc132gs = devm_kzalloc(dev, sizeof(*sc132gs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (!sc132gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) &sc132gs->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) &sc132gs->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) &sc132gs->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) &sc132gs->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) sc132gs->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) sc132gs->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) sc132gs->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (IS_ERR(sc132gs->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) sc132gs->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (IS_ERR(sc132gs->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) sc132gs->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (IS_ERR(sc132gs->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) ret = sc132gs_configure_regulators(sc132gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) sc132gs->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (!IS_ERR(sc132gs->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) sc132gs->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) pinctrl_lookup_state(sc132gs->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (IS_ERR(sc132gs->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) sc132gs->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) pinctrl_lookup_state(sc132gs->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (IS_ERR(sc132gs->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) mutex_init(&sc132gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) sd = &sc132gs->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) v4l2_i2c_subdev_init(sd, client, &sc132gs_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ret = sc132gs_initialize_controls(sc132gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) ret = __sc132gs_power_on(sc132gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ret = sc132gs_check_sensor_id(sc132gs, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) sd->internal_ops = &sc132gs_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) sc132gs->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ret = media_entity_pads_init(&sd->entity, 1, &sc132gs->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (strcmp(sc132gs->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) sc132gs->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) SC132GS_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) __sc132gs_power_off(sc132gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) v4l2_ctrl_handler_free(&sc132gs->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) mutex_destroy(&sc132gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static int sc132gs_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) struct sc132gs *sc132gs = to_sc132gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) v4l2_ctrl_handler_free(&sc132gs->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) mutex_destroy(&sc132gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) __sc132gs_power_off(sc132gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static const struct of_device_id sc132gs_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) { .compatible = "smartsens,sc132gs" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) MODULE_DEVICE_TABLE(of, sc132gs_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) static const struct i2c_device_id sc132gs_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) { "smartsens,sc132gs", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static struct i2c_driver sc132gs_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) .name = SC132GS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) .pm = &sc132gs_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .of_match_table = of_match_ptr(sc132gs_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .probe = &sc132gs_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) .remove = &sc132gs_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) .id_table = sc132gs_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) return i2c_add_driver(&sc132gs_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) i2c_del_driver(&sc132gs_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) MODULE_DESCRIPTION("Smartsens sc132gs sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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