^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sc035gs driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * V0.1.0: MIPI is ok.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MIPI_FREQ_180M 180000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MIPI_FREQ_300M 300000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PIXEL_RATE_WITH_180M (MIPI_FREQ_180M * 2 / 10 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PIXEL_RATE_WITH_300M (MIPI_FREQ_300M * 2 / 8 * 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SC035GS_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CHIP_ID 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SC132GS_REG_CHIP_ID 0x300A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SC035GS_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SC035GS_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SC035GS_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SC035GS_REG_EXPOSURE 0x3e01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SC035GS_EXPOSURE_MIN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SC035GS_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SC035GS_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC035GS_REG_COARSE_AGAIN 0x3e08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SC035GS_REG_FINE_AGAIN 0x3e09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ANALOG_GAIN_MIN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ANALOG_GAIN_MAX 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ANALOG_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ANALOG_GAIN_DEFAULT 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SC035GS_REG_TEST_PATTERN 0x4501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SC035GS_TEST_PATTERN_ENABLE 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SC035GS_TEST_PATTERN_DISABLE 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SC035GS_REG_VTS 0x320e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC035GS_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SC035GS_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SC035GS_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SC035GS_NAME "sc035gs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const char *const sc035gs_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SC035GS_NUM_SUPPLIES ARRAY_SIZE(sc035gs_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) LINK_FREQ_180M_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) LINK_FREQ_300M_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct sc035gs_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 link_freq_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u64 pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct sc035gs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct regulator_bulk_data supplies[SC035GS_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_fract cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const struct sc035gs_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define to_sc035gs(sd) container_of(sd, struct sc035gs, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * Pclk 72Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * linelength 1600(0x06a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * framelength 1250(0x04e2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * grabwindow_width 640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * grabwindow_height 480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * mipi 2 lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * mipi_datarate per lane 360Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static const struct regval sc035gs_2lane_10bit_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x36e9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x36f9, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x3000, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x300f, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x3018, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x3019, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x301c, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x301f, 0x9c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x3031, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x3037, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x303f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x320c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x320d, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x320e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x320f, 0xe2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x3217, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x3218, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x3220, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x3223, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x3226, 0x74},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x3227, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x323b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x3250, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x3251, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x3252, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x3253, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x3254, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x3255, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x3304, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x3305, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x3306, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x3309, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x330a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x330b, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x330c, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x330f, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3310, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3314, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3315, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3316, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3317, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3329, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x332d, 0x5c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x332f, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3335, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3344, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x335b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x335f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3366, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3385, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3387, 0x49},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3389, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x33b1, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x33b2, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x33bd, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x33bf, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3621, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3622, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3624, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3630, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3631, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3633, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3635, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3636, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3637, 0x8a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3638, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3639, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x363a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x363b, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x363c, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x363e, 0xf8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3640, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3641, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x36ea, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x36eb, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x36ec, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x36ed, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x36fa, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x36fb, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x36fc, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x36fd, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3908, 0x91},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x391b, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3d08, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3e01, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3e02, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3f04, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3f05, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x4500, 0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x4501, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x4603, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x4800, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x4809, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x4810, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x4811, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x4837, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x5011, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x5988, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x598e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x598f, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x36e9, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x36f9, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) //again adjust
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x4418, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x363d, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x4419, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) //mirror & flip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3221, (0x03 << 1)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) //exposure 5ms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3e01, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3e02, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) //dgain 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3e06, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3e07, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) //gain < 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3631, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3630, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) //again 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3e08, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3e09, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static const struct sc035gs_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .exp_def = 0x0bb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .hts_def = 0x640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .vts_def = 0x4e2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .link_freq_index = LINK_FREQ_300M_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .pixel_rate = PIXEL_RATE_WITH_300M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .reg_list = sc035gs_2lane_10bit_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .lanes = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .bus_fmt = MEDIA_BUS_FMT_Y10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static const char *const sc035gs_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MIPI_FREQ_180M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MIPI_FREQ_300M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static int sc035gs_write_reg(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u16 reg, u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) ret = i2c_master_send(client, buf, len + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (ret != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static int sc035gs_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ret = sc035gs_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) SC035GS_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static int sc035gs_read_reg(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) u16 reg, unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int sc035gs_get_reso_dist(const struct sc035gs_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static const struct sc035gs_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) sc035gs_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dist = sc035gs_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if ((cur_best_fit_dist == -1 || dist < cur_best_fit_dist) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) (supported_modes[i].bus_fmt == framefmt->code)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static int sc035gs_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct sc035gs *sc035gs = to_sc035gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) const struct sc035gs_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) mutex_lock(&sc035gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mode = sc035gs_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) mutex_unlock(&sc035gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) sc035gs->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) __v4l2_ctrl_modify_range(sc035gs->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) __v4l2_ctrl_modify_range(sc035gs->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) SC035GS_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) __v4l2_ctrl_s_ctrl_int64(sc035gs->pixel_rate, mode->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) __v4l2_ctrl_s_ctrl(sc035gs->link_freq, mode->link_freq_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) sc035gs->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) sc035gs->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) mutex_unlock(&sc035gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int sc035gs_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct sc035gs *sc035gs = to_sc035gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) const struct sc035gs_mode *mode = sc035gs->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) mutex_lock(&sc035gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) mutex_unlock(&sc035gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) mutex_unlock(&sc035gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static int sc035gs_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct sc035gs *sc035gs = to_sc035gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) code->code = sc035gs->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static int sc035gs_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (fse->code != supported_modes[fse->index].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int sc035gs_enable_test_pattern(struct sc035gs *sc035gs, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) val = (pattern - 1) | SC035GS_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) val = SC035GS_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return sc035gs_write_reg(sc035gs->client, SC035GS_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) SC035GS_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) static void sc035gs_get_module_inf(struct sc035gs *sc035gs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) strscpy(inf->base.sensor, SC035GS_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) strscpy(inf->base.module, sc035gs->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) strscpy(inf->base.lens, sc035gs->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static long sc035gs_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) struct sc035gs *sc035gs = to_sc035gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) sc035gs_get_module_inf(sc035gs, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) ret = sc035gs_write_reg(sc035gs->client, SC035GS_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) SC035GS_REG_VALUE_08BIT, SC035GS_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ret = sc035gs_write_reg(sc035gs->client, SC035GS_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) SC035GS_REG_VALUE_08BIT, SC035GS_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static long sc035gs_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ret = sc035gs_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (copy_from_user(&stream, up, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = sc035gs_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int sc035gs_set_ctrl_gain(struct sc035gs *sc035gs, u32 a_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u32 coarse_again, fine_again, fine_again_reg, coarse_again_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* (1.0 - 15.5) * 0x10 (fix point) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (a_gain < 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) a_gain = 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (a_gain > 0xf8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) a_gain = 0xf8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (a_gain < 0x20) { /*1x ~ 2x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) coarse_again = 0x3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) fine_again = a_gain * 16 / 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) } else if (a_gain < 0x40) { /*2x ~ 4x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) coarse_again = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) fine_again = a_gain * 8 / 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) } else if (a_gain < 0x80) { /*4x ~ 8x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) coarse_again = 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) fine_again = a_gain * 4 / 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) } else { /*8x ~ 16x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) coarse_again = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) fine_again = a_gain * 2 / 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) fine_again_reg = fine_again & 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) coarse_again_reg = coarse_again & 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (a_gain < 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ret |= sc035gs_write_reg(sc035gs->client, 0x3631,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) SC035GS_REG_VALUE_08BIT, 0x58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ret |= sc035gs_write_reg(sc035gs->client, 0x3630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) SC035GS_REG_VALUE_08BIT, 0x4a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ret |= sc035gs_write_reg(sc035gs->client, 0x3631,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) SC035GS_REG_VALUE_08BIT, 0x48);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ret |= sc035gs_write_reg(sc035gs->client, 0x3630,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) SC035GS_REG_VALUE_08BIT, 0x4c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ret |= sc035gs_write_reg(sc035gs->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) SC035GS_REG_COARSE_AGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) SC035GS_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) coarse_again_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ret |= sc035gs_write_reg(sc035gs->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) SC035GS_REG_FINE_AGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) SC035GS_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) fine_again_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int __sc035gs_start_stream(struct sc035gs *sc035gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) ret = sc035gs_write_array(sc035gs->client, sc035gs->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) mutex_unlock(&sc035gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ret = v4l2_ctrl_handler_setup(&sc035gs->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) mutex_lock(&sc035gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) ret = sc035gs_write_reg(sc035gs->client, SC035GS_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) SC035GS_REG_VALUE_08BIT, SC035GS_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) usleep_range(10000, 12000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret |= sc035gs_write_reg(sc035gs->client, 0x4418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) SC035GS_REG_VALUE_08BIT, 0x0a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ret |= sc035gs_write_reg(sc035gs->client, 0x4419,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) SC035GS_REG_VALUE_08BIT, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static int __sc035gs_stop_stream(struct sc035gs *sc035gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return sc035gs_write_reg(sc035gs->client, SC035GS_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) SC035GS_REG_VALUE_08BIT, SC035GS_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static int sc035gs_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct sc035gs *sc035gs = to_sc035gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct i2c_client *client = sc035gs->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) unsigned int fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) mutex_lock(&sc035gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (on == sc035gs->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) fps = DIV_ROUND_CLOSEST(sc035gs->cur_mode->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) sc035gs->cur_mode->max_fps.numerator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dev_info(&sc035gs->client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) sc035gs->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) sc035gs->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) fps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ret = __sc035gs_start_stream(sc035gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) __sc035gs_stop_stream(sc035gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) sc035gs->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) mutex_unlock(&sc035gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static int sc035gs_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct sc035gs *sc035gs = to_sc035gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct i2c_client *client = sc035gs->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) mutex_lock(&sc035gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (sc035gs->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) sc035gs->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) sc035gs->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mutex_unlock(&sc035gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static int sc035gs_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct sc035gs *sc035gs = to_sc035gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) const struct sc035gs_mode *mode = sc035gs->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (sc035gs->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) fi->interval = sc035gs->cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static inline u32 sc035gs_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return DIV_ROUND_UP(cycles, SC035GS_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static int __sc035gs_power_on(struct sc035gs *sc035gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) struct device *dev = &sc035gs->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (!IS_ERR_OR_NULL(sc035gs->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = pinctrl_select_state(sc035gs->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) sc035gs->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ret = clk_set_rate(sc035gs->xvclk, SC035GS_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (clk_get_rate(sc035gs->xvclk) != SC035GS_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ret = clk_prepare_enable(sc035gs->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ret = regulator_bulk_enable(SC035GS_NUM_SUPPLIES, sc035gs->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!IS_ERR(sc035gs->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) gpiod_set_value_cansleep(sc035gs->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (!IS_ERR(sc035gs->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) gpiod_set_value_cansleep(sc035gs->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (!IS_ERR(sc035gs->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) gpiod_set_value_cansleep(sc035gs->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) delay_us = sc035gs_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) clk_disable_unprepare(sc035gs->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) static void __sc035gs_power_off(struct sc035gs *sc035gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (!IS_ERR(sc035gs->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) gpiod_set_value_cansleep(sc035gs->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (!IS_ERR(sc035gs->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) gpiod_set_value_cansleep(sc035gs->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) clk_disable_unprepare(sc035gs->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (!IS_ERR_OR_NULL(sc035gs->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ret = pinctrl_select_state(sc035gs->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) sc035gs->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) dev_dbg(&sc035gs->client->dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) regulator_bulk_disable(SC035GS_NUM_SUPPLIES, sc035gs->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static int sc035gs_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct sc035gs *sc035gs = to_sc035gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return __sc035gs_power_on(sc035gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static int sc035gs_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct sc035gs *sc035gs = to_sc035gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) __sc035gs_power_off(sc035gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static int sc035gs_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) struct sc035gs *sc035gs = to_sc035gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) const struct sc035gs_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) mutex_lock(&sc035gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) mutex_unlock(&sc035gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static int sc035gs_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static int sc035gs_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct sc035gs *sc035gs = to_sc035gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) val = 1 << (sc035gs->cur_mode->lanes - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static const struct dev_pm_ops sc035gs_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) SET_RUNTIME_PM_OPS(sc035gs_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) sc035gs_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static const struct v4l2_subdev_internal_ops sc035gs_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .open = sc035gs_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) static const struct v4l2_subdev_core_ops sc035gs_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .s_power = sc035gs_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .ioctl = sc035gs_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) .compat_ioctl32 = sc035gs_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) static const struct v4l2_subdev_video_ops sc035gs_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) .s_stream = sc035gs_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .g_frame_interval = sc035gs_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static const struct v4l2_subdev_pad_ops sc035gs_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .enum_mbus_code = sc035gs_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .enum_frame_size = sc035gs_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .enum_frame_interval = sc035gs_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) .get_fmt = sc035gs_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .set_fmt = sc035gs_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .get_mbus_config = sc035gs_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static const struct v4l2_subdev_ops sc035gs_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .core = &sc035gs_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .video = &sc035gs_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .pad = &sc035gs_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static void sc035gs_modify_fps_info(struct sc035gs *sc035gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) const struct sc035gs_mode *mode = sc035gs->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) sc035gs->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) sc035gs->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) static int sc035gs_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct sc035gs *sc035gs = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) struct sc035gs, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct i2c_client *client = sc035gs->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) max = sc035gs->cur_mode->height + ctrl->val - 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) __v4l2_ctrl_modify_range(sc035gs->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) sc035gs->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) sc035gs->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) sc035gs->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) ret = sc035gs_write_reg(sc035gs->client, SC035GS_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) SC035GS_REG_VALUE_16BIT, ctrl->val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ret = sc035gs_set_ctrl_gain(sc035gs, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ret = sc035gs_write_reg(sc035gs->client, SC035GS_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) SC035GS_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ctrl->val + sc035gs->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) sc035gs->cur_vts = ctrl->val + sc035gs->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (sc035gs->cur_vts != sc035gs->cur_mode->vts_def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) sc035gs_modify_fps_info(sc035gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ret = sc035gs_enable_test_pattern(sc035gs, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static const struct v4l2_ctrl_ops sc035gs_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) .s_ctrl = sc035gs_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static int sc035gs_initialize_controls(struct sc035gs *sc035gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) const struct sc035gs_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) handler = &sc035gs->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) mode = sc035gs->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) handler->lock = &sc035gs->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) sc035gs->link_freq = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ARRAY_SIZE(link_freq_menu_items) - 1, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) sc035gs->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) 0, PIXEL_RATE_WITH_300M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) 1, mode->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) __v4l2_ctrl_s_ctrl(sc035gs->link_freq, mode->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) sc035gs->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (sc035gs->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) sc035gs->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) sc035gs->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) sc035gs->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) sc035gs->vblank = v4l2_ctrl_new_std(handler, &sc035gs_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) SC035GS_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) exposure_max = mode->vts_def - 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) sc035gs->exposure = v4l2_ctrl_new_std(handler, &sc035gs_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) V4L2_CID_EXPOSURE, SC035GS_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) exposure_max, SC035GS_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) sc035gs->anal_gain = v4l2_ctrl_new_std(handler, &sc035gs_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ANALOG_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) sc035gs->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) &sc035gs_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) ARRAY_SIZE(sc035gs_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) 0, 0, sc035gs_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) dev_err(&sc035gs->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) sc035gs->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) static int sc035gs_check_sensor_id(struct sc035gs *sc035gs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct device *dev = &sc035gs->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ret = sc035gs_read_reg(client, SC132GS_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) SC035GS_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (ret || id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) dev_info(dev, "Detected SC035GS CHIP ID = 0x%04x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static int sc035gs_configure_regulators(struct sc035gs *sc035gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) for (i = 0; i < SC035GS_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) sc035gs->supplies[i].supply = sc035gs_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) return devm_regulator_bulk_get(&sc035gs->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) SC035GS_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) sc035gs->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static int sc035gs_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct sc035gs *sc035gs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) sc035gs = devm_kzalloc(dev, sizeof(*sc035gs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (!sc035gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) &sc035gs->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) &sc035gs->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) &sc035gs->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) &sc035gs->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) sc035gs->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) sc035gs->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) sc035gs->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (IS_ERR(sc035gs->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) sc035gs->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (IS_ERR(sc035gs->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) sc035gs->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (IS_ERR(sc035gs->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ret = sc035gs_configure_regulators(sc035gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) sc035gs->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (!IS_ERR(sc035gs->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) sc035gs->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) pinctrl_lookup_state(sc035gs->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) if (IS_ERR(sc035gs->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) sc035gs->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) pinctrl_lookup_state(sc035gs->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (IS_ERR(sc035gs->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) mutex_init(&sc035gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) sd = &sc035gs->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) v4l2_i2c_subdev_init(sd, client, &sc035gs_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ret = sc035gs_initialize_controls(sc035gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ret = __sc035gs_power_on(sc035gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) ret = sc035gs_check_sensor_id(sc035gs, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) sd->internal_ops = &sc035gs_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) sc035gs->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) ret = media_entity_pads_init(&sd->entity, 1, &sc035gs->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (strcmp(sc035gs->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) sc035gs->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) SC035GS_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) __sc035gs_power_off(sc035gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) v4l2_ctrl_handler_free(&sc035gs->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) mutex_destroy(&sc035gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static int sc035gs_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct sc035gs *sc035gs = to_sc035gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) v4l2_ctrl_handler_free(&sc035gs->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) mutex_destroy(&sc035gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) __sc035gs_power_off(sc035gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static const struct of_device_id sc035gs_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) { .compatible = "smartsens,sc035gs" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) MODULE_DEVICE_TABLE(of, sc035gs_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static const struct i2c_device_id sc035gs_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) { "smartsens,sc035gs", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static struct i2c_driver sc035gs_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .name = SC035GS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .pm = &sc035gs_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .of_match_table = of_match_ptr(sc035gs_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .probe = &sc035gs_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .remove = &sc035gs_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .id_table = sc035gs_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return i2c_add_driver(&sc035gs_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) i2c_del_driver(&sc035gs_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) MODULE_DESCRIPTION("Smartsens sc035gs sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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