^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * sc031gs driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X04 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SC031GS_PIXEL_RATE (72 * 1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SC031GS_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CHIP_ID 0x0031
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SC031GS_REG_CHIP_ID 0x3107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SC031GS_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SC031GS_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SC031GS_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SC031GS_REG_EXPOSURE 0x3e01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SC031GS_EXPOSURE_MIN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SC031GS_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SC031GS_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SC031GS_REG_COARSE_AGAIN 0x3e08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SC031GS_REG_FINE_AGAIN 0x3e09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ANALOG_GAIN_MIN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ANALOG_GAIN_MAX 0x7c0 // 124x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ANALOG_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ANALOG_GAIN_DEFAULT 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SC031GS_REG_TEST_PATTERN 0x4501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SC031GS_TEST_PATTERN_ENABLE 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SC031GS_TEST_PATTERN_DISABLE 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SC031GS_REG_VTS 0x320e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SC031GS_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SC031GS_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SC031GS_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) //#define DVP_INTERFACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #ifdef DVP_INTERFACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PIX_FORMAT MEDIA_BUS_FMT_Y8_1X8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PIX_FORMAT MEDIA_BUS_FMT_Y10_1X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SC031GS_LANES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SC031GS_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SC031GS_NAME "sc031gs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const char * const sc031gs_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SC031GS_NUM_SUPPLIES ARRAY_SIZE(sc031gs_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct sc031gs_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct sc031gs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct regulator_bulk_data supplies[SC031GS_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct v4l2_fract cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) const struct sc031gs_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define to_sc031gs(sd) container_of(sd, struct sc031gs, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Pclk 45Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * linelength 683(0x2ab)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * framelength 878(0x36e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * grabwindow_width 640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * grabwindow_height 480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * max_framerate 120fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * mipi_datarate per lane 720Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static const struct regval sc031gs_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #ifdef DVP_INTERFACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0x300f, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0x3018, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0x3019, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0x301c, 0xb4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0x3028, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x320c, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x320d, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) // {0x320e, 0x02}, //120fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) // {0x320f, 0xab},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x320e, 0x0a}, //30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x320f, 0xac},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x3250, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x3251, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x3252, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x3253, 0xa6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x3254, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x3255, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x3304, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x3306, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x3309, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x330b, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x330c, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x330f, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x3310, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x3314, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x3315, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x3316, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x3317, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x3329, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x332d, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x332f, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x3335, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x3344, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x335b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x335f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x3366, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x3385, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x3387, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x3389, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x33b1, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x33b2, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x3621, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x3622, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3624, 0x47},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x3630, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x3631, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x3633, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3636, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3637, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3638, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3639, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x363a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x363b, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x363c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x363d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x363e, 0xf8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3640, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3641, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x36e9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x36ea, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x36eb, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x36ec, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x36ed, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x36f9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x36fa, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x36fc, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3908, 0x91},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3d08, 0x00},//0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3e01, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3e02, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3e06, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x4500, 0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x4501, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x5011, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x0100, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x4418, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x4419, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) // test pattern
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) // {0x4501, 0xac},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) // {0x5011, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3000, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x300f, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3018, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3019, 0xfe},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x301c, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3031, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3037, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x303f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x320c, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x320d, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x320e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x320f, 0x67},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3250, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3251, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3252, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x3253, 0xa6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x3254, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x3255, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x3304, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3306, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3309, 0x68},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x330b, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x330c, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x330f, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3310, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3314, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x3315, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x3316, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3317, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3329, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x332d, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x332f, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3335, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3344, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x335b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x335f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3366, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3385, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x3387, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3389, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x33b1, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x33b2, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x3621, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3622, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3630, 0x46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x3631, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x3633, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3636, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3637, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x3638, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3639, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x363a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x363b, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x363c, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x363d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x363e, 0xf8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x3640, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x3641, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x36e9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x36ea, 0x3b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x36eb, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x36ec, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x36ed, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x36f9, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x36fa, 0x3a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x36fc, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3908, 0x91},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x3d08, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x3e01, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3e02, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3e06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x4500, 0x59},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x4501, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x4603, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x5011, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x0100, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x4418, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x4419, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static const struct sc031gs_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) .width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) .exp_def = 0x0148,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) .hts_def = 0x036e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) .vts_def = 0x0aac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) .reg_list = sc031gs_global_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static const char * const sc031gs_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SC031GS_LINK_FREQ_360MHZ (360 * 1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) SC031GS_LINK_FREQ_360MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static int sc031gs_write_reg(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u16 reg, u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ret = i2c_master_send(client, buf, len + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) if (ret != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static int sc031gs_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = sc031gs_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) SC031GS_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (regs[i].addr == 0x0100 && regs[i].val == 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static int sc031gs_read_reg(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u16 reg, unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int sc031gs_get_reso_dist(const struct sc031gs_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static const struct sc031gs_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) sc031gs_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dist = sc031gs_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static int sc031gs_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct sc031gs *sc031gs = to_sc031gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) const struct sc031gs_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) mutex_lock(&sc031gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) mode = sc031gs_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) fmt->format.code = PIX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) mutex_unlock(&sc031gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) sc031gs->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) __v4l2_ctrl_modify_range(sc031gs->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) __v4l2_ctrl_modify_range(sc031gs->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) SC031GS_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) sc031gs->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) sc031gs->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) mutex_unlock(&sc031gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) static int sc031gs_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct sc031gs *sc031gs = to_sc031gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) const struct sc031gs_mode *mode = sc031gs->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) mutex_lock(&sc031gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) mutex_unlock(&sc031gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) fmt->format.code = PIX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) mutex_unlock(&sc031gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int sc031gs_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) code->code = PIX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int sc031gs_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) if (fse->code != PIX_FORMAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static int sc031gs_enable_test_pattern(struct sc031gs *sc031gs, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) val = (pattern - 1) | SC031GS_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) val = SC031GS_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return sc031gs_write_reg(sc031gs->client, SC031GS_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) SC031GS_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static void sc031gs_get_module_inf(struct sc031gs *sc031gs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) strlcpy(inf->base.sensor, SC031GS_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) strlcpy(inf->base.module, sc031gs->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) strlcpy(inf->base.lens, sc031gs->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static long sc031gs_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct sc031gs *sc031gs = to_sc031gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) sc031gs_get_module_inf(sc031gs, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = sc031gs_write_reg(sc031gs->client, SC031GS_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) SC031GS_REG_VALUE_08BIT, SC031GS_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ret = sc031gs_write_reg(sc031gs->client, SC031GS_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) SC031GS_REG_VALUE_08BIT, SC031GS_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static long sc031gs_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) ret = sc031gs_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (copy_to_user(up, inf, sizeof(*inf))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (copy_from_user(cfg, up, sizeof(*cfg))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ret = sc031gs_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (copy_from_user(&stream, up, sizeof(u32)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ret = sc031gs_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int sc031gs_set_ctrl_gain(struct sc031gs *sc031gs, u32 a_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) u32 coarse_again, fine_again, fine_again_reg, coarse_again_reg, digital_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (a_gain < 0x20) { /*1x ~ 2x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) fine_again = a_gain - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) coarse_again = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) fine_again_reg = ((0x01 << 4) & 0x10) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) (fine_again & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) coarse_again_reg = coarse_again & 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) digital_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) } else if (a_gain < 0x40) { /*2x ~ 4x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) fine_again = (a_gain >> 1) - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) coarse_again = 0x7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) fine_again_reg = ((0x01 << 4) & 0x10) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) (fine_again & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) coarse_again_reg = coarse_again & 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) digital_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) } else if (a_gain < 0x80) { /*4x ~ 8x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) fine_again = (a_gain >> 2) - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) coarse_again = 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) fine_again_reg = ((0x01 << 4) & 0x10) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) (fine_again & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) coarse_again_reg = coarse_again & 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) digital_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) } else if (a_gain < 0x100) { /*8x ~ 16x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) fine_again = (a_gain >> 3) - 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) coarse_again = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) fine_again_reg = ((0x01 << 4) & 0x10) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) (fine_again & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) coarse_again_reg = coarse_again & 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) digital_gain_reg = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) } else if (a_gain < 0x200) { /*16x ~ 32x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) fine_again_reg = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) coarse_again_reg = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) digital_gain_reg = (a_gain * 0x80 / 0x100) & 0xf8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) } else if (a_gain < 0x400) { /*32x ~ 64x*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) fine_again_reg = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) coarse_again_reg = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) digital_gain_reg = (a_gain * 0x80 / 0x200) & 0x1f8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) } else { /*64x ~ 124*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) fine_again_reg = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) coarse_again_reg = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) digital_gain_reg = (a_gain * 0x80 / 0x400) & 0x3f8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (a_gain < 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ret |= sc031gs_write_reg(sc031gs->client, 0x3314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) SC031GS_REG_VALUE_08BIT, 0x42);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ret |= sc031gs_write_reg(sc031gs->client, 0x3317,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) SC031GS_REG_VALUE_08BIT, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ret |= sc031gs_write_reg(sc031gs->client, 0x3314,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) SC031GS_REG_VALUE_08BIT, 0x4f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ret |= sc031gs_write_reg(sc031gs->client, 0x3317,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) SC031GS_REG_VALUE_08BIT, 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ret |= sc031gs_write_reg(sc031gs->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) SC031GS_REG_COARSE_AGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) SC031GS_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) coarse_again_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ret |= sc031gs_write_reg(sc031gs->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) SC031GS_REG_FINE_AGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) SC031GS_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) fine_again_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret |= sc031gs_write_reg(sc031gs->client, 0x3e06,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) SC031GS_REG_VALUE_16BIT, digital_gain_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int __sc031gs_start_stream(struct sc031gs *sc031gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) // ret = sc031gs_write_array(sc031gs->client, sc031gs_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) // if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) // return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) ret = sc031gs_write_array(sc031gs->client, sc031gs->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) mutex_unlock(&sc031gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ret = v4l2_ctrl_handler_setup(&sc031gs->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) mutex_lock(&sc031gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return sc031gs_write_reg(sc031gs->client, SC031GS_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) SC031GS_REG_VALUE_08BIT, SC031GS_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static int __sc031gs_stop_stream(struct sc031gs *sc031gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return sc031gs_write_reg(sc031gs->client, SC031GS_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) SC031GS_REG_VALUE_08BIT, SC031GS_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static int sc031gs_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct sc031gs *sc031gs = to_sc031gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct i2c_client *client = sc031gs->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) mutex_lock(&sc031gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (on == sc031gs->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ret = __sc031gs_start_stream(sc031gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) __sc031gs_stop_stream(sc031gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) sc031gs->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) mutex_unlock(&sc031gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static int sc031gs_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct sc031gs *sc031gs = to_sc031gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) const struct sc031gs_mode *mode = sc031gs->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) if (sc031gs->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) fi->interval = sc031gs->cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) static int sc031gs_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) struct sc031gs *sc031gs = to_sc031gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct i2c_client *client = sc031gs->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) mutex_lock(&sc031gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (sc031gs->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) sc031gs->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) sc031gs->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) mutex_unlock(&sc031gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static inline u32 sc031gs_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return DIV_ROUND_UP(cycles, SC031GS_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static int __sc031gs_power_on(struct sc031gs *sc031gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct device *dev = &sc031gs->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ret = clk_set_rate(sc031gs->xvclk, SC031GS_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (clk_get_rate(sc031gs->xvclk) != SC031GS_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ret = clk_prepare_enable(sc031gs->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ret = regulator_bulk_enable(SC031GS_NUM_SUPPLIES, sc031gs->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (!IS_ERR(sc031gs->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) gpiod_set_value_cansleep(sc031gs->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) delay_us = sc031gs_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) clk_disable_unprepare(sc031gs->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static void __sc031gs_power_off(struct sc031gs *sc031gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (!IS_ERR(sc031gs->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) gpiod_set_value_cansleep(sc031gs->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) clk_disable_unprepare(sc031gs->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) regulator_bulk_disable(SC031GS_NUM_SUPPLIES, sc031gs->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static int sc031gs_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct sc031gs *sc031gs = to_sc031gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return __sc031gs_power_on(sc031gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static int sc031gs_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct sc031gs *sc031gs = to_sc031gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) __sc031gs_power_off(sc031gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) static int sc031gs_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct sc031gs *sc031gs = to_sc031gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) const struct sc031gs_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) mutex_lock(&sc031gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) try_fmt->code = PIX_FORMAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) mutex_unlock(&sc031gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #ifdef DVP_INTERFACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) static int sc031gs_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) config->type = V4L2_MBUS_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) config->flags = V4L2_MBUS_HSYNC_ACTIVE_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) V4L2_MBUS_VSYNC_ACTIVE_LOW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) V4L2_MBUS_PCLK_SAMPLE_FALLING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) static int sc031gs_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (fie->code != PIX_FORMAT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static const struct dev_pm_ops sc031gs_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) SET_RUNTIME_PM_OPS(sc031gs_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) sc031gs_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) static const struct v4l2_subdev_internal_ops sc031gs_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) .open = sc031gs_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static const struct v4l2_subdev_core_ops sc031gs_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) .s_power = sc031gs_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) .ioctl = sc031gs_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) .compat_ioctl32 = sc031gs_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) static const struct v4l2_subdev_video_ops sc031gs_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .s_stream = sc031gs_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .g_frame_interval = sc031gs_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #ifdef DVP_INTERFACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .g_mbus_config = sc031gs_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) static const struct v4l2_subdev_pad_ops sc031gs_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) .enum_mbus_code = sc031gs_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .enum_frame_size = sc031gs_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .enum_frame_interval = sc031gs_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .get_fmt = sc031gs_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .set_fmt = sc031gs_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static const struct v4l2_subdev_ops sc031gs_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .core = &sc031gs_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .video = &sc031gs_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .pad = &sc031gs_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static void sc031gs_modify_fps_info(struct sc031gs *sc031gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) const struct sc031gs_mode *mode = sc031gs->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) sc031gs->cur_fps.denominator = mode->max_fps.denominator * mode->vts_def /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) sc031gs->cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) static int sc031gs_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct sc031gs *sc031gs = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct sc031gs, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct i2c_client *client = sc031gs->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) max = sc031gs->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) __v4l2_ctrl_modify_range(sc031gs->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) sc031gs->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) sc031gs->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) sc031gs->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ret = sc031gs_write_reg(sc031gs->client, SC031GS_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) SC031GS_REG_VALUE_16BIT, ctrl->val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) ret = sc031gs_set_ctrl_gain(sc031gs, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) ret = sc031gs_write_reg(sc031gs->client, SC031GS_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) SC031GS_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ctrl->val + sc031gs->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) sc031gs->cur_vts = ctrl->val + sc031gs->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (sc031gs->cur_vts != sc031gs->cur_mode->vts_def)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) sc031gs_modify_fps_info(sc031gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ret = sc031gs_enable_test_pattern(sc031gs, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) static const struct v4l2_ctrl_ops sc031gs_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) .s_ctrl = sc031gs_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static int sc031gs_initialize_controls(struct sc031gs *sc031gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) const struct sc031gs_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) handler = &sc031gs->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) mode = sc031gs->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) handler->lock = &sc031gs->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) 0, SC031GS_PIXEL_RATE, 1, SC031GS_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) sc031gs->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (sc031gs->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) sc031gs->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) sc031gs->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) sc031gs->vblank = v4l2_ctrl_new_std(handler, &sc031gs_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) SC031GS_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) exposure_max = mode->vts_def - 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) sc031gs->exposure = v4l2_ctrl_new_std(handler, &sc031gs_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) V4L2_CID_EXPOSURE, SC031GS_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) exposure_max, SC031GS_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) sc031gs->anal_gain = v4l2_ctrl_new_std(handler, &sc031gs_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) ANALOG_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) sc031gs->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) &sc031gs_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) ARRAY_SIZE(sc031gs_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) 0, 0, sc031gs_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) dev_err(&sc031gs->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) sc031gs->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) sc031gs->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static int sc031gs_check_sensor_id(struct sc031gs *sc031gs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct device *dev = &sc031gs->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) ret = sc031gs_read_reg(client, SC031GS_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) SC031GS_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) dev_info(dev, "Detected SC031GS CHIP ID = 0x%04x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static int sc031gs_configure_regulators(struct sc031gs *sc031gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) for (i = 0; i < SC031GS_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) sc031gs->supplies[i].supply = sc031gs_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) return devm_regulator_bulk_get(&sc031gs->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) SC031GS_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) sc031gs->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) static int sc031gs_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct sc031gs *sc031gs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) sc031gs = devm_kzalloc(dev, sizeof(*sc031gs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (!sc031gs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) &sc031gs->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) &sc031gs->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) &sc031gs->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) &sc031gs->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) sc031gs->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) sc031gs->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) sc031gs->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (IS_ERR(sc031gs->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) sc031gs->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (IS_ERR(sc031gs->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) sc031gs->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) if (IS_ERR(sc031gs->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) ret = sc031gs_configure_regulators(sc031gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) mutex_init(&sc031gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) sd = &sc031gs->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) v4l2_i2c_subdev_init(sd, client, &sc031gs_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) ret = sc031gs_initialize_controls(sc031gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ret = __sc031gs_power_on(sc031gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) ret = sc031gs_check_sensor_id(sc031gs, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) sd->internal_ops = &sc031gs_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) sc031gs->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ret = media_entity_pads_init(&sd->entity, 1, &sc031gs->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (strcmp(sc031gs->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) sc031gs->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) SC031GS_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) __sc031gs_power_off(sc031gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) v4l2_ctrl_handler_free(&sc031gs->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) mutex_destroy(&sc031gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static int sc031gs_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) struct sc031gs *sc031gs = to_sc031gs(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) v4l2_ctrl_handler_free(&sc031gs->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) mutex_destroy(&sc031gs->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) __sc031gs_power_off(sc031gs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static const struct of_device_id sc031gs_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) { .compatible = "smartsens,sc031gs" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) MODULE_DEVICE_TABLE(of, sc031gs_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) static const struct i2c_device_id sc031gs_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) { "smartsens,sc031gs", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) static struct i2c_driver sc031gs_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) .name = SC031GS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) .pm = &sc031gs_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .of_match_table = of_match_ptr(sc031gs_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .probe = &sc031gs_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .remove = &sc031gs_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .id_table = sc031gs_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) return i2c_add_driver(&sc031gs_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) i2c_del_driver(&sc031gs_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) MODULE_DESCRIPTION("Smartsens sc031gs sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) MODULE_AUTHOR("zack.zeng");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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