^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * saa717x - Philips SAA717xHL video decoder driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Based on the saa7115 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Changes by Ohta Kyuma <alpha292@bremen.or.jp>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * - Apply to SAA717x,NEC uPD64031,uPD64083. (1/31/2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Changes by T.Adachi (tadachi@tadachi-net.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * - support audio, video scaler etc, and checked the initialize sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Cleaned up by Hans Verkuil <hverkuil@xs4all.nl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Note: this is a reversed engineered driver based on captures from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * the I2C bus under Windows. This chip is very similar to the saa7134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * though. Unfortunately, this driver is currently only working for NTSC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_DESCRIPTION("Philips SAA717x audio/video decoder driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MODULE_AUTHOR("K. Ohta, T. Adachi, Hans Verkuil");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MODULE_PARM_DESC(debug, "Debug level (0-1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Generic i2c probe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * concerning the addresses: i2c wants 7 bit (without the r/w bit), so '>>1'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct saa717x_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) v4l2_std_id std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) int enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) int radio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) int playback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int audio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) int tuner_audio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int audio_main_mute;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int audio_main_vol_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int audio_main_vol_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u16 audio_main_bass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u16 audio_main_treble;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u16 audio_main_volume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u16 audio_main_balance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) int audio_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) static inline struct saa717x_state *to_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return container_of(sd, struct saa717x_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return &container_of(ctrl->handler, struct saa717x_state, hdl)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* for audio mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TUNER_AUDIO_MONO 0 /* LL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TUNER_AUDIO_STEREO 1 /* LR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TUNER_AUDIO_LANG1 2 /* LL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TUNER_AUDIO_LANG2 3 /* RR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SAA717X_NTSC_WIDTH (704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SAA717X_NTSC_HEIGHT (480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static int saa717x_write(struct v4l2_subdev *sd, u32 reg, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct i2c_adapter *adap = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int fw_addr = reg == 0x454 || (reg >= 0x464 && reg <= 0x478) || reg == 0x480 || reg == 0x488;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned char mm1[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) msg.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) mm1[0] = (reg >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) mm1[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) if (fw_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) mm1[4] = (value >> 16) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) mm1[3] = (value >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) mm1[2] = value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) mm1[2] = value & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) msg.len = fw_addr ? 5 : 3; /* Long Registers have *only* three bytes! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) msg.buf = mm1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) v4l2_dbg(2, debug, sd, "wrote: reg 0x%03x=%08x\n", reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return i2c_transfer(adap, &msg, 1) == 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void saa717x_write_regs(struct v4l2_subdev *sd, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) while (data[0] || data[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) saa717x_write(sd, data[0], data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) data += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static u32 saa717x_read(struct v4l2_subdev *sd, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct i2c_adapter *adap = client->adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int fw_addr = (reg >= 0x404 && reg <= 0x4b8) || reg == 0x528;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned char mm1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned char mm2[4] = { 0, 0, 0, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) msgs[0].addr = msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) mm1[0] = (reg >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) mm1[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) msgs[0].buf = mm1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) msgs[1].len = fw_addr ? 3 : 1; /* Multibyte Registers contains *only* 3 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) msgs[1].buf = mm2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) i2c_transfer(adap, msgs, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) if (fw_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) value = (mm2[2] << 16) | (mm2[1] << 8) | mm2[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) value = mm2[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) v4l2_dbg(2, debug, sd, "read: reg 0x%03x=0x%08x\n", reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) static u32 reg_init_initialize[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* from linux driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 0x101, 0x008, /* Increment delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 0x103, 0x000, /* Analog input control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 0x104, 0x090, /* Analog input control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 0x105, 0x090, /* Analog input control 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 0x106, 0x0eb, /* Horizontal sync start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 0x107, 0x0e0, /* Horizontal sync stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 0x109, 0x055, /* Luminance control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 0x10f, 0x02a, /* Chroma gain control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 0x110, 0x000, /* Chroma control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 0x114, 0x045, /* analog/ADC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 0x118, 0x040, /* RAW data gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 0x119, 0x080, /* RAW data offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 0x044, 0x000, /* VBI horizontal input window start (L) TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 0x045, 0x000, /* VBI horizontal input window start (H) TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 0x046, 0x0cf, /* VBI horizontal input window stop (L) TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 0x047, 0x002, /* VBI horizontal input window stop (H) TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 0x049, 0x000, /* VBI vertical input window start (H) TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 0x04c, 0x0d0, /* VBI horizontal output length (L) TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 0x04d, 0x002, /* VBI horizontal output length (H) TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 0x064, 0x080, /* Lumina brightness TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 0x065, 0x040, /* Luminance contrast TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 0x066, 0x040, /* Chroma saturation TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* 067H: Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 0x068, 0x000, /* VBI horizontal scaling increment (L) TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 0x069, 0x004, /* VBI horizontal scaling increment (H) TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 0x06a, 0x000, /* VBI phase offset TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 0x06e, 0x000, /* Horizontal phase offset Luma TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 0x06f, 0x000, /* Horizontal phase offset Chroma TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 0x072, 0x000, /* Vertical filter mode TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 0x084, 0x000, /* VBI horizontal input window start (L) TAKS B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 0x085, 0x000, /* VBI horizontal input window start (H) TAKS B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 0x086, 0x0cf, /* VBI horizontal input window stop (L) TAKS B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 0x087, 0x002, /* VBI horizontal input window stop (H) TAKS B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 0x089, 0x000, /* VBI vertical input window start (H) TAKS B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 0x08c, 0x0d0, /* VBI horizontal output length (L) TASK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 0x08d, 0x002, /* VBI horizontal output length (H) TASK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 0x0a4, 0x080, /* Lumina brightness TASK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 0x0a5, 0x040, /* Luminance contrast TASK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 0x0a6, 0x040, /* Chroma saturation TASK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* 0A7H reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 0x0a8, 0x000, /* VBI horizontal scaling increment (L) TASK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 0x0a9, 0x004, /* VBI horizontal scaling increment (H) TASK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 0x0aa, 0x000, /* VBI phase offset TASK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 0x0ae, 0x000, /* Horizontal phase offset Luma TASK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 0x0af, 0x000, /*Horizontal phase offset Chroma TASK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 0x0b2, 0x000, /* Vertical filter mode TASK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 0x00c, 0x000, /* Start point GREEN path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 0x00d, 0x000, /* Start point BLUE path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 0x00e, 0x000, /* Start point RED path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 0x010, 0x010, /* GREEN path gamma curve --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 0x011, 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 0x012, 0x030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 0x013, 0x040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 0x014, 0x050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 0x015, 0x060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 0x016, 0x070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 0x017, 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 0x018, 0x090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 0x019, 0x0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 0x01a, 0x0b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 0x01b, 0x0c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 0x01c, 0x0d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 0x01d, 0x0e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 0x01e, 0x0f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 0x01f, 0x0ff, /* --- GREEN path gamma curve */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 0x020, 0x010, /* BLUE path gamma curve --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 0x021, 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 0x022, 0x030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 0x023, 0x040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 0x024, 0x050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 0x025, 0x060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 0x026, 0x070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 0x027, 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 0x028, 0x090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 0x029, 0x0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 0x02a, 0x0b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 0x02b, 0x0c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 0x02c, 0x0d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 0x02d, 0x0e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 0x02e, 0x0f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 0x02f, 0x0ff, /* --- BLUE path gamma curve */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 0x030, 0x010, /* RED path gamma curve --- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 0x031, 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 0x032, 0x030,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 0x033, 0x040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 0x034, 0x050,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 0x035, 0x060,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 0x036, 0x070,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 0x037, 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 0x038, 0x090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 0x039, 0x0a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 0x03a, 0x0b0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 0x03b, 0x0c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 0x03c, 0x0d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 0x03d, 0x0e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 0x03e, 0x0f0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 0x03f, 0x0ff, /* --- RED path gamma curve */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 0x109, 0x085, /* Luminance control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /**** from app start ****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 0x584, 0x000, /* AGC gain control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 0x585, 0x000, /* Program count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 0x586, 0x003, /* Status reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 0x588, 0x0ff, /* Number of audio samples (L) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 0x589, 0x00f, /* Number of audio samples (M) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 0x58a, 0x000, /* Number of audio samples (H) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 0x58b, 0x000, /* Audio select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 0x58c, 0x010, /* Audio channel assign1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 0x58d, 0x032, /* Audio channel assign2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 0x58e, 0x054, /* Audio channel assign3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 0x58f, 0x023, /* Audio format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 0x590, 0x000, /* SIF control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 0x595, 0x000, /* ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 0x596, 0x000, /* ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 0x597, 0x000, /* ?? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 0x464, 0x00, /* Digital input crossbar1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 0x46c, 0xbbbb10, /* Digital output selection1-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 0x470, 0x101010, /* Digital output selection4-6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 0x478, 0x00, /* Sound feature control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 0x474, 0x18, /* Softmute control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 0x454, 0x0425b9, /* Sound Easy programming(reset) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 0x454, 0x042539, /* Sound Easy programming(reset) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /**** common setting( of DVD play, including scaler commands) ****/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 0x042, 0x003, /* Data path configuration for VBI (TASK A) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 0x082, 0x003, /* Data path configuration for VBI (TASK B) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 0x108, 0x0f8, /* Sync control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 0x2a9, 0x0fd, /* ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 0x102, 0x089, /* select video input "mode 9" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 0x111, 0x000, /* Mode/delay control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 0x10e, 0x00a, /* Chroma control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 0x594, 0x002, /* SIF, analog I/O select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 0x454, 0x0425b9, /* Sound */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 0x454, 0x042539,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 0x111, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 0x10e, 0x00a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 0x464, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 0x300, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 0x301, 0x006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 0x302, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 0x303, 0x006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 0x308, 0x040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 0x309, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 0x30a, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 0x30b, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 0x000, 0x002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 0x001, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 0x002, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 0x003, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 0x004, 0x033,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 0x040, 0x01d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 0x041, 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 0x042, 0x004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 0x043, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 0x080, 0x01e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 0x081, 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 0x082, 0x004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 0x083, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 0x190, 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 0x115, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 0x116, 0x012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 0x117, 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 0x04a, 0x011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 0x08a, 0x011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 0x04b, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 0x08b, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 0x048, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 0x088, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 0x04e, 0x012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 0x08e, 0x012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 0x058, 0x012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 0x098, 0x012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 0x059, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 0x099, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 0x05a, 0x003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 0x09a, 0x003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 0x05b, 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 0x09b, 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 0x054, 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 0x094, 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 0x055, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 0x095, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 0x056, 0x0c7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 0x096, 0x0c7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 0x057, 0x002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 0x097, 0x002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 0x0ff, 0x0ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 0x060, 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 0x0a0, 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 0x061, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 0x0a1, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 0x062, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 0x0a2, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 0x063, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 0x0a3, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 0x070, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 0x0b0, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 0x071, 0x004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 0x0b1, 0x004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 0x06c, 0x0e9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 0x0ac, 0x0e9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 0x06d, 0x003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 0x0ad, 0x003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 0x05c, 0x0d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 0x09c, 0x0d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 0x05d, 0x002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 0x09d, 0x002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 0x05e, 0x0f2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 0x09e, 0x0f2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 0x05f, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 0x09f, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 0x074, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 0x0b4, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 0x075, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 0x0b5, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 0x076, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 0x0b6, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 0x077, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 0x0b7, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 0x195, 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 0x0ff, 0x0ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 0x108, 0x0f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 0x111, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 0x10e, 0x00a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 0x2a9, 0x0fd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 0x464, 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 0x454, 0x042135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 0x598, 0x0e7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 0x599, 0x07d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 0x59a, 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 0x59c, 0x066,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 0x59d, 0x090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 0x59e, 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 0x584, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 0x585, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 0x586, 0x003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 0x588, 0x0ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 0x589, 0x00f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 0x58a, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 0x58b, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 0x58c, 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 0x58d, 0x032,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 0x58e, 0x054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 0x58f, 0x023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 0x590, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 0x595, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 0x596, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 0x597, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 0x464, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 0x46c, 0xbbbb10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 0x470, 0x101010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 0x478, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 0x474, 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 0x454, 0x042135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 0x598, 0x0e7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 0x599, 0x07d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 0x59a, 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 0x59c, 0x066,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 0x59d, 0x090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 0x59e, 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 0x584, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 0x585, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 0x586, 0x003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 0x588, 0x0ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 0x589, 0x00f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 0x58a, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 0x58b, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 0x58c, 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 0x58d, 0x032,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 0x58e, 0x054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 0x58f, 0x023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 0x590, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 0x595, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 0x596, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 0x597, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 0x464, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 0x46c, 0xbbbb10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 0x470, 0x101010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 0x478, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 0x474, 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 0x454, 0x042135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 0x598, 0x0e7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 0x599, 0x07d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 0x59a, 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 0x59c, 0x066,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 0x59d, 0x090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 0x59e, 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 0x584, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 0x585, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 0x586, 0x003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 0x588, 0x0ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 0x589, 0x00f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 0x58a, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 0x58b, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 0x58c, 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 0x58d, 0x032,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 0x58e, 0x054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 0x58f, 0x023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 0x590, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 0x595, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 0x596, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 0x597, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 0x464, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 0x46c, 0xbbbb10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 0x470, 0x101010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 0x478, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 0x474, 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 0x454, 0x042135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 0x193, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 0x300, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 0x301, 0x006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 0x302, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 0x303, 0x006,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 0x308, 0x040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 0x309, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 0x30a, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 0x30b, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 0x000, 0x002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 0x001, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 0x002, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 0x003, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 0x004, 0x033,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 0x040, 0x01d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 0x041, 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 0x042, 0x004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 0x043, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 0x080, 0x01e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 0x081, 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 0x082, 0x004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 0x083, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 0x190, 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 0x115, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 0x116, 0x012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 0x117, 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 0x04a, 0x011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 0x08a, 0x011,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 0x04b, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 0x08b, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 0x048, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 0x088, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 0x04e, 0x012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 0x08e, 0x012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 0x058, 0x012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 0x098, 0x012,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 0x059, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 0x099, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 0x05a, 0x003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 0x09a, 0x003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 0x05b, 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 0x09b, 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 0x054, 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 0x094, 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 0x055, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 0x095, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 0x056, 0x0c7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 0x096, 0x0c7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 0x057, 0x002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 0x097, 0x002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 0x060, 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 0x0a0, 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 0x061, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 0x0a1, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 0x062, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 0x0a2, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 0x063, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 0x0a3, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 0x070, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 0x0b0, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 0x071, 0x004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 0x0b1, 0x004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 0x06c, 0x0e9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 0x0ac, 0x0e9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 0x06d, 0x003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 0x0ad, 0x003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 0x05c, 0x0d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 0x09c, 0x0d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 0x05d, 0x002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 0x09d, 0x002,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 0x05e, 0x0f2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 0x09e, 0x0f2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 0x05f, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 0x09f, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 0x074, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 0x0b4, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 0x075, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 0x0b5, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 0x076, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 0x0b6, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 0x077, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 0x0b7, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 0x195, 0x008,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 0x598, 0x0e7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 0x599, 0x07d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 0x59a, 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 0x59c, 0x066,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 0x59d, 0x090,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 0x59e, 0x001,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 0x584, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 0x585, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 0x586, 0x003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 0x588, 0x0ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 0x589, 0x00f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 0x58a, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 0x58b, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 0x58c, 0x010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 0x58d, 0x032,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 0x58e, 0x054,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 0x58f, 0x023,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 0x590, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 0x595, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 0x596, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 0x597, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 0x464, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 0x46c, 0xbbbb10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 0x470, 0x101010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 0x478, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 0x474, 0x018,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 0x454, 0x042135,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 0x193, 0x0a6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 0x108, 0x0f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 0x042, 0x003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 0x082, 0x003,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 0x454, 0x0425b9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 0x454, 0x042539,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 0x193, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 0x193, 0x0a6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 0x464, 0x000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* Tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static u32 reg_init_tuner_input[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 0x108, 0x0f8, /* Sync control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 0x111, 0x000, /* Mode/delay control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 0x10e, 0x00a, /* Chroma control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* Composite */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static u32 reg_init_composite_input[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) 0x108, 0x0e8, /* Sync control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 0x111, 0x000, /* Mode/delay control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) 0x10e, 0x04a, /* Chroma control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* S-Video */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static u32 reg_init_svideo_input[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) 0x108, 0x0e8, /* Sync control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) 0x111, 0x000, /* Mode/delay control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) 0x10e, 0x04a, /* Chroma control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) 0, 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) static u32 reg_set_audio_template[4][2] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) { /* for MONO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) tadachi 6/29 DMA audio output select?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) Register 0x46c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) 7-4: DMA2, 3-0: DMA1 ch. DMA4, DMA3 DMA2, DMA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) 0: MAIN left, 1: MAIN right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) 2: AUX1 left, 3: AUX1 right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 4: AUX2 left, 5: AUX2 right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) 6: DPL left, 7: DPL right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) 8: DPL center, 9: DPL surround
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) A: monitor output, B: digital sense */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) 0xbbbb00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* tadachi 6/29 DAC and I2S output select?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) Register 0x470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 7-4:DAC right ch. 3-0:DAC left ch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) I2S1 right,left I2S2 right,left */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) { /* for STEREO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) 0xbbbb10, 0x101010,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) { /* for LANG1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 0xbbbb00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) { /* for LANG2/SAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) 0xbbbb11, 0x111111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* Get detected audio flags (from saa7134 driver) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static void get_inf_dev_status(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) int *dual_flag, int *stereo_flag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u32 reg_data3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) static char *stdres[0x20] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) [0x00] = "no standard detected",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) [0x01] = "B/G (in progress)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) [0x02] = "D/K (in progress)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) [0x03] = "M (in progress)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) [0x04] = "B/G A2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) [0x05] = "B/G NICAM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) [0x06] = "D/K A2 (1)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) [0x07] = "D/K A2 (2)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) [0x08] = "D/K A2 (3)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) [0x09] = "D/K NICAM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) [0x0a] = "L NICAM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) [0x0b] = "I NICAM",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) [0x0c] = "M Korea",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) [0x0d] = "M BTSC ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) [0x0e] = "M EIAJ",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) [0x0f] = "FM radio / IF 10.7 / 50 deemp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) [0x10] = "FM radio / IF 10.7 / 75 deemp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) [0x11] = "FM radio / IF sel / 50 deemp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) [0x12] = "FM radio / IF sel / 75 deemp",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) [0x13 ... 0x1e] = "unknown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) [0x1f] = "??? [in progress]",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) *dual_flag = *stereo_flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* (demdec status: 0x528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* read current status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) reg_data3 = saa717x_read(sd, 0x0528);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) v4l2_dbg(1, debug, sd, "tvaudio thread status: 0x%x [%s%s%s]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) reg_data3, stdres[reg_data3 & 0x1f],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) (reg_data3 & 0x000020) ? ",stereo" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) (reg_data3 & 0x000040) ? ",dual" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) v4l2_dbg(1, debug, sd, "detailed status: "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) "%s#%s#%s#%s#%s#%s#%s#%s#%s#%s#%s#%s#%s#%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) (reg_data3 & 0x000080) ? " A2/EIAJ pilot tone " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) (reg_data3 & 0x000100) ? " A2/EIAJ dual " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) (reg_data3 & 0x000200) ? " A2/EIAJ stereo " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) (reg_data3 & 0x000400) ? " A2/EIAJ noise mute " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) (reg_data3 & 0x000800) ? " BTSC/FM radio pilot " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) (reg_data3 & 0x001000) ? " SAP carrier " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) (reg_data3 & 0x002000) ? " BTSC stereo noise mute " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) (reg_data3 & 0x004000) ? " SAP noise mute " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) (reg_data3 & 0x008000) ? " VDSP " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) (reg_data3 & 0x010000) ? " NICST " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) (reg_data3 & 0x020000) ? " NICDU " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) (reg_data3 & 0x040000) ? " NICAM muted " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) (reg_data3 & 0x080000) ? " NICAM reserve sound " : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) (reg_data3 & 0x100000) ? " init done " : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (reg_data3 & 0x000220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) v4l2_dbg(1, debug, sd, "ST!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) *stereo_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (reg_data3 & 0x000140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) v4l2_dbg(1, debug, sd, "DUAL!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) *dual_flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) /* regs write to set audio mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static void set_audio_mode(struct v4l2_subdev *sd, int audio_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) v4l2_dbg(1, debug, sd, "writing registers to set audio mode by set %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) audio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) saa717x_write(sd, 0x46c, reg_set_audio_template[audio_mode][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) saa717x_write(sd, 0x470, reg_set_audio_template[audio_mode][1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* write regs to set audio volume, bass and treble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static int set_audio_regs(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct saa717x_state *decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u8 mute = 0xac; /* -84 dB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) unsigned int work_l, work_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* set SIF analog I/O select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) saa717x_write(sd, 0x0594, decoder->audio_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) v4l2_dbg(1, debug, sd, "set audio input %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) decoder->audio_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* normalize ( 65535 to 0 -> 24 to -40 (not -84)) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) work_l = (min(65536 - decoder->audio_main_balance, 32768) * decoder->audio_main_volume) / 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) work_r = (min(decoder->audio_main_balance, (u16)32768) * decoder->audio_main_volume) / 32768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) decoder->audio_main_vol_l = (long)work_l * (24 - (-40)) / 65535 - 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) decoder->audio_main_vol_r = (long)work_r * (24 - (-40)) / 65535 - 40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* set main volume */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* main volume L[7-0],R[7-0],0x00 24=24dB,-83dB, -84(mute) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* def:0dB->6dB(MPG600GR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* if mute is on, set mute */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (decoder->audio_main_mute) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) val = mute | (mute << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) val = (u8)decoder->audio_main_vol_l |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ((u8)decoder->audio_main_vol_r << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) saa717x_write(sd, 0x480, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* set bass and treble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) val = decoder->audio_main_bass & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) val |= (decoder->audio_main_treble & 0x1f) << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) saa717x_write(sd, 0x488, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /********** scaling staff ***********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static void set_h_prescale(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) int task, int prescale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) int xpsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) int xacl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) int xc2_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int xdcg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) int vpfy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) } vals[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* XPSC XACL XC2_1 XDCG VPFY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) { 1, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) { 2, 2, 1, 2, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) { 3, 4, 1, 3, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) { 4, 8, 1, 4, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) { 5, 8, 1, 4, 2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) { 6, 8, 1, 4, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) { 7, 8, 1, 4, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) { 8, 15, 0, 4, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) { 9, 15, 0, 4, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) { 10, 16, 1, 5, 3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) static const int count = ARRAY_SIZE(vals);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) int i, task_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) task_shift = task * 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) for (i = 0; i < count; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (vals[i].xpsc == prescale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (i == count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* horizontal prescaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) saa717x_write(sd, 0x60 + task_shift, vals[i].xpsc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* accumulation length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) saa717x_write(sd, 0x61 + task_shift, vals[i].xacl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* level control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) saa717x_write(sd, 0x62 + task_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) (vals[i].xc2_1 << 3) | vals[i].xdcg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /*FIR prefilter control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) saa717x_write(sd, 0x63 + task_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) (vals[i].vpfy << 2) | vals[i].vpfy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /********** scaling staff ***********/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static void set_v_scale(struct v4l2_subdev *sd, int task, int yscale)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) int task_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) task_shift = task * 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /* Vertical scaling ratio (LOW) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) saa717x_write(sd, 0x70 + task_shift, yscale & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* Vertical scaling ratio (HI) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) saa717x_write(sd, 0x71 + task_shift, yscale >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static int saa717x_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct saa717x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) saa717x_write(sd, 0x10a, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) saa717x_write(sd, 0x10b, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) saa717x_write(sd, 0x10c, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) case V4L2_CID_HUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) saa717x_write(sd, 0x10d, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) case V4L2_CID_AUDIO_MUTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) state->audio_main_mute = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) case V4L2_CID_AUDIO_VOLUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) state->audio_main_volume = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) case V4L2_CID_AUDIO_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) state->audio_main_balance = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) case V4L2_CID_AUDIO_TREBLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) state->audio_main_treble = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) case V4L2_CID_AUDIO_BASS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) state->audio_main_bass = ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) set_audio_regs(sd, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int saa717x_s_video_routing(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct saa717x_state *decoder = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) int is_tuner = input & 0x80; /* tuner input flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) input &= 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) v4l2_dbg(1, debug, sd, "decoder set input (%d)\n", input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /* inputs from 0-9 are available*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* saa717x have mode0-mode9 but mode5 is reserved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (input > 9 || input == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (decoder->input != input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) int input_line = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) decoder->input = input_line;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) v4l2_dbg(1, debug, sd, "now setting %s input %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) input_line >= 6 ? "S-Video" : "Composite",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) input_line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* select mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) saa717x_write(sd, 0x102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) (saa717x_read(sd, 0x102) & 0xf0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) input_line);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /* bypass chrominance trap for modes 6..9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) saa717x_write(sd, 0x109,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) (saa717x_read(sd, 0x109) & 0x7f) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) (input_line < 6 ? 0x0 : 0x80));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) /* change audio_mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (is_tuner) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /* tuner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) set_audio_mode(sd, decoder->tuner_audio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* Force to STEREO mode if Composite or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * S-Video were chosen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) set_audio_mode(sd, TUNER_AUDIO_STEREO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* change initialize procedure (Composite/S-Video) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (is_tuner)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) saa717x_write_regs(sd, reg_init_tuner_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) else if (input_line >= 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) saa717x_write_regs(sd, reg_init_svideo_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) saa717x_write_regs(sd, reg_init_composite_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static int saa717x_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) reg->val = saa717x_read(sd, reg->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) reg->size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static int saa717x_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) u16 addr = reg->reg & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) u8 val = reg->val & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) saa717x_write(sd, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) static int saa717x_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct v4l2_mbus_framefmt *fmt = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) int prescale, h_scale, v_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) v4l2_dbg(1, debug, sd, "decoder set size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (format->pad || fmt->code != MEDIA_BUS_FMT_FIXED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* FIXME need better bounds checking here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (fmt->width < 1 || fmt->width > 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (fmt->height < 1 || fmt->height > 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) fmt->field = V4L2_FIELD_INTERLACED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (format->which == V4L2_SUBDEV_FORMAT_TRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* scaling setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) /* NTSC and interlace only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) prescale = SAA717X_NTSC_WIDTH / fmt->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (prescale == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) prescale = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) h_scale = 1024 * SAA717X_NTSC_WIDTH / prescale / fmt->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* interlace */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) v_scale = 512 * 2 * SAA717X_NTSC_HEIGHT / fmt->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) /* Horizontal prescaling etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) set_h_prescale(sd, 0, prescale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) set_h_prescale(sd, 1, prescale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) /* Horizontal scaling increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /* TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) saa717x_write(sd, 0x6C, (u8)(h_scale & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) saa717x_write(sd, 0x6D, (u8)((h_scale >> 8) & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) /* TASK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) saa717x_write(sd, 0xAC, (u8)(h_scale & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) saa717x_write(sd, 0xAD, (u8)((h_scale >> 8) & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) /* Vertical prescaling etc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) set_v_scale(sd, 0, v_scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) set_v_scale(sd, 1, v_scale);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* set video output size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* video number of pixels at output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) /* TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) saa717x_write(sd, 0x5C, (u8)(fmt->width & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) saa717x_write(sd, 0x5D, (u8)((fmt->width >> 8) & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* TASK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) saa717x_write(sd, 0x9C, (u8)(fmt->width & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) saa717x_write(sd, 0x9D, (u8)((fmt->width >> 8) & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) /* video number of lines at output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* TASK A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) saa717x_write(sd, 0x5E, (u8)(fmt->height & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) saa717x_write(sd, 0x5F, (u8)((fmt->height >> 8) & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* TASK B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) saa717x_write(sd, 0x9E, (u8)(fmt->height & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) saa717x_write(sd, 0x9F, (u8)((fmt->height >> 8) & 0xFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) static int saa717x_s_radio(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct saa717x_state *decoder = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) decoder->radio = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static int saa717x_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct saa717x_state *decoder = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) v4l2_dbg(1, debug, sd, "decoder set norm ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) v4l2_dbg(1, debug, sd, "(not yet implemented)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) decoder->radio = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) decoder->std = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static int saa717x_s_audio_routing(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct saa717x_state *decoder = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (input < 3) { /* FIXME! --tadachi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) decoder->audio_input = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) "set decoder audio input to %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) decoder->audio_input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) set_audio_regs(sd, decoder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return -ERANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static int saa717x_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct saa717x_state *decoder = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) v4l2_dbg(1, debug, sd, "decoder %s output\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) enable ? "enable" : "disable");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) decoder->enable = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) saa717x_write(sd, 0x193, enable ? 0xa6 : 0x26);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) /* change audio mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static int saa717x_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *vt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct saa717x_state *decoder = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) int audio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) char *mes[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) "MONO", "STEREO", "LANG1", "LANG2/SAP"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) audio_mode = TUNER_AUDIO_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) switch (vt->audmode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) case V4L2_TUNER_MODE_MONO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) audio_mode = TUNER_AUDIO_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) case V4L2_TUNER_MODE_STEREO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) audio_mode = TUNER_AUDIO_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) case V4L2_TUNER_MODE_LANG2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) audio_mode = TUNER_AUDIO_LANG2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) case V4L2_TUNER_MODE_LANG1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) audio_mode = TUNER_AUDIO_LANG1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) v4l2_dbg(1, debug, sd, "change audio mode to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) mes[audio_mode]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) decoder->tuner_audio_mode = audio_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* The registers are not changed here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /* See DECODER_ENABLE_OUTPUT section. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) set_audio_mode(sd, decoder->tuner_audio_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static int saa717x_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) struct saa717x_state *decoder = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) int dual_f, stereo_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (decoder->radio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) get_inf_dev_status(sd, &dual_f, &stereo_f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) v4l2_dbg(1, debug, sd, "DETECT==st:%d dual:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) stereo_f, dual_f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* mono */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if ((dual_f == 0) && (stereo_f == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) vt->rxsubchans = V4L2_TUNER_SUB_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) v4l2_dbg(1, debug, sd, "DETECT==MONO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /* stereo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (stereo_f == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (vt->audmode == V4L2_TUNER_MODE_STEREO ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) vt->audmode == V4L2_TUNER_MODE_LANG1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) vt->rxsubchans = V4L2_TUNER_SUB_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) v4l2_dbg(1, debug, sd, "DETECT==ST(ST)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) vt->rxsubchans = V4L2_TUNER_SUB_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) v4l2_dbg(1, debug, sd, "DETECT==ST(MONO)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) /* dual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (dual_f == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (vt->audmode == V4L2_TUNER_MODE_LANG2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) vt->rxsubchans = V4L2_TUNER_SUB_LANG2 | V4L2_TUNER_SUB_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) v4l2_dbg(1, debug, sd, "DETECT==DUAL1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) vt->rxsubchans = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_MONO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) v4l2_dbg(1, debug, sd, "DETECT==DUAL2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static int saa717x_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct saa717x_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) v4l2_ctrl_handler_log_status(&state->hdl, sd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static const struct v4l2_ctrl_ops saa717x_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .s_ctrl = saa717x_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static const struct v4l2_subdev_core_ops saa717x_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .g_register = saa717x_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .s_register = saa717x_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .log_status = saa717x_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) static const struct v4l2_subdev_tuner_ops saa717x_tuner_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .g_tuner = saa717x_g_tuner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .s_tuner = saa717x_s_tuner,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .s_radio = saa717x_s_radio,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) static const struct v4l2_subdev_video_ops saa717x_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .s_std = saa717x_s_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .s_routing = saa717x_s_video_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .s_stream = saa717x_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) static const struct v4l2_subdev_audio_ops saa717x_audio_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .s_routing = saa717x_s_audio_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static const struct v4l2_subdev_pad_ops saa717x_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .set_fmt = saa717x_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static const struct v4l2_subdev_ops saa717x_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) .core = &saa717x_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .tuner = &saa717x_tuner_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .audio = &saa717x_audio_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .video = &saa717x_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .pad = &saa717x_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /* i2c implementation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) static int saa717x_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) const struct i2c_device_id *did)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct saa717x_state *decoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct v4l2_ctrl_handler *hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) u8 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) char *p = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (decoder == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) sd = &decoder->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) v4l2_i2c_subdev_init(sd, client, &saa717x_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) if (saa717x_write(sd, 0x5a4, 0xfe) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) saa717x_write(sd, 0x5a5, 0x0f) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) saa717x_write(sd, 0x5a6, 0x00) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) saa717x_write(sd, 0x5a7, 0x01))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) id = saa717x_read(sd, 0x5a0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (id != 0xc2 && id != 0x32 && id != 0xf2 && id != 0x6c) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) v4l2_dbg(1, debug, sd, "saa717x not found (id=%02x)\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (id == 0xc2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) p = "saa7173";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) else if (id == 0x32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) p = "saa7174A";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) else if (id == 0x6c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) p = "saa7174HL";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) p = "saa7171";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) v4l2_info(sd, "%s found @ 0x%x (%s)\n", p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) hdl = &decoder->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) v4l2_ctrl_handler_init(hdl, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* add in ascending ID order */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) v4l2_ctrl_new_std(hdl, &saa717x_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) v4l2_ctrl_new_std(hdl, &saa717x_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) V4L2_CID_CONTRAST, 0, 255, 1, 68);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) v4l2_ctrl_new_std(hdl, &saa717x_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) V4L2_CID_SATURATION, 0, 255, 1, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) v4l2_ctrl_new_std(hdl, &saa717x_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) V4L2_CID_HUE, -128, 127, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) v4l2_ctrl_new_std(hdl, &saa717x_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) V4L2_CID_AUDIO_VOLUME, 0, 65535, 65535 / 100, 42000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) v4l2_ctrl_new_std(hdl, &saa717x_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) V4L2_CID_AUDIO_BALANCE, 0, 65535, 65535 / 100, 32768);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) v4l2_ctrl_new_std(hdl, &saa717x_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) V4L2_CID_AUDIO_BASS, -16, 15, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) v4l2_ctrl_new_std(hdl, &saa717x_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) V4L2_CID_AUDIO_TREBLE, -16, 15, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) v4l2_ctrl_new_std(hdl, &saa717x_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) V4L2_CID_AUDIO_MUTE, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) sd->ctrl_handler = hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) if (hdl->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) int err = hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) v4l2_ctrl_handler_free(hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) decoder->std = V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) decoder->input = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) decoder->enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /* FIXME!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) decoder->playback = 0; /* initially capture mode used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) decoder->audio = 1; /* DECODER_AUDIO_48_KHZ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) decoder->audio_input = 2; /* FIXME!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) decoder->tuner_audio_mode = TUNER_AUDIO_STEREO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) /* set volume, bass and treble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) decoder->audio_main_vol_l = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) decoder->audio_main_vol_r = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) v4l2_dbg(1, debug, sd, "writing init values\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /* FIXME!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) saa717x_write_regs(sd, reg_init_initialize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) v4l2_ctrl_handler_setup(hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) set_current_state(TASK_INTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) schedule_timeout(2*HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) static int saa717x_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) v4l2_ctrl_handler_free(sd->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static const struct i2c_device_id saa717x_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) { "saa717x", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) MODULE_DEVICE_TABLE(i2c, saa717x_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) static struct i2c_driver saa717x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .name = "saa717x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .probe = saa717x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) .remove = saa717x_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) .id_table = saa717x_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) module_i2c_driver(saa717x_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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