^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * saa7127 - Philips SAA7127/SAA7129 video encoder driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2003 Roy Bulter <rbulter@hetnet.nl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on SAA7126 video encoder driver by Gillem & Andreas Oberritter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2000-2001 Gillem <htoa@gmx.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2002 Andreas Oberritter <obi@saftware.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Based on Stadis 4:2:2 MPEG-2 Decoder Driver by Nathan Laredo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 1999 Nathan Laredo <laredo@gnu.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * This driver is designed for the Hauppauge 250/350 Linux driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * from the ivtv Project
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Copyright (C) 2003 Kevin Thayer <nufan_wfk@yahoo.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Dual output support:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Copyright (C) 2004 Eric Varsanyi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * NTSC Tuning and 7.5 IRE Setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Copyright (C) 2004 Chris Kennedy <c@groovy.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * VBI additions & cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Copyright (C) 2004, 2005 Hans Verkuil <hverkuil@xs4all.nl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * Note: the saa7126 is identical to the saa7127, and the saa7128 is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * identical to the saa7129, except that the saa7126 and saa7128 have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * macrovision anti-taping support. This driver will almost certainly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * work fine for those chips, except of course for the missing anti-taping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include <media/i2c/saa7127.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static int test_image;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MODULE_DESCRIPTION("Philips SAA7127/9 video encoder driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MODULE_AUTHOR("Kevin Thayer, Chris Kennedy, Hans Verkuil");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) module_param(test_image, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MODULE_PARM_DESC(debug, "debug level (0-2)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MODULE_PARM_DESC(test_image, "test_image (0-1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * SAA7127 registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SAA7127_REG_STATUS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SAA7127_REG_WIDESCREEN_CONFIG 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SAA7127_REG_WIDESCREEN_ENABLE 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SAA7127_REG_BURST_START 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SAA7127_REG_BURST_END 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SAA7127_REG_COPYGEN_0 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SAA7127_REG_COPYGEN_1 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SAA7127_REG_COPYGEN_2 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SAA7127_REG_OUTPUT_PORT_CONTROL 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SAA7127_REG_GAIN_LUMINANCE_RGB 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SAA7127_REG_GAIN_COLORDIFF_RGB 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SAA7127_REG_INPUT_PORT_CONTROL_1 0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SAA7129_REG_FADE_KEY_COL2 0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SAA7127_REG_CHROMA_PHASE 0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SAA7127_REG_GAINU 0x5b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SAA7127_REG_GAINV 0x5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SAA7127_REG_BLACK_LEVEL 0x5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SAA7127_REG_BLANKING_LEVEL 0x5e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SAA7127_REG_VBI_BLANKING 0x5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SAA7127_REG_DAC_CONTROL 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SAA7127_REG_BURST_AMP 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SAA7127_REG_SUBC3 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SAA7127_REG_SUBC2 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SAA7127_REG_SUBC1 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SAA7127_REG_SUBC0 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SAA7127_REG_LINE_21_ODD_0 0x67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SAA7127_REG_LINE_21_ODD_1 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SAA7127_REG_LINE_21_EVEN_0 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SAA7127_REG_LINE_21_EVEN_1 0x6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SAA7127_REG_RCV_PORT_CONTROL 0x6b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SAA7127_REG_VTRIG 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SAA7127_REG_HTRIG_HI 0x6d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SAA7127_REG_MULTI 0x6e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SAA7127_REG_CLOSED_CAPTION 0x6f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SAA7127_REG_RCV2_OUTPUT_START 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SAA7127_REG_RCV2_OUTPUT_END 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SAA7127_REG_RCV2_OUTPUT_MSBS 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SAA7127_REG_TTX_REQUEST_H_START 0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SAA7127_REG_TTX_REQUEST_H_DELAY_LENGTH 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SAA7127_REG_CSYNC_ADVANCE_VSYNC_SHIFT 0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SAA7127_REG_TTX_ODD_REQ_VERT_START 0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SAA7127_REG_TTX_ODD_REQ_VERT_END 0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SAA7127_REG_TTX_EVEN_REQ_VERT_START 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SAA7127_REG_TTX_EVEN_REQ_VERT_END 0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SAA7127_REG_FIRST_ACTIVE 0x7a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SAA7127_REG_LAST_ACTIVE 0x7b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SAA7127_REG_MSB_VERTICAL 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SAA7127_REG_DISABLE_TTX_LINE_LO_0 0x7e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SAA7127_REG_DISABLE_TTX_LINE_LO_1 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) **********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * Arrays with configuration parameters for the SAA7127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) **********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct i2c_reg_value {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned char reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned char value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct i2c_reg_value saa7129_init_config_extra[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { SAA7127_REG_OUTPUT_PORT_CONTROL, 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { SAA7127_REG_VTRIG, 0xfa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct i2c_reg_value saa7127_init_config_common[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { SAA7127_REG_WIDESCREEN_CONFIG, 0x0d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { SAA7127_REG_WIDESCREEN_ENABLE, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { SAA7127_REG_COPYGEN_0, 0x77 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { SAA7127_REG_COPYGEN_1, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { SAA7127_REG_COPYGEN_2, 0x00 }, /* Macrovision enable/disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { SAA7127_REG_OUTPUT_PORT_CONTROL, 0xbf },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { SAA7127_REG_GAIN_LUMINANCE_RGB, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { SAA7127_REG_GAIN_COLORDIFF_RGB, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { SAA7127_REG_INPUT_PORT_CONTROL_1, 0x80 }, /* for color bars */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { SAA7127_REG_LINE_21_ODD_0, 0x77 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { SAA7127_REG_LINE_21_ODD_1, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { SAA7127_REG_LINE_21_EVEN_0, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { SAA7127_REG_LINE_21_EVEN_1, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { SAA7127_REG_RCV_PORT_CONTROL, 0x12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { SAA7127_REG_VTRIG, 0xf9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { SAA7127_REG_HTRIG_HI, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { SAA7127_REG_RCV2_OUTPUT_START, 0x41 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { SAA7127_REG_RCV2_OUTPUT_END, 0xc3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { SAA7127_REG_RCV2_OUTPUT_MSBS, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { SAA7127_REG_TTX_REQUEST_H_START, 0x3e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { SAA7127_REG_TTX_REQUEST_H_DELAY_LENGTH, 0xb8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { SAA7127_REG_CSYNC_ADVANCE_VSYNC_SHIFT, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { SAA7127_REG_TTX_ODD_REQ_VERT_START, 0x15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { SAA7127_REG_TTX_ODD_REQ_VERT_END, 0x16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { SAA7127_REG_TTX_EVEN_REQ_VERT_START, 0x15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { SAA7127_REG_TTX_EVEN_REQ_VERT_END, 0x16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { SAA7127_REG_FIRST_ACTIVE, 0x1a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { SAA7127_REG_LAST_ACTIVE, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { SAA7127_REG_MSB_VERTICAL, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { SAA7127_REG_DISABLE_TTX_LINE_LO_0, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { SAA7127_REG_DISABLE_TTX_LINE_LO_1, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SAA7127_60HZ_DAC_CONTROL 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const struct i2c_reg_value saa7127_init_config_60hz[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { SAA7127_REG_BURST_START, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* BURST_END is also used as a chip ID in saa7127_probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { SAA7127_REG_BURST_END, 0x1d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { SAA7127_REG_CHROMA_PHASE, 0xa3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { SAA7127_REG_GAINU, 0x98 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { SAA7127_REG_GAINV, 0xd3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { SAA7127_REG_BLACK_LEVEL, 0x39 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { SAA7127_REG_BLANKING_LEVEL, 0x2e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { SAA7127_REG_VBI_BLANKING, 0x2e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { SAA7127_REG_DAC_CONTROL, 0x15 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { SAA7127_REG_BURST_AMP, 0x4d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { SAA7127_REG_SUBC3, 0x1f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { SAA7127_REG_SUBC2, 0x7c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { SAA7127_REG_SUBC1, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { SAA7127_REG_SUBC0, 0x21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { SAA7127_REG_MULTI, 0x90 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { SAA7127_REG_CLOSED_CAPTION, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SAA7127_50HZ_PAL_DAC_CONTROL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static struct i2c_reg_value saa7127_init_config_50hz_pal[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { SAA7127_REG_BURST_START, 0x21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* BURST_END is also used as a chip ID in saa7127_probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { SAA7127_REG_BURST_END, 0x1d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { SAA7127_REG_CHROMA_PHASE, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { SAA7127_REG_GAINU, 0x7d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { SAA7127_REG_GAINV, 0xaf },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { SAA7127_REG_BLACK_LEVEL, 0x33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { SAA7127_REG_BLANKING_LEVEL, 0x35 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { SAA7127_REG_VBI_BLANKING, 0x35 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { SAA7127_REG_DAC_CONTROL, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { SAA7127_REG_BURST_AMP, 0x2f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { SAA7127_REG_SUBC3, 0xcb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { SAA7127_REG_SUBC2, 0x8a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { SAA7127_REG_SUBC1, 0x09 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { SAA7127_REG_SUBC0, 0x2a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { SAA7127_REG_MULTI, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { SAA7127_REG_CLOSED_CAPTION, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SAA7127_50HZ_SECAM_DAC_CONTROL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static struct i2c_reg_value saa7127_init_config_50hz_secam[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { SAA7127_REG_BURST_START, 0x21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* BURST_END is also used as a chip ID in saa7127_probe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { SAA7127_REG_BURST_END, 0x1d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { SAA7127_REG_CHROMA_PHASE, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { SAA7127_REG_GAINU, 0x6a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { SAA7127_REG_GAINV, 0x81 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { SAA7127_REG_BLACK_LEVEL, 0x33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { SAA7127_REG_BLANKING_LEVEL, 0x35 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { SAA7127_REG_VBI_BLANKING, 0x35 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { SAA7127_REG_DAC_CONTROL, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { SAA7127_REG_BURST_AMP, 0x2f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { SAA7127_REG_SUBC3, 0xb2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { SAA7127_REG_SUBC2, 0x3b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { SAA7127_REG_SUBC1, 0xa3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { SAA7127_REG_SUBC0, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { SAA7127_REG_MULTI, 0x90 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { SAA7127_REG_CLOSED_CAPTION, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { 0, 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) **********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * Encoder Struct, holds the configuration state of the encoder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) **********************************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) enum saa712x_model {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) SAA7127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) SAA7129,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct saa7127_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) v4l2_std_id std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) enum saa712x_model ident;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) enum saa7127_input_type input_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) enum saa7127_output_type output_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int video_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int wss_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u16 wss_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) int cc_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u16 cc_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int xds_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u16 xds_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int vps_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u8 vps_data[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u8 reg_2d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u8 reg_3a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u8 reg_3a_cb; /* colorbar bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u8 reg_61;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static inline struct saa7127_state *to_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return container_of(sd, struct saa7127_state, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static const char * const output_strs[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "S-Video + Composite",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "Composite",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "S-Video",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "RGB",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "YUV C",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "YUV V"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static const char * const wss_strs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "letterbox 14:9 center",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "letterbox 14:9 top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "letterbox 16:9 top",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "16:9 full format anamorphic",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "4:3 full format",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "letterbox 16:9 center",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "letterbox >16:9 center",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "14:9 full format center",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "invalid",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int saa7127_read(struct v4l2_subdev *sd, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static int saa7127_write(struct v4l2_subdev *sd, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (i2c_smbus_write_byte_data(client, reg, val) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) v4l2_err(sd, "I2C Write Problem\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static int saa7127_write_inittab(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) const struct i2c_reg_value *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) while (regs->reg != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) saa7127_write(sd, regs->reg, regs->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) regs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int saa7127_set_vps(struct v4l2_subdev *sd, const struct v4l2_sliced_vbi_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct saa7127_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int enable = (data->line != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (enable && (data->field != 0 || data->line != 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (state->vps_enable != enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) v4l2_dbg(1, debug, sd, "Turn VPS Signal %s\n", enable ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) saa7127_write(sd, 0x54, enable << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) state->vps_enable = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) state->vps_data[0] = data->data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) state->vps_data[1] = data->data[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) state->vps_data[2] = data->data[9];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) state->vps_data[3] = data->data[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) state->vps_data[4] = data->data[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) v4l2_dbg(1, debug, sd, "Set VPS data %*ph\n", 5, state->vps_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) saa7127_write(sd, 0x55, state->vps_data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) saa7127_write(sd, 0x56, state->vps_data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) saa7127_write(sd, 0x57, state->vps_data[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) saa7127_write(sd, 0x58, state->vps_data[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) saa7127_write(sd, 0x59, state->vps_data[4]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int saa7127_set_cc(struct v4l2_subdev *sd, const struct v4l2_sliced_vbi_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct saa7127_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u16 cc = data->data[1] << 8 | data->data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) int enable = (data->line != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (enable && (data->field != 0 || data->line != 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (state->cc_enable != enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "Turn CC %s\n", enable ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) saa7127_write(sd, SAA7127_REG_CLOSED_CAPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) (state->xds_enable << 7) | (enable << 6) | 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) state->cc_enable = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) v4l2_dbg(2, debug, sd, "CC data: %04x\n", cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) saa7127_write(sd, SAA7127_REG_LINE_21_ODD_0, cc & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) saa7127_write(sd, SAA7127_REG_LINE_21_ODD_1, cc >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) state->cc_data = cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int saa7127_set_xds(struct v4l2_subdev *sd, const struct v4l2_sliced_vbi_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct saa7127_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u16 xds = data->data[1] << 8 | data->data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int enable = (data->line != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (enable && (data->field != 1 || data->line != 21))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if (state->xds_enable != enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) v4l2_dbg(1, debug, sd, "Turn XDS %s\n", enable ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) saa7127_write(sd, SAA7127_REG_CLOSED_CAPTION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) (enable << 7) | (state->cc_enable << 6) | 0x11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) state->xds_enable = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) v4l2_dbg(2, debug, sd, "XDS data: %04x\n", xds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) saa7127_write(sd, SAA7127_REG_LINE_21_EVEN_0, xds & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) saa7127_write(sd, SAA7127_REG_LINE_21_EVEN_1, xds >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) state->xds_data = xds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static int saa7127_set_wss(struct v4l2_subdev *sd, const struct v4l2_sliced_vbi_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) struct saa7127_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int enable = (data->line != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (enable && (data->field != 0 || data->line != 23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (state->wss_enable != enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) v4l2_dbg(1, debug, sd, "Turn WSS %s\n", enable ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) saa7127_write(sd, 0x27, enable << 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) state->wss_enable = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) saa7127_write(sd, 0x26, data->data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) saa7127_write(sd, 0x27, 0x80 | (data->data[1] & 0x3f));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) "WSS mode: %s\n", wss_strs[data->data[0] & 0xf]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) state->wss_mode = (data->data[1] & 0x3f) << 8 | data->data[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static int saa7127_set_video_enable(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct saa7127_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) v4l2_dbg(1, debug, sd, "Enable Video Output\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) saa7127_write(sd, 0x2d, state->reg_2d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) saa7127_write(sd, 0x61, state->reg_61);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) v4l2_dbg(1, debug, sd, "Disable Video Output\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) saa7127_write(sd, 0x2d, (state->reg_2d & 0xf0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) saa7127_write(sd, 0x61, (state->reg_61 | 0xc0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) state->video_enable = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int saa7127_set_std(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) struct saa7127_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) const struct i2c_reg_value *inittab;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (std & V4L2_STD_525_60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) v4l2_dbg(1, debug, sd, "Selecting 60 Hz video Standard\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) inittab = saa7127_init_config_60hz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) state->reg_61 = SAA7127_60HZ_DAC_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } else if (state->ident == SAA7129 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) (std & V4L2_STD_SECAM) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) !(std & (V4L2_STD_625_50 & ~V4L2_STD_SECAM))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* If and only if SECAM, with a SAA712[89] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) "Selecting 50 Hz SECAM video Standard\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) inittab = saa7127_init_config_50hz_secam;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) state->reg_61 = SAA7127_50HZ_SECAM_DAC_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) v4l2_dbg(1, debug, sd, "Selecting 50 Hz PAL video Standard\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) inittab = saa7127_init_config_50hz_pal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) state->reg_61 = SAA7127_50HZ_PAL_DAC_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* Write Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) saa7127_write_inittab(sd, inittab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) state->std = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static int saa7127_set_output_type(struct v4l2_subdev *sd, int output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct saa7127_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) switch (output) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) case SAA7127_OUTPUT_TYPE_RGB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) state->reg_2d = 0x0f; /* RGB + CVBS (for sync) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) state->reg_3a = 0x13; /* by default switch YUV to RGB-matrix on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) case SAA7127_OUTPUT_TYPE_COMPOSITE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (state->ident == SAA7129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) state->reg_2d = 0x20; /* CVBS only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) state->reg_2d = 0x08; /* 00001000 CVBS only, RGB DAC's off (high impedance mode) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) state->reg_3a = 0x13; /* by default switch YUV to RGB-matrix on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) case SAA7127_OUTPUT_TYPE_SVIDEO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (state->ident == SAA7129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) state->reg_2d = 0x18; /* Y + C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) state->reg_2d = 0xff; /*11111111 croma -> R, luma -> CVBS + G + B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) state->reg_3a = 0x13; /* by default switch YUV to RGB-matrix on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) case SAA7127_OUTPUT_TYPE_YUV_V:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) state->reg_2d = 0x4f; /* reg 2D = 01001111, all DAC's on, RGB + VBS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) state->reg_3a = 0x0b; /* reg 3A = 00001011, bypass RGB-matrix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) case SAA7127_OUTPUT_TYPE_YUV_C:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) state->reg_2d = 0x0f; /* reg 2D = 00001111, all DAC's on, RGB + CVBS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) state->reg_3a = 0x0b; /* reg 3A = 00001011, bypass RGB-matrix */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case SAA7127_OUTPUT_TYPE_BOTH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (state->ident == SAA7129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) state->reg_2d = 0x38;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) state->reg_2d = 0xbf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) state->reg_3a = 0x13; /* by default switch YUV to RGB-matrix on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) v4l2_dbg(1, debug, sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) "Selecting %s output type\n", output_strs[output]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Configure Encoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) saa7127_write(sd, 0x2d, state->reg_2d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) saa7127_write(sd, 0x3a, state->reg_3a | state->reg_3a_cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) state->output_type = output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static int saa7127_set_input_type(struct v4l2_subdev *sd, int input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) struct saa7127_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) switch (input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) case SAA7127_INPUT_TYPE_NORMAL: /* avia */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) v4l2_dbg(1, debug, sd, "Selecting Normal Encoder Input\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) state->reg_3a_cb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) case SAA7127_INPUT_TYPE_TEST_IMAGE: /* color bar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) v4l2_dbg(1, debug, sd, "Selecting Color Bar generator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) state->reg_3a_cb = 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) saa7127_write(sd, 0x3a, state->reg_3a | state->reg_3a_cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) state->input_type = input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static int saa7127_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct saa7127_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (state->std == std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return saa7127_set_std(sd, std);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) static int saa7127_s_routing(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct saa7127_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (state->input_type != input)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) rc = saa7127_set_input_type(sd, input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (rc == 0 && state->output_type != output)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) rc = saa7127_set_output_type(sd, output);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static int saa7127_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct saa7127_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (state->video_enable == enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return saa7127_set_video_enable(sd, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static int saa7127_g_sliced_fmt(struct v4l2_subdev *sd, struct v4l2_sliced_vbi_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct saa7127_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) memset(fmt->service_lines, 0, sizeof(fmt->service_lines));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) if (state->vps_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) fmt->service_lines[0][16] = V4L2_SLICED_VPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (state->wss_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) fmt->service_lines[0][23] = V4L2_SLICED_WSS_625;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (state->cc_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) fmt->service_lines[0][21] = V4L2_SLICED_CAPTION_525;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) fmt->service_lines[1][21] = V4L2_SLICED_CAPTION_525;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) fmt->service_set =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) (state->vps_enable ? V4L2_SLICED_VPS : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) (state->wss_enable ? V4L2_SLICED_WSS_625 : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) (state->cc_enable ? V4L2_SLICED_CAPTION_525 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) static int saa7127_s_vbi_data(struct v4l2_subdev *sd, const struct v4l2_sliced_vbi_data *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) switch (data->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) case V4L2_SLICED_WSS_625:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return saa7127_set_wss(sd, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) case V4L2_SLICED_VPS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return saa7127_set_vps(sd, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) case V4L2_SLICED_CAPTION_525:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (data->field == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return saa7127_set_cc(sd, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return saa7127_set_xds(sd, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static int saa7127_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) reg->val = saa7127_read(sd, reg->reg & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) reg->size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int saa7127_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) saa7127_write(sd, reg->reg & 0xff, reg->val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static int saa7127_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct saa7127_state *state = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) v4l2_info(sd, "Standard: %s\n", (state->std & V4L2_STD_525_60) ? "60 Hz" : "50 Hz");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) v4l2_info(sd, "Input: %s\n", state->input_type ? "color bars" : "normal");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) v4l2_info(sd, "Output: %s\n", state->video_enable ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) output_strs[state->output_type] : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) v4l2_info(sd, "WSS: %s\n", state->wss_enable ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) wss_strs[state->wss_mode] : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) v4l2_info(sd, "VPS: %s\n", state->vps_enable ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) v4l2_info(sd, "CC: %s\n", state->cc_enable ? "enabled" : "disabled");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static const struct v4l2_subdev_core_ops saa7127_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .log_status = saa7127_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .g_register = saa7127_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .s_register = saa7127_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static const struct v4l2_subdev_video_ops saa7127_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .s_std_output = saa7127_s_std_output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .s_routing = saa7127_s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .s_stream = saa7127_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static const struct v4l2_subdev_vbi_ops saa7127_vbi_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .s_vbi_data = saa7127_s_vbi_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .g_sliced_fmt = saa7127_g_sliced_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static const struct v4l2_subdev_ops saa7127_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .core = &saa7127_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .video = &saa7127_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .vbi = &saa7127_vbi_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static int saa7127_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct saa7127_state *state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct v4l2_sliced_vbi_data vbi = { 0, 0, 0, 0 }; /* set to disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) /* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) v4l_dbg(1, debug, client, "detecting saa7127 client on address 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) client->addr << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (state == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) sd = &state->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) v4l2_i2c_subdev_init(sd, client, &saa7127_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* First test register 0: Bits 5-7 are a version ID (should be 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) and bit 2 should also be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) This is rather general, so the second test is more specific and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) looks at the 'ending point of burst in clock cycles' which is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) 0x1d after a reset and not expected to ever change. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if ((saa7127_read(sd, 0) & 0xe4) != 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) (saa7127_read(sd, 0x29) & 0x3f) != 0x1d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) v4l2_dbg(1, debug, sd, "saa7127 not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (id->driver_data) { /* Chip type is already known */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) state->ident = id->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) } else { /* Needs detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) int read_result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Detect if it's an saa7129 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) read_result = saa7127_read(sd, SAA7129_REG_FADE_KEY_COL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) saa7127_write(sd, SAA7129_REG_FADE_KEY_COL2, 0xaa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (saa7127_read(sd, SAA7129_REG_FADE_KEY_COL2) == 0xaa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) saa7127_write(sd, SAA7129_REG_FADE_KEY_COL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) read_result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) state->ident = SAA7129;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) strscpy(client->name, "saa7129", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) state->ident = SAA7127;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) strscpy(client->name, "saa7127", I2C_NAME_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) v4l2_dbg(1, debug, sd, "Configuring encoder\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) saa7127_write_inittab(sd, saa7127_init_config_common);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) saa7127_set_std(sd, V4L2_STD_NTSC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) saa7127_set_output_type(sd, SAA7127_OUTPUT_TYPE_BOTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) saa7127_set_vps(sd, &vbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) saa7127_set_wss(sd, &vbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) saa7127_set_cc(sd, &vbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) saa7127_set_xds(sd, &vbi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (test_image == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* The Encoder has an internal Colorbar generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* This can be used for debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) saa7127_set_input_type(sd, SAA7127_INPUT_TYPE_TEST_IMAGE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) saa7127_set_input_type(sd, SAA7127_INPUT_TYPE_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) saa7127_set_video_enable(sd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (state->ident == SAA7129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) saa7127_write_inittab(sd, saa7129_init_config_extra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static int saa7127_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* Turn off TV output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) saa7127_set_video_enable(sd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static const struct i2c_device_id saa7127_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) { "saa7127_auto", 0 }, /* auto-detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) { "saa7126", SAA7127 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) { "saa7127", SAA7127 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) { "saa7128", SAA7129 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) { "saa7129", SAA7129 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) MODULE_DEVICE_TABLE(i2c, saa7127_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static struct i2c_driver saa7127_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .name = "saa7127",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .probe = saa7127_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .remove = saa7127_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .id_table = saa7127_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) module_i2c_driver(saa7127_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags