^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * saa711x - Philips SAA711x video decoder register specifications
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2006 Mauro Carvalho Chehab <mchehab@kernel.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define R_00_CHIP_VERSION 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* Video Decoder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* Video Decoder - Frontend part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define R_01_INC_DELAY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define R_02_INPUT_CNTL_1 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define R_03_INPUT_CNTL_2 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define R_04_INPUT_CNTL_3 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define R_05_INPUT_CNTL_4 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Video Decoder - Decoder part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define R_06_H_SYNC_START 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define R_07_H_SYNC_STOP 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define R_08_SYNC_CNTL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define R_09_LUMA_CNTL 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define R_0A_LUMA_BRIGHT_CNTL 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define R_0B_LUMA_CONTRAST_CNTL 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define R_0C_CHROMA_SAT_CNTL 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define R_0D_CHROMA_HUE_CNTL 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define R_0E_CHROMA_CNTL_1 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define R_0F_CHROMA_GAIN_CNTL 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define R_10_CHROMA_CNTL_2 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define R_11_MODE_DELAY_CNTL 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define R_12_RT_SIGNAL_CNTL 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define R_13_RT_X_PORT_OUT_CNTL 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define R_14_ANAL_ADC_COMPAT_CNTL 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define R_15_VGATE_START_FID_CHG 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define R_16_VGATE_STOP 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define R_17_MISC_VGATE_CONF_AND_MSB 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define R_18_RAW_DATA_GAIN_CNTL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define R_19_RAW_DATA_OFF_CNTL 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define R_1A_COLOR_KILL_LVL_CNTL 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define R_1B_MISC_TVVCRDET 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define R_1C_ENHAN_COMB_CTRL1 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define R_1D_ENHAN_COMB_CTRL2 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define R_1E_STATUS_BYTE_1_VD_DEC 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define R_1F_STATUS_BYTE_2_VD_DEC 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Component processing and interrupt masking part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define R_23_INPUT_CNTL_5 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define R_24_INPUT_CNTL_6 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define R_25_INPUT_CNTL_7 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define R_29_COMP_DELAY 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define R_2A_COMP_BRIGHT_CNTL 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define R_2B_COMP_CONTRAST_CNTL 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define R_2C_COMP_SAT_CNTL 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define R_2D_INTERRUPT_MASK_1 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define R_2E_INTERRUPT_MASK_2 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define R_2F_INTERRUPT_MASK_3 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Audio clock generator part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define R_30_AUD_MAST_CLK_CYCLES_PER_FIELD 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define R_34_AUD_MAST_CLK_NOMINAL_INC 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define R_38_CLK_RATIO_AMXCLK_TO_ASCLK 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define R_39_CLK_RATIO_ASCLK_TO_ALRCLK 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define R_3A_AUD_CLK_GEN_BASIC_SETUP 0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* General purpose VBI data slicer part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define R_40_SLICER_CNTL_1 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define R_41_LCR_BASE 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define R_58_PROGRAM_FRAMING_CODE 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define R_59_H_OFF_FOR_SLICER 0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define R_5A_V_OFF_FOR_SLICER 0x5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF 0x5b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define R_5D_DID 0x5d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define R_5E_SDID 0x5e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define R_60_SLICER_STATUS_BYTE_0 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define R_61_SLICER_STATUS_BYTE_1 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define R_62_SLICER_STATUS_BYTE_2 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* X port, I port and the scaler part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Task independent global settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define R_80_GLOBAL_CNTL_1 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define R_83_X_PORT_I_O_ENA_AND_OUT_CLK 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define R_84_I_PORT_SIGNAL_DEF 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define R_85_I_PORT_SIGNAL_POLAR 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define R_88_POWER_SAVE_ADC_PORT_CNTL 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define R_8F_STATUS_INFO_SCALER 0x8f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Task A definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Basic settings and acquisition window definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define R_90_A_TASK_HANDLING_CNTL 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define R_91_A_X_PORT_FORMATS_AND_CONF 0x91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL 0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF 0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define R_94_A_HORIZ_INPUT_WINDOW_START 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define R_95_A_HORIZ_INPUT_WINDOW_START_MSB 0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define R_96_A_HORIZ_INPUT_WINDOW_LENGTH 0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define R_97_A_HORIZ_INPUT_WINDOW_LENGTH_MSB 0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define R_98_A_VERT_INPUT_WINDOW_START 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define R_99_A_VERT_INPUT_WINDOW_START_MSB 0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define R_9A_A_VERT_INPUT_WINDOW_LENGTH 0x9a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define R_9B_A_VERT_INPUT_WINDOW_LENGTH_MSB 0x9b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH 0x9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define R_9D_A_HORIZ_OUTPUT_WINDOW_LENGTH_MSB 0x9d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define R_9E_A_VERT_OUTPUT_WINDOW_LENGTH 0x9e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define R_9F_A_VERT_OUTPUT_WINDOW_LENGTH_MSB 0x9f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* FIR filtering and prescaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define R_A0_A_HORIZ_PRESCALING 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define R_A1_A_ACCUMULATION_LENGTH 0xa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER 0xa2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define R_A4_A_LUMA_BRIGHTNESS_CNTL 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define R_A5_A_LUMA_CONTRAST_CNTL 0xa5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define R_A6_A_CHROMA_SATURATION_CNTL 0xa6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Horizontal phase scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define R_A8_A_HORIZ_LUMA_SCALING_INC 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define R_A9_A_HORIZ_LUMA_SCALING_INC_MSB 0xa9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define R_AA_A_HORIZ_LUMA_PHASE_OFF 0xaa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define R_AC_A_HORIZ_CHROMA_SCALING_INC 0xac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define R_AD_A_HORIZ_CHROMA_SCALING_INC_MSB 0xad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define R_AE_A_HORIZ_CHROMA_PHASE_OFF 0xae
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define R_AF_A_HORIZ_CHROMA_PHASE_OFF_MSB 0xaf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Vertical scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define R_B0_A_VERT_LUMA_SCALING_INC 0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define R_B1_A_VERT_LUMA_SCALING_INC_MSB 0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define R_B2_A_VERT_CHROMA_SCALING_INC 0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define R_B3_A_VERT_CHROMA_SCALING_INC_MSB 0xb3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define R_B4_A_VERT_SCALING_MODE_CNTL 0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define R_B8_A_VERT_CHROMA_PHASE_OFF_00 0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define R_B9_A_VERT_CHROMA_PHASE_OFF_01 0xb9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define R_BA_A_VERT_CHROMA_PHASE_OFF_10 0xba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define R_BB_A_VERT_CHROMA_PHASE_OFF_11 0xbb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define R_BC_A_VERT_LUMA_PHASE_OFF_00 0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define R_BD_A_VERT_LUMA_PHASE_OFF_01 0xbd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define R_BE_A_VERT_LUMA_PHASE_OFF_10 0xbe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define R_BF_A_VERT_LUMA_PHASE_OFF_11 0xbf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* Task B definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Basic settings and acquisition window definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define R_C0_B_TASK_HANDLING_CNTL 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define R_C1_B_X_PORT_FORMATS_AND_CONF 0xc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION 0xc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define R_C3_B_I_PORT_FORMATS_AND_CONF 0xc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define R_C4_B_HORIZ_INPUT_WINDOW_START 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define R_C5_B_HORIZ_INPUT_WINDOW_START_MSB 0xc5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define R_C6_B_HORIZ_INPUT_WINDOW_LENGTH 0xc6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define R_C7_B_HORIZ_INPUT_WINDOW_LENGTH_MSB 0xc7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define R_C8_B_VERT_INPUT_WINDOW_START 0xc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define R_C9_B_VERT_INPUT_WINDOW_START_MSB 0xc9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define R_CA_B_VERT_INPUT_WINDOW_LENGTH 0xca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define R_CB_B_VERT_INPUT_WINDOW_LENGTH_MSB 0xcb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH 0xcc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define R_CD_B_HORIZ_OUTPUT_WINDOW_LENGTH_MSB 0xcd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define R_CE_B_VERT_OUTPUT_WINDOW_LENGTH 0xce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define R_CF_B_VERT_OUTPUT_WINDOW_LENGTH_MSB 0xcf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* FIR filtering and prescaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define R_D0_B_HORIZ_PRESCALING 0xd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define R_D1_B_ACCUMULATION_LENGTH 0xd1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER 0xd2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define R_D4_B_LUMA_BRIGHTNESS_CNTL 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define R_D5_B_LUMA_CONTRAST_CNTL 0xd5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define R_D6_B_CHROMA_SATURATION_CNTL 0xd6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Horizontal phase scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define R_D8_B_HORIZ_LUMA_SCALING_INC 0xd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define R_D9_B_HORIZ_LUMA_SCALING_INC_MSB 0xd9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define R_DA_B_HORIZ_LUMA_PHASE_OFF 0xda
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define R_DC_B_HORIZ_CHROMA_SCALING 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define R_DD_B_HORIZ_CHROMA_SCALING_MSB 0xdd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA 0xde
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* Vertical scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define R_E0_B_VERT_LUMA_SCALING_INC 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define R_E1_B_VERT_LUMA_SCALING_INC_MSB 0xe1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define R_E2_B_VERT_CHROMA_SCALING_INC 0xe2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define R_E3_B_VERT_CHROMA_SCALING_INC_MSB 0xe3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define R_E4_B_VERT_SCALING_MODE_CNTL 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define R_E8_B_VERT_CHROMA_PHASE_OFF_00 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define R_E9_B_VERT_CHROMA_PHASE_OFF_01 0xe9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define R_EA_B_VERT_CHROMA_PHASE_OFF_10 0xea
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define R_EB_B_VERT_CHROMA_PHASE_OFF_11 0xeb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define R_EC_B_VERT_LUMA_PHASE_OFF_00 0xec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define R_ED_B_VERT_LUMA_PHASE_OFF_01 0xed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define R_EE_B_VERT_LUMA_PHASE_OFF_10 0xee
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define R_EF_B_VERT_LUMA_PHASE_OFF_11 0xef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* second PLL (PLL2) and Pulsegenerator Programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define R_F0_LFCO_PER_LINE 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define R_F1_P_I_PARAM_SELECT 0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define R_F2_NOMINAL_PLL2_DTO 0xf2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define R_F3_PLL_INCREMENT 0xf3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define R_F4_PLL2_STATUS 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define R_F5_PULSGEN_LINE_LENGTH 0xf5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG 0xf6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define R_F7_PULSE_A_POS_MSB 0xf7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define R_F8_PULSE_B_POS 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define R_F9_PULSE_B_POS_MSB 0xf9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define R_FA_PULSE_C_POS 0xfa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define R_FB_PULSE_C_POS_MSB 0xfb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* SAA7113 bit-masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SAA7113_R_08_HTC_OFFSET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SAA7113_R_08_HTC_MASK (0x3 << SAA7113_R_08_HTC_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SAA7113_R_08_FSEL 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SAA7113_R_08_AUFD 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SAA7113_R_10_VRLN_OFFSET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SAA7113_R_10_VRLN_MASK (0x1 << SAA7113_R_10_VRLN_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SAA7113_R_10_OFTS_OFFSET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SAA7113_R_10_OFTS_MASK (0x3 << SAA7113_R_10_OFTS_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SAA7113_R_12_RTS0_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SAA7113_R_12_RTS0_MASK (0xf << SAA7113_R_12_RTS0_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SAA7113_R_12_RTS1_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SAA7113_R_12_RTS1_MASK (0xf << SAA7113_R_12_RTS1_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SAA7113_R_13_ADLSB_OFFSET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SAA7113_R_13_ADLSB_MASK (0x1 << SAA7113_R_13_ADLSB_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* Those structs will be used in the future for debug purposes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct saa711x_reg_descr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct saa711x_reg_descr saa711x_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* REG COUNT NAME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {R_00_CHIP_VERSION,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "Chip version"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Video Decoder: R_01_INC_DELAY to R_1F_STATUS_BYTE_2_VD_DEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* Video Decoder - Frontend part: R_01_INC_DELAY to R_05_INPUT_CNTL_4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {R_01_INC_DELAY,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "Increment delay"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {R_02_INPUT_CNTL_1,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "Analog input control 1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {R_03_INPUT_CNTL_2,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "Analog input control 2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {R_04_INPUT_CNTL_3,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "Analog input control 3"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {R_05_INPUT_CNTL_4,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) "Analog input control 4"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* Video Decoder - Decoder part: R_06_H_SYNC_START to R_1F_STATUS_BYTE_2_VD_DEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {R_06_H_SYNC_START,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "Horizontal sync start"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {R_07_H_SYNC_STOP,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "Horizontal sync stop"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {R_08_SYNC_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "Sync control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {R_09_LUMA_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "Luminance control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {R_0A_LUMA_BRIGHT_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "Luminance brightness control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {R_0B_LUMA_CONTRAST_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "Luminance contrast control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {R_0C_CHROMA_SAT_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "Chrominance saturation control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {R_0D_CHROMA_HUE_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "Chrominance hue control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {R_0E_CHROMA_CNTL_1,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "Chrominance control 1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {R_0F_CHROMA_GAIN_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "Chrominance gain control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {R_10_CHROMA_CNTL_2,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "Chrominance control 2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {R_11_MODE_DELAY_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "Mode/delay control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {R_12_RT_SIGNAL_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "RT signal control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {R_13_RT_X_PORT_OUT_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "RT/X port output control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {R_14_ANAL_ADC_COMPAT_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "Analog/ADC/compatibility control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {R_15_VGATE_START_FID_CHG, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "VGATE start FID change"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {R_16_VGATE_STOP,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "VGATE stop"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {R_17_MISC_VGATE_CONF_AND_MSB, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "Miscellaneous VGATE configuration and MSBs"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {R_18_RAW_DATA_GAIN_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "Raw data gain control",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {R_19_RAW_DATA_OFF_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "Raw data offset control",},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {R_1A_COLOR_KILL_LVL_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "Color Killer Level Control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { R_1B_MISC_TVVCRDET, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "MISC /TVVCRDET"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { R_1C_ENHAN_COMB_CTRL1, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "Enhanced comb ctrl1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { R_1D_ENHAN_COMB_CTRL2, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "Enhanced comb ctrl1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {R_1E_STATUS_BYTE_1_VD_DEC,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "Status byte 1 video decoder"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {R_1F_STATUS_BYTE_2_VD_DEC,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "Status byte 2 video decoder"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* Component processing and interrupt masking part: 0x20h to R_2F_INTERRUPT_MASK_3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* 0x20 to 0x22 - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {R_23_INPUT_CNTL_5,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "Analog input control 5"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {R_24_INPUT_CNTL_6,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "Analog input control 6"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {R_25_INPUT_CNTL_7,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "Analog input control 7"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* 0x26 to 0x28 - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {R_29_COMP_DELAY,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "Component delay"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {R_2A_COMP_BRIGHT_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "Component brightness control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {R_2B_COMP_CONTRAST_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "Component contrast control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {R_2C_COMP_SAT_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "Component saturation control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {R_2D_INTERRUPT_MASK_1,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "Interrupt mask 1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {R_2E_INTERRUPT_MASK_2,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) "Interrupt mask 2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {R_2F_INTERRUPT_MASK_3,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "Interrupt mask 3"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Audio clock generator part: R_30_AUD_MAST_CLK_CYCLES_PER_FIELD to 0x3f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {R_30_AUD_MAST_CLK_CYCLES_PER_FIELD,3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "Audio master clock cycles per field"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* 0x33 - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {R_34_AUD_MAST_CLK_NOMINAL_INC,3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "Audio master clock nominal increment"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* 0x37 - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {R_38_CLK_RATIO_AMXCLK_TO_ASCLK,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "Clock ratio AMXCLK to ASCLK"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {R_39_CLK_RATIO_ASCLK_TO_ALRCLK,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "Clock ratio ASCLK to ALRCLK"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {R_3A_AUD_CLK_GEN_BASIC_SETUP,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "Audio clock generator basic setup"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* 0x3b-0x3f - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* General purpose VBI data slicer part: R_40_SLICER_CNTL_1 to 0x7f */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {R_40_SLICER_CNTL_1,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "Slicer control 1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {R_41_LCR,23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "R_41_LCR"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {R_58_PROGRAM_FRAMING_CODE,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "Programmable framing code"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {R_59_H_OFF_FOR_SLICER,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "Horizontal offset for slicer"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {R_5A_V_OFF_FOR_SLICER,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "Vertical offset for slicer"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "Field offset and MSBs for horizontal and vertical offset"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {R_5D_DID,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "Header and data identification (R_5D_DID)"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {R_5E_SDID,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "Sliced data identification (R_5E_SDID) code"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {R_60_SLICER_STATUS_BYTE_0,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) "Slicer status byte 0"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {R_61_SLICER_STATUS_BYTE_1,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "Slicer status byte 1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {R_62_SLICER_STATUS_BYTE_2,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "Slicer status byte 2"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* 0x63-0x7f - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* X port, I port and the scaler part: R_80_GLOBAL_CNTL_1 to R_EF_B_VERT_LUMA_PHASE_OFF_11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* Task independent global settings: R_80_GLOBAL_CNTL_1 to R_8F_STATUS_INFO_SCALER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {R_80_GLOBAL_CNTL_1,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "Global control 1"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "Vertical sync and Field ID source selection, retimed V and F signals"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* 0x82 - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {R_83_X_PORT_I_O_ENA_AND_OUT_CLK,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "X port I/O enable and output clock"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {R_84_I_PORT_SIGNAL_DEF,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) "I port signal definitions"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {R_85_I_PORT_SIGNAL_POLAR,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "I port signal polarities"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) "I port FIFO flag control and arbitration"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "I port I/O enable output clock and gated"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {R_88_POWER_SAVE_ADC_PORT_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) "Power save/ADC port control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* 089-0x8e - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {R_8F_STATUS_INFO_SCALER,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) "Status information scaler part"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Task A definition: R_90_A_TASK_HANDLING_CNTL to R_BF_A_VERT_LUMA_PHASE_OFF_11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Task A: Basic settings and acquisition window definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {R_90_A_TASK_HANDLING_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) "Task A: Task handling control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {R_91_A_X_PORT_FORMATS_AND_CONF,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) "Task A: X port formats and configuration"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) "Task A: X port input reference signal definition"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) "Task A: I port output formats and configuration"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {R_94_A_HORIZ_INPUT_WINDOW_START,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) "Task A: Horizontal input window start"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {R_96_A_HORIZ_INPUT_WINDOW_LENGTH,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "Task A: Horizontal input window length"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {R_98_A_VERT_INPUT_WINDOW_START,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) "Task A: Vertical input window start"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {R_9A_A_VERT_INPUT_WINDOW_LENGTH,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "Task A: Vertical input window length"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {R_9C_A_HORIZ_OUTPUT_WINDOW_LENGTH,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "Task A: Horizontal output window length"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {R_9E_A_VERT_OUTPUT_WINDOW_LENGTH,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) "Task A: Vertical output window length"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Task A: FIR filtering and prescaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {R_A0_A_HORIZ_PRESCALING,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) "Task A: Horizontal prescaling"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {R_A1_A_ACCUMULATION_LENGTH,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) "Task A: Accumulation length"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) "Task A: Prescaler DC gain and FIR prefilter"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* 0xa3 - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {R_A4_A_LUMA_BRIGHTNESS_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) "Task A: Luminance brightness control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {R_A5_A_LUMA_CONTRAST_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) "Task A: Luminance contrast control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {R_A6_A_CHROMA_SATURATION_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) "Task A: Chrominance saturation control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* 0xa7 - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Task A: Horizontal phase scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {R_A8_A_HORIZ_LUMA_SCALING_INC,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) "Task A: Horizontal luminance scaling increment"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {R_AA_A_HORIZ_LUMA_PHASE_OFF,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) "Task A: Horizontal luminance phase offset"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* 0xab - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {R_AC_A_HORIZ_CHROMA_SCALING_INC,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) "Task A: Horizontal chrominance scaling increment"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {R_AE_A_HORIZ_CHROMA_PHASE_OFF,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) "Task A: Horizontal chrominance phase offset"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* 0xaf - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Task A: Vertical scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {R_B0_A_VERT_LUMA_SCALING_INC,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) "Task A: Vertical luminance scaling increment"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {R_B2_A_VERT_CHROMA_SCALING_INC,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) "Task A: Vertical chrominance scaling increment"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {R_B4_A_VERT_SCALING_MODE_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) "Task A: Vertical scaling mode control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* 0xb5-0xb7 - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {R_B8_A_VERT_CHROMA_PHASE_OFF_00,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) "Task A: Vertical chrominance phase offset '00'"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {R_B9_A_VERT_CHROMA_PHASE_OFF_01,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) "Task A: Vertical chrominance phase offset '01'"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {R_BA_A_VERT_CHROMA_PHASE_OFF_10,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) "Task A: Vertical chrominance phase offset '10'"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {R_BB_A_VERT_CHROMA_PHASE_OFF_11,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) "Task A: Vertical chrominance phase offset '11'"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {R_BC_A_VERT_LUMA_PHASE_OFF_00,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) "Task A: Vertical luminance phase offset '00'"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {R_BD_A_VERT_LUMA_PHASE_OFF_01,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) "Task A: Vertical luminance phase offset '01'"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {R_BE_A_VERT_LUMA_PHASE_OFF_10,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) "Task A: Vertical luminance phase offset '10'"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {R_BF_A_VERT_LUMA_PHASE_OFF_11,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) "Task A: Vertical luminance phase offset '11'"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* Task B definition: R_C0_B_TASK_HANDLING_CNTL to R_EF_B_VERT_LUMA_PHASE_OFF_11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /* Task B: Basic settings and acquisition window definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {R_C0_B_TASK_HANDLING_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) "Task B: Task handling control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {R_C1_B_X_PORT_FORMATS_AND_CONF,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) "Task B: X port formats and configuration"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) "Task B: Input reference signal definition"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {R_C3_B_I_PORT_FORMATS_AND_CONF,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "Task B: I port formats and configuration"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {R_C4_B_HORIZ_INPUT_WINDOW_START,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "Task B: Horizontal input window start"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {R_C6_B_HORIZ_INPUT_WINDOW_LENGTH,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) "Task B: Horizontal input window length"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {R_C8_B_VERT_INPUT_WINDOW_START,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) "Task B: Vertical input window start"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {R_CA_B_VERT_INPUT_WINDOW_LENGTH,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) "Task B: Vertical input window length"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {R_CC_B_HORIZ_OUTPUT_WINDOW_LENGTH,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "Task B: Horizontal output window length"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {R_CE_B_VERT_OUTPUT_WINDOW_LENGTH,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) "Task B: Vertical output window length"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Task B: FIR filtering and prescaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {R_D0_B_HORIZ_PRESCALING,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) "Task B: Horizontal prescaling"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {R_D1_B_ACCUMULATION_LENGTH,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "Task B: Accumulation length"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) "Task B: Prescaler DC gain and FIR prefilter"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* 0xd3 - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {R_D4_B_LUMA_BRIGHTNESS_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) "Task B: Luminance brightness control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {R_D5_B_LUMA_CONTRAST_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) "Task B: Luminance contrast control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {R_D6_B_CHROMA_SATURATION_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) "Task B: Chrominance saturation control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* 0xd7 - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Task B: Horizontal phase scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {R_D8_B_HORIZ_LUMA_SCALING_INC,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) "Task B: Horizontal luminance scaling increment"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {R_DA_B_HORIZ_LUMA_PHASE_OFF,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) "Task B: Horizontal luminance phase offset"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* 0xdb - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {R_DC_B_HORIZ_CHROMA_SCALING,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) "Task B: Horizontal chrominance scaling"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) "Task B: Horizontal Phase Offset Chroma"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* 0xdf - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Task B: Vertical scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {R_E0_B_VERT_LUMA_SCALING_INC,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) "Task B: Vertical luminance scaling increment"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {R_E2_B_VERT_CHROMA_SCALING_INC,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) "Task B: Vertical chrominance scaling increment"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {R_E4_B_VERT_SCALING_MODE_CNTL,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) "Task B: Vertical scaling mode control"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* 0xe5-0xe7 - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {R_E8_B_VERT_CHROMA_PHASE_OFF_00,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) "Task B: Vertical chrominance phase offset '00'"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {R_E9_B_VERT_CHROMA_PHASE_OFF_01,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) "Task B: Vertical chrominance phase offset '01'"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {R_EA_B_VERT_CHROMA_PHASE_OFF_10,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) "Task B: Vertical chrominance phase offset '10'"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {R_EB_B_VERT_CHROMA_PHASE_OFF_11,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) "Task B: Vertical chrominance phase offset '11'"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {R_EC_B_VERT_LUMA_PHASE_OFF_00,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) "Task B: Vertical luminance phase offset '00'"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {R_ED_B_VERT_LUMA_PHASE_OFF_01,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) "Task B: Vertical luminance phase offset '01'"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {R_EE_B_VERT_LUMA_PHASE_OFF_10,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) "Task B: Vertical luminance phase offset '10'"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {R_EF_B_VERT_LUMA_PHASE_OFF_11,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) "Task B: Vertical luminance phase offset '11'"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* second PLL (PLL2) and Pulsegenerator Programming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { R_F0_LFCO_PER_LINE, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) "LFCO's per line"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { R_F1_P_I_PARAM_SELECT,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) "P-/I- Param. Select., PLL Mode, PLL H-Src., LFCO's per line"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) { R_F2_NOMINAL_PLL2_DTO,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) "Nominal PLL2 DTO"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {R_F3_PLL_INCREMENT,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) "PLL2 Increment"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) {R_F4_PLL2_STATUS,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) "PLL2 Status"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) {R_F5_PULSGEN_LINE_LENGTH,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) "Pulsgen. line length"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) {R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) "Pulse A Position, Pulsgen Resync., Pulsgen. H-Src., Pulsgen. line length"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {R_F7_PULSE_A_POS_MSB,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) "Pulse A Position"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {R_F8_PULSE_B_POS,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) "Pulse B Position"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {R_FA_PULSE_C_POS,2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) "Pulse C Position"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* 0xfc to 0xfe - Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES,1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) "S_PLL max. phase, error threshold, PLL2 no. of lines, threshold"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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