Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * saa7110 - Philips SAA7110(A) video decoder driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 1998 Pauline Middelink <middelin@polyware.nl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (C) 1999 Wolfgang Scherr <scherr@net4you.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 2000 Serguei Miridonov <mirsev@cicese.mx>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *    - some corrections for Pinnacle Systems Inc. DC10plus card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * Changes by Ronald Bultje <rbultje@ronald.bitfreak.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *    - moved over to linux>=2.4.x i2c protocol (1/1/2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <linux/wait.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) MODULE_DESCRIPTION("Philips SAA7110 video decoder driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) MODULE_AUTHOR("Pauline Middelink");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) module_param(debug, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) MODULE_PARM_DESC(debug, "Debug level (0-1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SAA7110_MAX_INPUT	9	/* 6 CVBS, 3 SVHS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SAA7110_MAX_OUTPUT	1	/* 1 YUV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SAA7110_NR_REG		0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) struct saa7110 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u8 reg[SAA7110_NR_REG];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	v4l2_std_id norm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	int input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	int enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	wait_queue_head_t wq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static inline struct saa7110 *to_saa7110(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	return container_of(sd, struct saa7110, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	return &container_of(ctrl->handler, struct saa7110, hdl)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* I2C support functions						   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static int saa7110_write(struct v4l2_subdev *sd, u8 reg, u8 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct saa7110 *decoder = to_saa7110(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	decoder->reg[reg] = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	return i2c_smbus_write_byte_data(client, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) static int saa7110_write_block(struct v4l2_subdev *sd, const u8 *data, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	struct saa7110 *decoder = to_saa7110(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	int ret = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u8 reg = *data;		/* first register to write to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/* Sanity check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	if (reg + (len - 1) > SAA7110_NR_REG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	/* the saa7110 has an autoincrement function, use it if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	 * the adapter understands raw I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	if (i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		ret = i2c_master_send(client, data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		/* Cache the written data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 		memcpy(decoder->reg + reg, data + 1, len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		for (++data, --len; len; len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 			ret = saa7110_write(sd, reg++, *data++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 			if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static inline int saa7110_read(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	return i2c_smbus_read_byte(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* SAA7110 functions							   */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define FRESP_06H_COMPST 0x03	/*0x13*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define FRESP_06H_SVIDEO 0x83	/*0xC0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static int saa7110_selmux(struct v4l2_subdev *sd, int chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	static const unsigned char modes[9][8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		/* mode 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 		{FRESP_06H_COMPST, 0xD9, 0x17, 0x40, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			      0x44, 0x75, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		/* mode 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		{FRESP_06H_COMPST, 0xD8, 0x17, 0x40, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			      0x44, 0x75, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 		/* mode 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 		{FRESP_06H_COMPST, 0xBA, 0x07, 0x91, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 			      0x60, 0xB5, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 		/* mode 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		{FRESP_06H_COMPST, 0xB8, 0x07, 0x91, 0x03,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 			      0x60, 0xB5, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 		/* mode 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 		{FRESP_06H_COMPST, 0x7C, 0x07, 0xD2, 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 			      0x60, 0xB5, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		/* mode 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		{FRESP_06H_COMPST, 0x78, 0x07, 0xD2, 0x83,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 			      0x60, 0xB5, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 		/* mode 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 		{FRESP_06H_SVIDEO, 0x59, 0x17, 0x42, 0xA3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 			      0x44, 0x75, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		/* mode 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		{FRESP_06H_SVIDEO, 0x9A, 0x17, 0xB1, 0x13,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 			      0x60, 0xB5, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 		/* mode 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		{FRESP_06H_SVIDEO, 0x3C, 0x27, 0xC1, 0x23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			      0x44, 0x75, 0x21}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct saa7110 *decoder = to_saa7110(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	const unsigned char *ptr = modes[chan];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	saa7110_write(sd, 0x06, ptr[0]);	/* Luminance control    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	saa7110_write(sd, 0x20, ptr[1]);	/* Analog Control #1    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	saa7110_write(sd, 0x21, ptr[2]);	/* Analog Control #2    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	saa7110_write(sd, 0x22, ptr[3]);	/* Mixer Control #1     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	saa7110_write(sd, 0x2C, ptr[4]);	/* Mixer Control #2     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	saa7110_write(sd, 0x30, ptr[5]);	/* ADCs gain control    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	saa7110_write(sd, 0x31, ptr[6]);	/* Mixer Control #3     */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	saa7110_write(sd, 0x21, ptr[7]);	/* Analog Control #2    */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	decoder->input = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static const unsigned char initseq[1 + SAA7110_NR_REG] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 	0, 0x4C, 0x3C, 0x0D, 0xEF, 0xBD, 0xF2, 0x03, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	/* 0x08 */ 0xF8, 0xF8, 0x60, 0x60, 0x00, 0x86, 0x18, 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	/* 0x10 */ 0x00, 0x59, 0x40, 0x46, 0x42, 0x1A, 0xFF, 0xDA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	/* 0x18 */ 0xF2, 0x8B, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	/* 0x20 */ 0xD9, 0x16, 0x40, 0x41, 0x80, 0x41, 0x80, 0x4F,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	/* 0x28 */ 0xFE, 0x01, 0xCF, 0x0F, 0x03, 0x01, 0x03, 0x0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	/* 0x30 */ 0x44, 0x71, 0x02, 0x8C, 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static v4l2_std_id determine_norm(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	DEFINE_WAIT(wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	struct saa7110 *decoder = to_saa7110(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	/* mode changed, start automatic detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	saa7110_write_block(sd, initseq, sizeof(initseq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	saa7110_selmux(sd, decoder->input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	prepare_to_wait(&decoder->wq, &wait, TASK_UNINTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	schedule_timeout(msecs_to_jiffies(250));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	finish_wait(&decoder->wq, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	status = saa7110_read(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (status & 0x40) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		v4l2_dbg(1, debug, sd, "status=0x%02x (no signal)\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 		return V4L2_STD_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	if ((status & 3) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 		saa7110_write(sd, 0x06, 0x83);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 		if (status & 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 			v4l2_dbg(1, debug, sd, "status=0x%02x (NTSC/no color)\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 			/*saa7110_write(sd,0x2E,0x81);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 			return V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		v4l2_dbg(1, debug, sd, "status=0x%02x (PAL/no color)\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		/*saa7110_write(sd,0x2E,0x9A);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		return V4L2_STD_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	/*saa7110_write(sd,0x06,0x03);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (status & 0x20) {	/* 60Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		v4l2_dbg(1, debug, sd, "status=0x%02x (NTSC)\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 		saa7110_write(sd, 0x0D, 0x86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 		saa7110_write(sd, 0x0F, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		saa7110_write(sd, 0x11, 0x2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 		/*saa7110_write(sd,0x2E,0x81);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		return V4L2_STD_NTSC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	/* 50Hz -> PAL/SECAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	saa7110_write(sd, 0x0D, 0x86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	saa7110_write(sd, 0x0F, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	saa7110_write(sd, 0x11, 0x59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	/*saa7110_write(sd,0x2E,0x9A);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	prepare_to_wait(&decoder->wq, &wait, TASK_UNINTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	schedule_timeout(msecs_to_jiffies(250));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	finish_wait(&decoder->wq, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	status = saa7110_read(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	if ((status & 0x03) == 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		v4l2_dbg(1, debug, sd, "status=0x%02x (SECAM)\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		saa7110_write(sd, 0x0D, 0x87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		return V4L2_STD_SECAM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	v4l2_dbg(1, debug, sd, "status=0x%02x (PAL)\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	return V4L2_STD_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static int saa7110_g_input_status(struct v4l2_subdev *sd, u32 *pstatus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	struct saa7110 *decoder = to_saa7110(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	int res = V4L2_IN_ST_NO_SIGNAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	int status = saa7110_read(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	v4l2_dbg(1, debug, sd, "status=0x%02x norm=%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 		       status, (unsigned long long)decoder->norm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (!(status & 0x40))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		res = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	if (!(status & 0x03))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 		res |= V4L2_IN_ST_NO_COLOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	*pstatus = res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int saa7110_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	*std &= determine_norm(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int saa7110_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	struct saa7110 *decoder = to_saa7110(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	if (decoder->norm != std) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		decoder->norm = std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		/*saa7110_write(sd, 0x06, 0x03);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		if (std & V4L2_STD_NTSC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 			saa7110_write(sd, 0x0D, 0x86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 			saa7110_write(sd, 0x0F, 0x50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 			saa7110_write(sd, 0x11, 0x2C);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 			/*saa7110_write(sd, 0x2E, 0x81);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 			v4l2_dbg(1, debug, sd, "switched to NTSC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		} else if (std & V4L2_STD_PAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			saa7110_write(sd, 0x0D, 0x86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 			saa7110_write(sd, 0x0F, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			saa7110_write(sd, 0x11, 0x59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 			/*saa7110_write(sd, 0x2E, 0x9A);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 			v4l2_dbg(1, debug, sd, "switched to PAL\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		} else if (std & V4L2_STD_SECAM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 			saa7110_write(sd, 0x0D, 0x87);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 			saa7110_write(sd, 0x0F, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 			saa7110_write(sd, 0x11, 0x59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 			/*saa7110_write(sd, 0x2E, 0x9A);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 			v4l2_dbg(1, debug, sd, "switched to SECAM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static int saa7110_s_routing(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 			     u32 input, u32 output, u32 config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	struct saa7110 *decoder = to_saa7110(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	if (input >= SAA7110_MAX_INPUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 		v4l2_dbg(1, debug, sd, "input=%d not available\n", input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	if (decoder->input != input) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 		saa7110_selmux(sd, input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		v4l2_dbg(1, debug, sd, "switched to input=%d\n", input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static int saa7110_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct saa7110 *decoder = to_saa7110(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (decoder->enable != enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		decoder->enable = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		saa7110_write(sd, 0x0E, enable ? 0x18 : 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		v4l2_dbg(1, debug, sd, "YUV %s\n", enable ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) static int saa7110_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		saa7110_write(sd, 0x19, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 		saa7110_write(sd, 0x13, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		saa7110_write(sd, 0x12, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	case V4L2_CID_HUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		saa7110_write(sd, 0x07, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) static const struct v4l2_ctrl_ops saa7110_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	.s_ctrl = saa7110_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const struct v4l2_subdev_video_ops saa7110_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	.s_std = saa7110_s_std,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	.s_routing = saa7110_s_routing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	.s_stream = saa7110_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	.querystd = saa7110_querystd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	.g_input_status = saa7110_g_input_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const struct v4l2_subdev_ops saa7110_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 	.video = &saa7110_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int saa7110_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	struct saa7110 *decoder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	int rv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	/* Check if the adapter supports the needed features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 	if (!i2c_check_functionality(client->adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		I2C_FUNC_SMBUS_READ_BYTE | I2C_FUNC_SMBUS_WRITE_BYTE_DATA))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 		return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	v4l_info(client, "chip found @ 0x%x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 			client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	decoder = devm_kzalloc(&client->dev, sizeof(*decoder), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	if (!decoder)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	sd = &decoder->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	v4l2_i2c_subdev_init(sd, client, &saa7110_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	decoder->norm = V4L2_STD_PAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	decoder->input = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 	decoder->enable = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	v4l2_ctrl_handler_init(&decoder->hdl, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	v4l2_ctrl_new_std(&decoder->hdl, &saa7110_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 		V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	v4l2_ctrl_new_std(&decoder->hdl, &saa7110_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		V4L2_CID_CONTRAST, 0, 127, 1, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	v4l2_ctrl_new_std(&decoder->hdl, &saa7110_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 		V4L2_CID_SATURATION, 0, 127, 1, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	v4l2_ctrl_new_std(&decoder->hdl, &saa7110_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		V4L2_CID_HUE, -128, 127, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	sd->ctrl_handler = &decoder->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	if (decoder->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		int err = decoder->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		v4l2_ctrl_handler_free(&decoder->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	v4l2_ctrl_handler_setup(&decoder->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	init_waitqueue_head(&decoder->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 	rv = saa7110_write_block(sd, initseq, sizeof(initseq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	if (rv < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		v4l2_dbg(1, debug, sd, "init status %d\n", rv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 		int ver, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 		saa7110_write(sd, 0x21, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		saa7110_write(sd, 0x0e, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		saa7110_write(sd, 0x0D, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		ver = saa7110_read(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		saa7110_write(sd, 0x0D, 0x06);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		/*mdelay(150);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		status = saa7110_read(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 		v4l2_dbg(1, debug, sd, "version %x, status=0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 			       ver, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		saa7110_write(sd, 0x0D, 0x86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		saa7110_write(sd, 0x0F, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		saa7110_write(sd, 0x11, 0x59);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 		/*saa7110_write(sd, 0x2E, 0x9A);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	/*saa7110_selmux(sd,0);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	/*determine_norm(sd);*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	/* setup and implicit mode 0 select has been performed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static int saa7110_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	struct saa7110 *decoder = to_saa7110(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 	v4l2_ctrl_handler_free(&decoder->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static const struct i2c_device_id saa7110_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	{ "saa7110", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	{ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MODULE_DEVICE_TABLE(i2c, saa7110_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static struct i2c_driver saa7110_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 		.name	= "saa7110",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	.probe		= saa7110_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	.remove		= saa7110_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	.id_table	= saa7110_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) module_i2c_driver(saa7110_driver);