^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for Samsung S5K4ECGX 1/4" 5Mp CMOS Image Sensor SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * with an Embedded Image Signal Processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2012, Linaro, Sangwook Lee <sangwook.lee@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2012, Insignal Co,. Ltd, Homin Lee <suapapa@insignal.co.kr>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based on s5k6aa and noon010pc30 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Copyright (C) 2011, Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/i2c/s5k4ecgx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) module_param(debug, int, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define S5K4ECGX_DRIVER_NAME "s5k4ecgx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define S5K4ECGX_FIRMWARE "s5k4ecgx.bin"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Firmware revision information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define REG_FW_REVISION 0x700001a6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_FW_VERSION 0x700001a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S5K4ECGX_REVISION_1_1 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S5K4ECGX_FW_VERSION 0x4ec0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* General purpose parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_USER_BRIGHTNESS 0x7000022c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_USER_CONTRAST 0x7000022e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_USER_SATURATION 0x70000230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_G_ENABLE_PREV 0x7000023e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REG_G_ENABLE_PREV_CHG 0x70000240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_G_NEW_CFG_SYNC 0x7000024a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_G_PREV_IN_WIDTH 0x70000250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_G_PREV_IN_HEIGHT 0x70000252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_G_PREV_IN_XOFFS 0x70000254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define REG_G_PREV_IN_YOFFS 0x70000256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define REG_G_CAP_IN_WIDTH 0x70000258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define REG_G_CAP_IN_HEIGHT 0x7000025a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REG_G_CAP_IN_XOFFS 0x7000025c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_G_CAP_IN_YOFFS 0x7000025e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define REG_G_INPUTS_CHANGE_REQ 0x70000262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define REG_G_ACTIVE_PREV_CFG 0x70000266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define REG_G_PREV_CFG_CHG 0x70000268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_G_PREV_OPEN_AFTER_CH 0x7000026a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Preview context register sets. n = 0...4. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PREG(n, x) ((n) * 0x30 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define REG_P_OUT_WIDTH(n) PREG(n, 0x700002a6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define REG_P_OUT_HEIGHT(n) PREG(n, 0x700002a8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define REG_P_FMT(n) PREG(n, 0x700002aa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define REG_P_PVI_MASK(n) PREG(n, 0x700002b4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define REG_P_FR_TIME_TYPE(n) PREG(n, 0x700002be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define FR_TIME_DYNAMIC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define FR_TIME_FIXED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define FR_TIME_FIXED_ACCURATE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REG_P_FR_TIME_Q_TYPE(n) PREG(n, 0x700002c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define FR_TIME_Q_DYNAMIC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FR_TIME_Q_BEST_FRRATE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FR_TIME_Q_BEST_QUALITY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* Frame period in 0.1 ms units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define REG_P_MAX_FR_TIME(n) PREG(n, 0x700002c2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define REG_P_MIN_FR_TIME(n) PREG(n, 0x700002c4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define US_TO_FR_TIME(__t) ((__t) / 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define REG_P_PREV_MIRROR(n) PREG(n, 0x700002d0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define REG_P_CAP_MIRROR(n) PREG(n, 0x700002d2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define REG_G_PREVZOOM_IN_WIDTH 0x70000494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define REG_G_PREVZOOM_IN_HEIGHT 0x70000496
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define REG_G_PREVZOOM_IN_XOFFS 0x70000498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define REG_G_PREVZOOM_IN_YOFFS 0x7000049a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define REG_G_CAPZOOM_IN_WIDTH 0x7000049c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define REG_G_CAPZOOM_IN_HEIGHT 0x7000049e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define REG_G_CAPZOOM_IN_XOFFS 0x700004a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define REG_G_CAPZOOM_IN_YOFFS 0x700004a2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* n = 0...4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define REG_USER_SHARPNESS(n) (0x70000a28 + (n) * 0xb6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Reduce sharpness range for user space API */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SHARPNESS_DIV 8208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TOK_TERM 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * FIXME: This is copied from s5k6aa, because of no information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * in the S5K4ECGX datasheet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * H/W register Interface (0xd0000000 - 0xd0000fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define AHB_MSB_ADDR_PTR 0xfcfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GEN_REG_OFFSH 0xd000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define REG_CMDWR_ADDRH 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define REG_CMDWR_ADDRL 0x002a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define REG_CMDRD_ADDRH 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define REG_CMDRD_ADDRL 0x002e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define REG_CMDBUF0_ADDR 0x0f12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct s5k4ecgx_frmsize {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct v4l2_frmsize_discrete size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Fixed sensor matrix crop rectangle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct v4l2_rect input_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct regval_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * TODO: currently only preview is supported and snapshot (capture)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * is not implemented yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static const struct s5k4ecgx_frmsize s5k4ecgx_prev_sizes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) .size = { 176, 144 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) .input_window = { 0x00, 0x00, 0x928, 0x780 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) .size = { 352, 288 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) .input_window = { 0x00, 0x00, 0x928, 0x780 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .size = { 640, 480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .input_window = { 0x00, 0x00, 0xa00, 0x780 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) .size = { 720, 480 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) .input_window = { 0x00, 0x00, 0xa00, 0x6a8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define S5K4ECGX_NUM_PREV ARRAY_SIZE(s5k4ecgx_prev_sizes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct s5k4ecgx_pixfmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* REG_TC_PCFG_Format register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u16 reg_p_format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* By default value, output from sensor will be YUV422 0-255 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static const struct s5k4ecgx_pixfmt s5k4ecgx_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG, 5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const char * const s5k4ecgx_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Usually 2.8V is used for analog power (vdda)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * and digital IO (vddio, vdddcore)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "vdda",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "vddio",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "vddcore",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "vddreg", /* The internal s5k4ecgx regulator's supply (1.8V) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define S5K4ECGX_NUM_SUPPLIES ARRAY_SIZE(s5k4ecgx_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) enum s5k4ecgx_gpio_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) STBY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) RSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) GPIO_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct s5k4ecgx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct v4l2_ctrl_handler handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct s5k4ecgx_platform_data *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) const struct s5k4ecgx_pixfmt *curr_pixfmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) const struct s5k4ecgx_frmsize *curr_frmsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u8 streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u8 set_params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct regulator_bulk_data supplies[S5K4ECGX_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct s5k4ecgx_gpio gpio[GPIO_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static inline struct s5k4ecgx *to_s5k4ecgx(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return container_of(sd, struct s5k4ecgx, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static int s5k4ecgx_i2c_read(struct i2c_client *client, u16 addr, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 wbuf[2] = { addr >> 8, addr & 0xff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u8 rbuf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) msg[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) msg[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) msg[0].buf = wbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) msg[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) msg[1].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) msg[1].buf = rbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) *val = be16_to_cpu(*((__be16 *)rbuf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) v4l2_dbg(4, debug, client, "i2c_read: 0x%04X : 0x%04x\n", addr, *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return ret == 2 ? 0 : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static int s5k4ecgx_i2c_write(struct i2c_client *client, u16 addr, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u8 buf[4] = { addr >> 8, addr & 0xff, val >> 8, val & 0xff };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int ret = i2c_master_send(client, buf, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) v4l2_dbg(4, debug, client, "i2c_write: 0x%04x : 0x%04x\n", addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return ret == 4 ? 0 : ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static int s5k4ecgx_write(struct i2c_client *client, u32 addr, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u16 high = addr >> 16, low = addr & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) v4l2_dbg(3, debug, client, "write: 0x%08x : 0x%04x\n", addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ret = s5k4ecgx_i2c_write(client, REG_CMDWR_ADDRH, high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ret = s5k4ecgx_i2c_write(client, REG_CMDWR_ADDRL, low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ret = s5k4ecgx_i2c_write(client, REG_CMDBUF0_ADDR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int s5k4ecgx_read(struct i2c_client *client, u32 addr, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u16 high = addr >> 16, low = addr & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = s5k4ecgx_i2c_write(client, REG_CMDRD_ADDRH, high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) ret = s5k4ecgx_i2c_write(client, REG_CMDRD_ADDRL, low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) ret = s5k4ecgx_i2c_read(client, REG_CMDBUF0_ADDR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int s5k4ecgx_read_fw_ver(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u16 hw_rev, fw_ver = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ret = s5k4ecgx_read(client, REG_FW_VERSION, &fw_ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (ret < 0 || fw_ver != S5K4ECGX_FW_VERSION) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) v4l2_err(sd, "FW version check failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ret = s5k4ecgx_read(client, REG_FW_REVISION, &hw_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) v4l2_info(sd, "chip found FW ver: 0x%x, HW rev: 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) fw_ver, hw_rev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) static int s5k4ecgx_set_ahb_address(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Set APB peripherals start address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ret = s5k4ecgx_i2c_write(client, AHB_MSB_ADDR_PTR, GEN_REG_OFFSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * FIXME: This is copied from s5k6aa, because of no information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * in s5k4ecgx's datasheet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * sw_reset is activated to put device into idle status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) ret = s5k4ecgx_i2c_write(client, 0x0010, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ret = s5k4ecgx_i2c_write(client, 0x1030, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Halt ARM CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return s5k4ecgx_i2c_write(client, 0x0014, 0x0001);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define FW_CRC_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Register address, value are 4, 2 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define FW_RECORD_SIZE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * The firmware has following format:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * < total number of records (4 bytes + 2 bytes padding) N >,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * < record 0 >, ..., < record N - 1 >, < CRC32-CCITT (4-bytes) >,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * where "record" is a 4-byte register address followed by 2-byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * register value (little endian).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * The firmware generator can be found in following git repository:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * git://git.linaro.org/people/sangwook/fimc-v4l2-app.git
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static int s5k4ecgx_load_firmware(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) const struct firmware *fw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) const u8 *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) int err, i, regs_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 addr, crc, crc_file, addr_inc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) err = request_firmware(&fw, S5K4ECGX_FIRMWARE, sd->v4l2_dev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) v4l2_err(sd, "Failed to read firmware %s\n", S5K4ECGX_FIRMWARE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) regs_num = get_unaligned_le32(fw->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) v4l2_dbg(3, debug, sd, "FW: %s size %zu register sets %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) S5K4ECGX_FIRMWARE, fw->size, regs_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) regs_num++; /* Add header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (fw->size != regs_num * FW_RECORD_SIZE + FW_CRC_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) goto fw_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) crc_file = get_unaligned_le32(fw->data + regs_num * FW_RECORD_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) crc = crc32_le(~0, fw->data, regs_num * FW_RECORD_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) if (crc != crc_file) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) v4l2_err(sd, "FW: invalid crc (%#x:%#x)\n", crc, crc_file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) goto fw_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ptr = fw->data + FW_RECORD_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) for (i = 1; i < regs_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) addr = get_unaligned_le32(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ptr += sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) val = get_unaligned_le16(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) ptr += sizeof(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if (addr - addr_inc != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) err = s5k4ecgx_write(client, addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) err = s5k4ecgx_i2c_write(client, REG_CMDBUF0_ADDR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) addr_inc = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) fw_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Set preview and capture input window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static int s5k4ecgx_set_input_window(struct i2c_client *c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) const struct v4l2_rect *r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = s5k4ecgx_write(c, REG_G_PREV_IN_WIDTH, r->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ret = s5k4ecgx_write(c, REG_G_PREV_IN_HEIGHT, r->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ret = s5k4ecgx_write(c, REG_G_PREV_IN_XOFFS, r->left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = s5k4ecgx_write(c, REG_G_PREV_IN_YOFFS, r->top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ret = s5k4ecgx_write(c, REG_G_CAP_IN_WIDTH, r->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ret = s5k4ecgx_write(c, REG_G_CAP_IN_HEIGHT, r->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ret = s5k4ecgx_write(c, REG_G_CAP_IN_XOFFS, r->left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ret = s5k4ecgx_write(c, REG_G_CAP_IN_YOFFS, r->top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Set preview and capture zoom input window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static int s5k4ecgx_set_zoom_window(struct i2c_client *c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) const struct v4l2_rect *r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret = s5k4ecgx_write(c, REG_G_PREVZOOM_IN_WIDTH, r->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = s5k4ecgx_write(c, REG_G_PREVZOOM_IN_HEIGHT, r->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ret = s5k4ecgx_write(c, REG_G_PREVZOOM_IN_XOFFS, r->left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ret = s5k4ecgx_write(c, REG_G_PREVZOOM_IN_YOFFS, r->top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) ret = s5k4ecgx_write(c, REG_G_CAPZOOM_IN_WIDTH, r->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = s5k4ecgx_write(c, REG_G_CAPZOOM_IN_HEIGHT, r->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ret = s5k4ecgx_write(c, REG_G_CAPZOOM_IN_XOFFS, r->left);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ret = s5k4ecgx_write(c, REG_G_CAPZOOM_IN_YOFFS, r->top);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int s5k4ecgx_set_output_framefmt(struct s5k4ecgx *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) ret = s5k4ecgx_write(client, REG_P_OUT_WIDTH(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) priv->curr_frmsize->size.width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ret = s5k4ecgx_write(client, REG_P_OUT_HEIGHT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) priv->curr_frmsize->size.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ret = s5k4ecgx_write(client, REG_P_FMT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) priv->curr_pixfmt->reg_p_format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int s5k4ecgx_init_sensor(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) ret = s5k4ecgx_set_ahb_address(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* The delay is from manufacturer's settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ret = s5k4ecgx_load_firmware(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) v4l2_err(sd, "Failed to write initial settings\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static int s5k4ecgx_gpio_set_value(struct s5k4ecgx *priv, int id, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!gpio_is_valid(priv->gpio[id].gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) gpio_set_value(priv->gpio[id].gpio, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int __s5k4ecgx_power_on(struct s5k4ecgx *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ret = regulator_bulk_enable(S5K4ECGX_NUM_SUPPLIES, priv->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) usleep_range(30, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /* The polarity of STBY is controlled by TSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (s5k4ecgx_gpio_set_value(priv, STBY, priv->gpio[STBY].level))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) usleep_range(30, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (s5k4ecgx_gpio_set_value(priv, RSET, priv->gpio[RSET].level))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) usleep_range(30, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static int __s5k4ecgx_power_off(struct s5k4ecgx *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (s5k4ecgx_gpio_set_value(priv, RSET, !priv->gpio[RSET].level))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) usleep_range(30, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if (s5k4ecgx_gpio_set_value(priv, STBY, !priv->gpio[STBY].level))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) usleep_range(30, 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) priv->streaming = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) return regulator_bulk_disable(S5K4ECGX_NUM_SUPPLIES, priv->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* Find nearest matching image pixel size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) static int s5k4ecgx_try_frame_size(struct v4l2_mbus_framefmt *mf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) const struct s5k4ecgx_frmsize **size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned int min_err = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int i = ARRAY_SIZE(s5k4ecgx_prev_sizes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) const struct s5k4ecgx_frmsize *fsize = &s5k4ecgx_prev_sizes[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) *match = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) while (i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int err = abs(fsize->size.width - mf->width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) + abs(fsize->size.height - mf->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) if (err < min_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) min_err = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) match = fsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) fsize++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (match) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) mf->width = match->size.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) mf->height = match->size.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) *size = match;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int s5k4ecgx_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (code->index >= ARRAY_SIZE(s5k4ecgx_formats))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) code->code = s5k4ecgx_formats[code->index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int s5k4ecgx_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct s5k4ecgx *priv = to_s5k4ecgx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct v4l2_mbus_framefmt *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) mf = v4l2_subdev_get_try_format(sd, cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) fmt->format = *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) mf = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) mf->width = priv->curr_frmsize->size.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) mf->height = priv->curr_frmsize->size.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mf->code = priv->curr_pixfmt->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mf->colorspace = priv->curr_pixfmt->colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static const struct s5k4ecgx_pixfmt *s5k4ecgx_try_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct v4l2_mbus_framefmt *mf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) int i = ARRAY_SIZE(s5k4ecgx_formats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) while (--i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (mf->code == s5k4ecgx_formats[i].code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) mf->code = s5k4ecgx_formats[i].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return &s5k4ecgx_formats[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int s5k4ecgx_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct s5k4ecgx *priv = to_s5k4ecgx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) const struct s5k4ecgx_frmsize *fsize = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) const struct s5k4ecgx_pixfmt *pf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct v4l2_mbus_framefmt *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) pf = s5k4ecgx_try_fmt(sd, &fmt->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) s5k4ecgx_try_frame_size(&fmt->format, &fsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) fmt->format.colorspace = V4L2_COLORSPACE_JPEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) mf = v4l2_subdev_get_try_format(sd, cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) *mf = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (!priv->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) priv->curr_frmsize = fsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) priv->curr_pixfmt = pf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) priv->set_params = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static const struct v4l2_subdev_pad_ops s5k4ecgx_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) .enum_mbus_code = s5k4ecgx_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) .get_fmt = s5k4ecgx_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) .set_fmt = s5k4ecgx_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * V4L2 subdev controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int s5k4ecgx_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct v4l2_subdev *sd = &container_of(ctrl->handler, struct s5k4ecgx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) handler)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct s5k4ecgx *priv = to_s5k4ecgx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) v4l2_dbg(1, debug, sd, "ctrl: 0x%x, value: %d\n", ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) err = s5k4ecgx_write(client, REG_USER_CONTRAST, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) err = s5k4ecgx_write(client, REG_USER_SATURATION, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) case V4L2_CID_SHARPNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /* TODO: Revisit, is this setting for all presets ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) for (i = 0; i < 4 && !err; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) err = s5k4ecgx_write(client, REG_USER_SHARPNESS(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ctrl->val * SHARPNESS_DIV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) err = s5k4ecgx_write(client, REG_USER_BRIGHTNESS, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) v4l2_err(sd, "Failed to write s_ctrl err %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static const struct v4l2_ctrl_ops s5k4ecgx_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .s_ctrl = s5k4ecgx_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * Reading s5k4ecgx version information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static int s5k4ecgx_registered(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct s5k4ecgx *priv = to_s5k4ecgx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ret = __s5k4ecgx_power_on(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ret = s5k4ecgx_read_fw_ver(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) __s5k4ecgx_power_off(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) * V4L2 subdev internal operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int s5k4ecgx_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct v4l2_mbus_framefmt *mf = v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) mf->width = s5k4ecgx_prev_sizes[0].size.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) mf->height = s5k4ecgx_prev_sizes[0].size.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) mf->code = s5k4ecgx_formats[0].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) mf->colorspace = V4L2_COLORSPACE_JPEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static const struct v4l2_subdev_internal_ops s5k4ecgx_subdev_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) .registered = s5k4ecgx_registered,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .open = s5k4ecgx_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int s5k4ecgx_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct s5k4ecgx *priv = to_s5k4ecgx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) v4l2_dbg(1, debug, sd, "Switching %s\n", on ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ret = __s5k4ecgx_power_on(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* Time to stabilize sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret = s5k4ecgx_init_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) __s5k4ecgx_power_off(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) priv->set_params = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret = __s5k4ecgx_power_off(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static int s5k4ecgx_log_status(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) v4l2_ctrl_handler_log_status(sd->ctrl_handler, sd->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static const struct v4l2_subdev_core_ops s5k4ecgx_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .s_power = s5k4ecgx_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .log_status = s5k4ecgx_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) static int __s5k4ecgx_s_params(struct s5k4ecgx *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) const struct v4l2_rect *crop_rect = &priv->curr_frmsize->input_window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ret = s5k4ecgx_set_input_window(client, crop_rect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ret = s5k4ecgx_set_zoom_window(client, crop_rect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ret = s5k4ecgx_write(client, REG_G_INPUTS_CHANGE_REQ, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ret = s5k4ecgx_write(client, 0x70000a1e, 0x28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ret = s5k4ecgx_write(client, 0x70000ad4, 0x3c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) ret = s5k4ecgx_set_output_framefmt(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ret = s5k4ecgx_write(client, REG_P_PVI_MASK(0), 0x52);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) ret = s5k4ecgx_write(client, REG_P_FR_TIME_TYPE(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) FR_TIME_DYNAMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) ret = s5k4ecgx_write(client, REG_P_FR_TIME_Q_TYPE(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) FR_TIME_Q_BEST_FRRATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) ret = s5k4ecgx_write(client, REG_P_MIN_FR_TIME(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) US_TO_FR_TIME(33300));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ret = s5k4ecgx_write(client, REG_P_MAX_FR_TIME(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) US_TO_FR_TIME(66600));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ret = s5k4ecgx_write(client, REG_P_PREV_MIRROR(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ret = s5k4ecgx_write(client, REG_P_CAP_MIRROR(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ret = s5k4ecgx_write(client, REG_G_ACTIVE_PREV_CFG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ret = s5k4ecgx_write(client, REG_G_PREV_OPEN_AFTER_CH, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ret = s5k4ecgx_write(client, REG_G_NEW_CFG_SYNC, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ret = s5k4ecgx_write(client, REG_G_PREV_CFG_CHG, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static int __s5k4ecgx_s_stream(struct s5k4ecgx *priv, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct i2c_client *client = v4l2_get_subdevdata(&priv->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (on && priv->set_params) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ret = __s5k4ecgx_s_params(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) priv->set_params = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * This enables/disables preview stream only. Capture requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) * are not supported yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ret = s5k4ecgx_write(client, REG_G_ENABLE_PREV, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return s5k4ecgx_write(client, REG_G_ENABLE_PREV_CHG, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static int s5k4ecgx_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct s5k4ecgx *priv = to_s5k4ecgx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) v4l2_dbg(1, debug, sd, "Turn streaming %s\n", on ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (priv->streaming == !on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = __s5k4ecgx_s_stream(priv, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) priv->streaming = on & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static const struct v4l2_subdev_video_ops s5k4ecgx_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .s_stream = s5k4ecgx_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) static const struct v4l2_subdev_ops s5k4ecgx_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .core = &s5k4ecgx_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .pad = &s5k4ecgx_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .video = &s5k4ecgx_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * GPIO setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int s5k4ecgx_config_gpio(int nr, int val, const char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) unsigned long flags = val ? GPIOF_OUT_INIT_HIGH : GPIOF_OUT_INIT_LOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (!gpio_is_valid(nr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ret = gpio_request_one(nr, flags, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) gpio_export(nr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static void s5k4ecgx_free_gpios(struct s5k4ecgx *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) for (i = 0; i < ARRAY_SIZE(priv->gpio); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (!gpio_is_valid(priv->gpio[i].gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) gpio_free(priv->gpio[i].gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) priv->gpio[i].gpio = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static int s5k4ecgx_config_gpios(struct s5k4ecgx *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) const struct s5k4ecgx_platform_data *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) const struct s5k4ecgx_gpio *gpio = &pdata->gpio_stby;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) priv->gpio[STBY].gpio = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) priv->gpio[RSET].gpio = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ret = s5k4ecgx_config_gpio(gpio->gpio, gpio->level, "S5K4ECGX_STBY");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) s5k4ecgx_free_gpios(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) priv->gpio[STBY] = *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (gpio_is_valid(gpio->gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) gpio_set_value(gpio->gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) gpio = &pdata->gpio_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ret = s5k4ecgx_config_gpio(gpio->gpio, gpio->level, "S5K4ECGX_RST");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) s5k4ecgx_free_gpios(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) priv->gpio[RSET] = *gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (gpio_is_valid(gpio->gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) gpio_set_value(gpio->gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) static int s5k4ecgx_init_v4l2_ctrls(struct s5k4ecgx *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) const struct v4l2_ctrl_ops *ops = &s5k4ecgx_ctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct v4l2_ctrl_handler *hdl = &priv->handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ret = v4l2_ctrl_handler_init(hdl, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BRIGHTNESS, -208, 127, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST, -127, 127, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION, -127, 127, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* Sharpness default is 24612, and then (24612/SHARPNESS_DIV) = 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SHARPNESS, -32704/SHARPNESS_DIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) 24612/SHARPNESS_DIV, 1, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (hdl->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ret = hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) v4l2_ctrl_handler_free(hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) priv->sd.ctrl_handler = hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static int s5k4ecgx_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct s5k4ecgx_platform_data *pdata = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) struct s5k4ecgx *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (pdata == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) dev_err(&client->dev, "platform data is missing!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) priv = devm_kzalloc(&client->dev, sizeof(struct s5k4ecgx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) mutex_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) priv->streaming = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) sd = &priv->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* Registering subdev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) v4l2_i2c_subdev_init(sd, client, &s5k4ecgx_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* Static name; NEVER use in new drivers! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) strscpy(sd->name, S5K4ECGX_DRIVER_NAME, sizeof(sd->name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) sd->internal_ops = &s5k4ecgx_subdev_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) /* Support v4l2 sub-device user space API */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) priv->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ret = media_entity_pads_init(&sd->entity, 1, &priv->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ret = s5k4ecgx_config_gpios(priv, pdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) dev_err(&client->dev, "Failed to set gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) goto out_err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) for (i = 0; i < S5K4ECGX_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) priv->supplies[i].supply = s5k4ecgx_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) ret = devm_regulator_bulk_get(&client->dev, S5K4ECGX_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) priv->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) dev_err(&client->dev, "Failed to get regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) goto out_err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ret = s5k4ecgx_init_v4l2_ctrls(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) goto out_err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) priv->curr_pixfmt = &s5k4ecgx_formats[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) priv->curr_frmsize = &s5k4ecgx_prev_sizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) out_err2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) s5k4ecgx_free_gpios(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) out_err1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) media_entity_cleanup(&priv->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static int s5k4ecgx_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct s5k4ecgx *priv = to_s5k4ecgx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) mutex_destroy(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) s5k4ecgx_free_gpios(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) v4l2_device_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) v4l2_ctrl_handler_free(&priv->handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) static const struct i2c_device_id s5k4ecgx_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) { S5K4ECGX_DRIVER_NAME, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) MODULE_DEVICE_TABLE(i2c, s5k4ecgx_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static struct i2c_driver v4l2_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .name = S5K4ECGX_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .probe = s5k4ecgx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .remove = s5k4ecgx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) .id_table = s5k4ecgx_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) module_i2c_driver(v4l2_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) MODULE_DESCRIPTION("Samsung S5K4ECGX 5MP SOC camera");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) MODULE_AUTHOR("Sangwook Lee <sangwook.lee@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) MODULE_AUTHOR("Seok-Young Jang <quartz.jang@samsung.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) MODULE_FIRMWARE(S5K4ECGX_FIRMWARE);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags