^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * s5k3l6xx camera driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2022 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X00 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * 1.add flip and mirror support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * 2.fix stream on sequential
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) // #define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/compat.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S5K3L6XX_LINK_FREQ_600MHZ 600000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define S5K3L6XX_LINK_FREQ_284MHZ 284000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define S5K3L6XX_PIXEL_RATE (S5K3L6XX_LINK_FREQ_600MHZ * 2LL * 4LL / 10LL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define S5K3L6XX_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CHIP_ID 0x30c6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define S5K3L6XX_REG_CHIP_ID 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define S5K3L6XX_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define S5K3L6XX_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define S5K3L6XX_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define S5K3L6XX_REG_STREAM_ON 0x3C1E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define S5K3L6XX_REG_EXPOSURE 0x0202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define S5K3L6XX_EXPOSURE_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define S5K3L6XX_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define S5K3L6XX_VTS_MAX 0xfff7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define S5K3L6XX_REG_ANALOG_GAIN 0x0204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define S5K3L6XX_GAIN_MIN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define S5K3L6XX_GAIN_MAX 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define S5K3L6XX_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define S5K3L6XX_GAIN_DEFAULT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define S5K3L6XX_REG_TEST_PATTERN 0x0601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define S5K3L6XX_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define S5K3L6XX_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define S5K3L6XX_REG_VTS 0x0340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define S5K3L6XX_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define S5K3L6XX_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define S5K3L6XX_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define S5K3L6XX_LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define S5K3L6XX_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define S5K3L6XX_CHIP_REVISION_REG 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define S5K3L6XX_NAME "s5k3l6xx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) // #define S5K3L6XX_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) // #define S5K3L6XX_FLIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) // #define S5K3L6XX_FLIP_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #ifdef S5K3L6XX_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define S5K3L6XX_MEDIA_BUS_FMT MEDIA_BUS_FMT_SRGGB10_1X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #elif defined S5K3L6XX_FLIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define S5K3L6XX_MEDIA_BUS_FMT MEDIA_BUS_FMT_SBGGR10_1X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #elif defined S5K3L6XX_FLIP_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define S5K3L6XX_MEDIA_BUS_FMT MEDIA_BUS_FMT_SGBRG10_1X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define S5K3L6XX_MEDIA_BUS_FMT MEDIA_BUS_FMT_SGRBG10_1X10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static const char * const s5k3l6xx_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define S5K3L6XX_NUM_SUPPLIES ARRAY_SIZE(s5k3l6xx_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct s5k3l6xx_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 link_freq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 bpp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct s5k3l6xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct regulator_bulk_data supplies[S5K3L6XX_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const struct s5k3l6xx_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define to_s5k3l6xx(sd) container_of(sd, struct s5k3l6xx, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static const struct regval s5k3l6xx_4208x3120_30fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #ifdef S5K3L6XX_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x0100, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #elif defined S5K3L6XX_FLIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x0100, 0x0002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #elif defined S5K3L6XX_FLIP_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x0100, 0x0003},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x0100, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x0000, 0x0060},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x0000, 0x30C6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x0A02, 0x3400},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x3084, 0x1314},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x3266, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x3242, 0x2020},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x306A, 0x2F4C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x306C, 0xCA01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x307A, 0x0D20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x309E, 0x002D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x3072, 0x0013},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x3074, 0x0977},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x3076, 0x9411},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x3024, 0x0016},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x3070, 0x3D00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x3002, 0x0E00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x3006, 0x1000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x300A, 0x0C00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x3010, 0x0400},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3018, 0xC500},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x303A, 0x0204},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x3452, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x3454, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3456, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3458, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x345a, 0x0002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x345C, 0x0014},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x345E, 0x0002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3460, 0x0014},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3464, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3466, 0x0012},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3468, 0x0012},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x346A, 0x0012},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x346C, 0x0012},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x346E, 0x0012},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3470, 0x0012},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3472, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3474, 0x0004},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3476, 0x0044},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3478, 0x0004},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x347A, 0x0044},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x347E, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3480, 0x0010},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3482, 0x0010},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3484, 0x0010},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3486, 0x0010},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3488, 0x0010},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x348A, 0x0010},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x348E, 0x000C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3490, 0x004C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3492, 0x000C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3494, 0x004C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3496, 0x0020},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3498, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x349A, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x349C, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x349E, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x34A0, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x34A2, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x34A4, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x34A8, 0x001A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x34AA, 0x002A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x34AC, 0x001A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x34AE, 0x002A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x34B0, 0x0080},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x34B2, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x32A2, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x32A4, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x32A6, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x32A8, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x0344, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x0346, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x0348, 0x1077},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x034A, 0x0C37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x034C, 0x1070},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x034E, 0x0C30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x0900, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x0380, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x0382, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x0384, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x0386, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x0114, 0x0330},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x0110, 0x0002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x0136, 0x1800},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x0304, 0x0004},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x0306, 0x0078},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3C1E, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x030C, 0x0004},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x030E, 0x0064},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3C16, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x0300, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x0342, 0x1320},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x0340, 0x0CBC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x38C4, 0x0009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x38D8, 0x002A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x38DA, 0x000A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x38DC, 0x000B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x38C2, 0x000A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x38C0, 0x000F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x38D6, 0x000A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x38D4, 0x0009},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x38B0, 0x000F},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3932, 0x1000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x3934, 0x0180},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3938, 0x000C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x0820, 0x04B0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x380C, 0x0090},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x3064, 0xEFCF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x309C, 0x0640},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3090, 0x8800},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x3238, 0x000C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x314A, 0x5F00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x32B2, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x32B4, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x32B6, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x32B8, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x3300, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x3400, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x3402, 0x4E42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x32B2, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x32B4, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x32B6, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x32B8, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x3C34, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x3C36, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x3C38, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x393E, 0x4000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {REG_NULL, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static const struct regval s5k3l6xx_2104x1560_30fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #ifdef S5K3L6XX_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x0100, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #elif defined S5K3L6XX_FLIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x0100, 0x0002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #elif defined S5K3L6XX_FLIP_MIRROR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x0100, 0x0003},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x0100, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x0000, 0x0050},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x0000, 0x30C6},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x0A02, 0x3400},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3084, 0x1314},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3266, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x3242, 0x2020},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x306A, 0x2F4C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x306C, 0xCA01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x307A, 0x0D20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x309E, 0x002D},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x3072, 0x0013},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x3074, 0x0977},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x3076, 0x9411},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x3024, 0x0016},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x3070, 0x3D00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x3002, 0x0E00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x3006, 0x1000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x300A, 0x0C00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x3010, 0x0400},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x3018, 0xC500},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x303A, 0x0204},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x3452, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x3454, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x3456, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x3458, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x345a, 0x0002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x345C, 0x0014},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x345E, 0x0002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x3460, 0x0014},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x3464, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x3466, 0x0012},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x3468, 0x0012},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x346A, 0x0012},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x346C, 0x0012},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x346E, 0x0012},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x3470, 0x0012},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x3472, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x3474, 0x0004},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x3476, 0x0044},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x3478, 0x0004},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x347A, 0x0044},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x347E, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x3480, 0x0010},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x3482, 0x0010},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x3484, 0x0010},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x3486, 0x0010},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x3488, 0x0010},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x348A, 0x0010},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x348E, 0x000C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x3490, 0x004C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x3492, 0x000C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x3494, 0x004C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x3496, 0x0020},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x3498, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x349A, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x349C, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x349E, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x34A0, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x34A2, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x34A4, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x34A8, 0x001A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x34AA, 0x002A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x34AC, 0x001A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x34AE, 0x002A},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x34B0, 0x0080},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x34B2, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x32A2, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x32A4, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x32A6, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x32A8, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x3066, 0x7E00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x3004, 0x0800},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) //mode setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x0344, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x0346, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x0348, 0x1077},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x034A, 0x0C37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x034C, 0x0838},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x034E, 0x0618},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x0900, 0x0122},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x0380, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x0382, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x0384, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x0386, 0x0003},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x0114, 0x0330},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x0110, 0x0002},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x0136, 0x1800},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x0304, 0x0004},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x0306, 0x0078},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x3C1E, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x030C, 0x0003},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x030E, 0x0047},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x3C16, 0x0001},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x0300, 0x0006},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x0342, 0x1320},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x0340, 0x0CBC},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x38C4, 0x0004},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x38D8, 0x0011},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x38DA, 0x0005},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x38DC, 0x0005},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x38C2, 0x0005},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x38C0, 0x0004},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x38D6, 0x0004},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x38D4, 0x0004},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x38B0, 0x0007},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x3932, 0x1000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x3934, 0x0180},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x3938, 0x000C},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x0820, 0x0238},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x380C, 0x0049},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x3064, 0xFFCF},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x309C, 0x0640},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x3090, 0x8000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x3238, 0x000B},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x314A, 0x5F02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x3300, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x3400, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x3402, 0x4E46},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x32B2, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x32B4, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x32B6, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x32B8, 0x0008},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x3C34, 0x0048},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x3C36, 0x3000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x3C38, 0x0020},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x393E, 0x4000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x303A, 0x0204},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x3034, 0x4B01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x3036, 0x0029},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3032, 0x4800},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x320E, 0x049E},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {REG_NULL, 0x0000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const struct s5k3l6xx_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .width = 4208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .height = 3120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .exp_def = 0x0cb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .hts_def = 0x1320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .vts_def = 0x0cbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .reg_list = s5k3l6xx_4208x3120_30fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .link_freq_idx = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .width = 2104,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .height = 1560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .exp_def = 0x0cb0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .hts_def = 0x1320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .vts_def = 0x0cbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .bpp = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .reg_list = s5k3l6xx_2104x1560_30fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .link_freq_idx = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) static const s64 link_freq_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) S5K3L6XX_LINK_FREQ_600MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) S5K3L6XX_LINK_FREQ_284MHZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static const char * const s5k3l6xx_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) "Vertical Color Bar Type 3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int s5k3l6xx_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dev_dbg(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int s5k3l6xx_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) ret = s5k3l6xx_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) S5K3L6XX_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static int s5k3l6xx_read_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int s5k3l6xx_get_reso_dist(const struct s5k3l6xx_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static const struct s5k3l6xx_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) s5k3l6xx_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dist = s5k3l6xx_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static int s5k3l6xx_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) const struct s5k3l6xx_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) u64 pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) u32 lane_num = S5K3L6XX_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) mutex_lock(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) mode = s5k3l6xx_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) fmt->format.code = S5K3L6XX_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) mutex_unlock(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) s5k3l6xx->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) __v4l2_ctrl_modify_range(s5k3l6xx->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) __v4l2_ctrl_modify_range(s5k3l6xx->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) S5K3L6XX_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) __v4l2_ctrl_s_ctrl_int64(s5k3l6xx->pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) __v4l2_ctrl_s_ctrl(s5k3l6xx->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) mode->link_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) mutex_unlock(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static int s5k3l6xx_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) const struct s5k3l6xx_mode *mode = s5k3l6xx->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) mutex_lock(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) mutex_unlock(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) fmt->format.code = S5K3L6XX_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) mutex_unlock(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static int s5k3l6xx_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) code->code = S5K3L6XX_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int s5k3l6xx_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (fse->code != S5K3L6XX_MEDIA_BUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) static int s5k3l6xx_enable_test_pattern(struct s5k3l6xx *s5k3l6xx, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) val = (pattern - 1) | S5K3L6XX_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) val = S5K3L6XX_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return s5k3l6xx_write_reg(s5k3l6xx->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) S5K3L6XX_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) S5K3L6XX_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int s5k3l6xx_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) const struct s5k3l6xx_mode *mode = s5k3l6xx->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) mutex_lock(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) mutex_unlock(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) static void s5k3l6xx_get_module_inf(struct s5k3l6xx *s5k3l6xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) strscpy(inf->base.sensor, S5K3L6XX_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) strscpy(inf->base.module, s5k3l6xx->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) strscpy(inf->base.lens, s5k3l6xx->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static long s5k3l6xx_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) s5k3l6xx_get_module_inf(s5k3l6xx, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ret = s5k3l6xx_write_reg(s5k3l6xx->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) S5K3L6XX_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) S5K3L6XX_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) S5K3L6XX_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ret = s5k3l6xx_write_reg(s5k3l6xx->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) S5K3L6XX_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) S5K3L6XX_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) S5K3L6XX_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static long s5k3l6xx_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) ret = s5k3l6xx_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret = s5k3l6xx_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ret = s5k3l6xx_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static int __s5k3l6xx_start_stream(struct s5k3l6xx *s5k3l6xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ret = s5k3l6xx_write_array(s5k3l6xx->client, s5k3l6xx->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) mutex_unlock(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ret = v4l2_ctrl_handler_setup(&s5k3l6xx->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) mutex_lock(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) s5k3l6xx_write_reg(s5k3l6xx->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) S5K3L6XX_REG_STREAM_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) S5K3L6XX_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) S5K3L6XX_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) s5k3l6xx_write_reg(s5k3l6xx->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) S5K3L6XX_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) S5K3L6XX_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) S5K3L6XX_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) s5k3l6xx_write_reg(s5k3l6xx->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) S5K3L6XX_REG_STREAM_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) S5K3L6XX_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) S5K3L6XX_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) static int __s5k3l6xx_stop_stream(struct s5k3l6xx *s5k3l6xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return s5k3l6xx_write_reg(s5k3l6xx->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) S5K3L6XX_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) S5K3L6XX_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) S5K3L6XX_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) static int s5k3l6xx_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct i2c_client *client = s5k3l6xx->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev_info(&client->dev, "%s: on: %d, %dx%d@%d\n", __func__, on,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) s5k3l6xx->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) s5k3l6xx->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) DIV_ROUND_CLOSEST(s5k3l6xx->cur_mode->max_fps.denominator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) s5k3l6xx->cur_mode->max_fps.numerator));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) mutex_lock(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (on == s5k3l6xx->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ret = __s5k3l6xx_start_stream(s5k3l6xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) __s5k3l6xx_stop_stream(s5k3l6xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) s5k3l6xx->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) mutex_unlock(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static int s5k3l6xx_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct i2c_client *client = s5k3l6xx->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) mutex_lock(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (s5k3l6xx->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) s5k3l6xx->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) s5k3l6xx->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) mutex_unlock(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) static inline u32 s5k3l6xx_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) return DIV_ROUND_UP(cycles, S5K3L6XX_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) static int __s5k3l6xx_power_on(struct s5k3l6xx *s5k3l6xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct device *dev = &s5k3l6xx->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (!IS_ERR(s5k3l6xx->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) gpiod_set_value_cansleep(s5k3l6xx->power_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (!IS_ERR_OR_NULL(s5k3l6xx->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ret = pinctrl_select_state(s5k3l6xx->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) s5k3l6xx->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ret = clk_set_rate(s5k3l6xx->xvclk, S5K3L6XX_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (clk_get_rate(s5k3l6xx->xvclk) != S5K3L6XX_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) ret = clk_prepare_enable(s5k3l6xx->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (!IS_ERR(s5k3l6xx->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) gpiod_set_value_cansleep(s5k3l6xx->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ret = regulator_bulk_enable(S5K3L6XX_NUM_SUPPLIES, s5k3l6xx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (!IS_ERR(s5k3l6xx->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) gpiod_set_value_cansleep(s5k3l6xx->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (!IS_ERR(s5k3l6xx->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) gpiod_set_value_cansleep(s5k3l6xx->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) delay_us = s5k3l6xx_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) clk_disable_unprepare(s5k3l6xx->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static void __s5k3l6xx_power_off(struct s5k3l6xx *s5k3l6xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) struct device *dev = &s5k3l6xx->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (!IS_ERR(s5k3l6xx->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) gpiod_set_value_cansleep(s5k3l6xx->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) clk_disable_unprepare(s5k3l6xx->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (!IS_ERR(s5k3l6xx->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) gpiod_set_value_cansleep(s5k3l6xx->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (!IS_ERR_OR_NULL(s5k3l6xx->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ret = pinctrl_select_state(s5k3l6xx->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) s5k3l6xx->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (!IS_ERR(s5k3l6xx->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) gpiod_set_value_cansleep(s5k3l6xx->power_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) regulator_bulk_disable(S5K3L6XX_NUM_SUPPLIES, s5k3l6xx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) static int s5k3l6xx_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return __s5k3l6xx_power_on(s5k3l6xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static int s5k3l6xx_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) __s5k3l6xx_power_off(s5k3l6xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static int s5k3l6xx_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) const struct s5k3l6xx_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) mutex_lock(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) try_fmt->code = S5K3L6XX_MEDIA_BUS_FMT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) mutex_unlock(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) static int s5k3l6xx_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (fie->code != S5K3L6XX_MEDIA_BUS_FMT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static int s5k3l6xx_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (2 == S5K3L6XX_LANES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) config->flags = V4L2_MBUS_CSI2_2_LANE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) } else if (4 == S5K3L6XX_LANES) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) config->flags = V4L2_MBUS_CSI2_4_LANE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) #define CROP_START(SRC, DST) (((SRC) - (DST)) / 2 / 4 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define DST_WIDTH_2096 2096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define DST_HEIGHT_1560 1560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static int s5k3l6xx_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (sel->target == V4L2_SEL_TGT_CROP_BOUNDS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (s5k3l6xx->cur_mode->width == 2104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) sel->r.left = CROP_START(s5k3l6xx->cur_mode->width, DST_WIDTH_2096);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) sel->r.width = DST_WIDTH_2096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) sel->r.top = CROP_START(s5k3l6xx->cur_mode->height, DST_HEIGHT_1560);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) sel->r.height = DST_HEIGHT_1560;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) sel->r.left = CROP_START(s5k3l6xx->cur_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) s5k3l6xx->cur_mode->width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) sel->r.width = s5k3l6xx->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) sel->r.top = CROP_START(s5k3l6xx->cur_mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) s5k3l6xx->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) sel->r.height = s5k3l6xx->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) static const struct dev_pm_ops s5k3l6xx_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) SET_RUNTIME_PM_OPS(s5k3l6xx_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) s5k3l6xx_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) static const struct v4l2_subdev_internal_ops s5k3l6xx_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .open = s5k3l6xx_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static const struct v4l2_subdev_core_ops s5k3l6xx_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .s_power = s5k3l6xx_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .ioctl = s5k3l6xx_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .compat_ioctl32 = s5k3l6xx_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static const struct v4l2_subdev_video_ops s5k3l6xx_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .s_stream = s5k3l6xx_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) .g_frame_interval = s5k3l6xx_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) static const struct v4l2_subdev_pad_ops s5k3l6xx_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) .enum_mbus_code = s5k3l6xx_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) .enum_frame_size = s5k3l6xx_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) .enum_frame_interval = s5k3l6xx_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) .get_fmt = s5k3l6xx_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) .set_fmt = s5k3l6xx_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) .get_selection = s5k3l6xx_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .get_mbus_config = s5k3l6xx_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) static const struct v4l2_subdev_ops s5k3l6xx_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .core = &s5k3l6xx_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .video = &s5k3l6xx_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) .pad = &s5k3l6xx_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) static int s5k3l6xx_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) struct s5k3l6xx *s5k3l6xx = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) struct s5k3l6xx, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) struct i2c_client *client = s5k3l6xx->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) max = s5k3l6xx->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) __v4l2_ctrl_modify_range(s5k3l6xx->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) s5k3l6xx->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) s5k3l6xx->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) s5k3l6xx->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ret = s5k3l6xx_write_reg(s5k3l6xx->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) S5K3L6XX_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) S5K3L6XX_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ret = s5k3l6xx_write_reg(s5k3l6xx->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) S5K3L6XX_REG_ANALOG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) S5K3L6XX_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) ret = s5k3l6xx_write_reg(s5k3l6xx->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) S5K3L6XX_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) S5K3L6XX_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) ctrl->val + s5k3l6xx->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ret = s5k3l6xx_enable_test_pattern(s5k3l6xx, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) static const struct v4l2_ctrl_ops s5k3l6xx_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .s_ctrl = s5k3l6xx_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static int s5k3l6xx_initialize_controls(struct s5k3l6xx *s5k3l6xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) const struct s5k3l6xx_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) u64 dst_pixel_rate = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) u32 lane_num = S5K3L6XX_LANES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) handler = &s5k3l6xx->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) mode = s5k3l6xx->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) handler->lock = &s5k3l6xx->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) s5k3l6xx->link_freq = v4l2_ctrl_new_int_menu(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) 1, 0, link_freq_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) dst_pixel_rate = (u32)link_freq_items[mode->link_freq_idx] / mode->bpp * 2 * lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) s5k3l6xx->pixel_rate = v4l2_ctrl_new_std(handler, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) 0, S5K3L6XX_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) 1, dst_pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) __v4l2_ctrl_s_ctrl(s5k3l6xx->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) mode->link_freq_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) s5k3l6xx->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (s5k3l6xx->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) s5k3l6xx->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) s5k3l6xx->vblank = v4l2_ctrl_new_std(handler, &s5k3l6xx_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) S5K3L6XX_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) s5k3l6xx->exposure = v4l2_ctrl_new_std(handler, &s5k3l6xx_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) V4L2_CID_EXPOSURE, S5K3L6XX_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) exposure_max, S5K3L6XX_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) s5k3l6xx->anal_gain = v4l2_ctrl_new_std(handler, &s5k3l6xx_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) V4L2_CID_ANALOGUE_GAIN, S5K3L6XX_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) S5K3L6XX_GAIN_MAX, S5K3L6XX_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) S5K3L6XX_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) s5k3l6xx->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) &s5k3l6xx_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) ARRAY_SIZE(s5k3l6xx_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) 0, 0, s5k3l6xx_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) dev_err(&s5k3l6xx->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) s5k3l6xx->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static int s5k3l6xx_check_sensor_id(struct s5k3l6xx *s5k3l6xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct device *dev = &s5k3l6xx->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) ret = s5k3l6xx_read_reg(client, S5K3L6XX_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) S5K3L6XX_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) ret = s5k3l6xx_read_reg(client, S5K3L6XX_CHIP_REVISION_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) S5K3L6XX_REG_VALUE_08BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) dev_err(dev, "Read chip revision register error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) dev_info(dev, "Detected Samsung %04x sensor, REVISION 0x%x\n", CHIP_ID, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) static int s5k3l6xx_configure_regulators(struct s5k3l6xx *s5k3l6xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) for (i = 0; i < S5K3L6XX_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) s5k3l6xx->supplies[i].supply = s5k3l6xx_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) return devm_regulator_bulk_get(&s5k3l6xx->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) S5K3L6XX_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) s5k3l6xx->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static int s5k3l6xx_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) struct s5k3l6xx *s5k3l6xx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) s5k3l6xx = devm_kzalloc(dev, sizeof(*s5k3l6xx), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) if (!s5k3l6xx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) &s5k3l6xx->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) &s5k3l6xx->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) &s5k3l6xx->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) &s5k3l6xx->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) s5k3l6xx->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) s5k3l6xx->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) s5k3l6xx->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (IS_ERR(s5k3l6xx->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) s5k3l6xx->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (IS_ERR(s5k3l6xx->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) s5k3l6xx->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) if (IS_ERR(s5k3l6xx->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) s5k3l6xx->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (IS_ERR(s5k3l6xx->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) ret = s5k3l6xx_configure_regulators(s5k3l6xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) s5k3l6xx->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (!IS_ERR(s5k3l6xx->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) s5k3l6xx->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) pinctrl_lookup_state(s5k3l6xx->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (IS_ERR(s5k3l6xx->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) s5k3l6xx->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) pinctrl_lookup_state(s5k3l6xx->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (IS_ERR(s5k3l6xx->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) mutex_init(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) sd = &s5k3l6xx->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) v4l2_i2c_subdev_init(sd, client, &s5k3l6xx_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) ret = s5k3l6xx_initialize_controls(s5k3l6xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) ret = __s5k3l6xx_power_on(s5k3l6xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) ret = s5k3l6xx_check_sensor_id(s5k3l6xx, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) sd->internal_ops = &s5k3l6xx_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) s5k3l6xx->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ret = media_entity_pads_init(&sd->entity, 1, &s5k3l6xx->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (strcmp(s5k3l6xx->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) s5k3l6xx->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) S5K3L6XX_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) __s5k3l6xx_power_off(s5k3l6xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) v4l2_ctrl_handler_free(&s5k3l6xx->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) mutex_destroy(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static int s5k3l6xx_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) struct s5k3l6xx *s5k3l6xx = to_s5k3l6xx(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) v4l2_ctrl_handler_free(&s5k3l6xx->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) mutex_destroy(&s5k3l6xx->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) __s5k3l6xx_power_off(s5k3l6xx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) static const struct of_device_id s5k3l6xx_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) { .compatible = "samsung,s5k3l6xx" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) MODULE_DEVICE_TABLE(of, s5k3l6xx_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) static const struct i2c_device_id s5k3l6xx_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) { "samsung,s5k3l6xx", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static struct i2c_driver s5k3l6xx_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .name = S5K3L6XX_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .pm = &s5k3l6xx_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .of_match_table = of_match_ptr(s5k3l6xx_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .probe = &s5k3l6xx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .remove = &s5k3l6xx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .id_table = s5k3l6xx_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) return i2c_add_driver(&s5k3l6xx_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) i2c_del_driver(&s5k3l6xx_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) MODULE_DESCRIPTION("Samsung s5k3l6xx sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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