^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Samsung LSI S5C73M3 8M pixel camera driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2012, Samsung Electronics, Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Sylwester Nawrocki <s.nawrocki@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Andrzej Hajda <a.hajda@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef S5C73M3_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define S5C73M3_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <media/i2c/s5c73m3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DRIVER_NAME "S5C73M3"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define S5C73M3_ISP_FMT MEDIA_BUS_FMT_VYUY8_2X8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define S5C73M3_JPEG_FMT MEDIA_BUS_FMT_S5C_UYVY_JPEG_1X8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* Subdevs pad index definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) enum s5c73m3_pads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) S5C73M3_ISP_PAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) S5C73M3_JPEG_PAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) S5C73M3_NUM_PADS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) enum s5c73m3_oif_pads {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) OIF_ISP_PAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) OIF_JPEG_PAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) OIF_SOURCE_PAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) OIF_NUM_PADS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define S5C73M3_SENSOR_FW_LEN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define S5C73M3_SENSOR_TYPE_LEN 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define S5C73M3_REG(_addrh, _addrl) (((_addrh) << 16) | _addrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AHB_MSB_ADDR_PTR 0xfcfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_CMDWR_ADDRH 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_CMDWR_ADDRL 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_CMDRD_ADDRH 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_CMDRD_ADDRL 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define REG_CMDBUF_ADDR 0x0f14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_I2C_SEQ_STATUS S5C73M3_REG(0x0009, 0x59A6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SEQ_END_PLL (1<<0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SEQ_END_SENSOR (1<<0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SEQ_END_GPIO (1<<0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SEQ_END_FROM (1<<0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SEQ_END_STABLE_AE_AWB (1<<0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SEQ_END_READY_I2C_CMD (1<<0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_I2C_STATUS S5C73M3_REG(0x0009, 0x599E)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define I2C_STATUS_CIS_I2C (1<<0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define I2C_STATUS_AF_INIT (1<<0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define I2C_STATUS_CAL_DATA (1<<0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define I2C_STATUS_FRAME_COUNT (1<<0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define I2C_STATUS_FROM_INIT (1<<0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define I2C_STATUS_I2C_CIS_STREAM_OFF (1<<0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define I2C_STATUS_I2C_N_CMD_OVER (1<<0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define I2C_STATUS_I2C_N_CMD_MISMATCH (1<<0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define I2C_STATUS_CHECK_BIN_CRC (1<<0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define I2C_STATUS_EXCEPTION (1<<0x9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define I2C_STATUS_INIF_INIT_STATE (0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define REG_STATUS S5C73M3_REG(0x0009, 0x5080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define REG_STATUS_BOOT_SUB_MAIN_ENTER 0xff01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define REG_STATUS_BOOT_SRAM_TIMING_OK 0xff02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REG_STATUS_BOOT_INTERRUPTS_EN 0xff03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define REG_STATUS_BOOT_R_PLL_DONE 0xff04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REG_STATUS_BOOT_R_PLL_LOCKTIME_DONE 0xff05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define REG_STATUS_BOOT_DELAY_COUNT_DONE 0xff06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define REG_STATUS_BOOT_I_PLL_DONE 0xff07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define REG_STATUS_BOOT_I_PLL_LOCKTIME_DONE 0xff08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define REG_STATUS_BOOT_PLL_INIT_OK 0xff09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define REG_STATUS_BOOT_SENSOR_INIT_OK 0xff0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define REG_STATUS_BOOT_GPIO_SETTING_OK 0xff0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define REG_STATUS_BOOT_READ_CAL_DATA_OK 0xff0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define REG_STATUS_BOOT_STABLE_AE_AWB_OK 0xff0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define REG_STATUS_ISP_COMMAND_COMPLETED 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define REG_STATUS_EXCEPTION_OCCURED 0xdead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define COMM_RESULT_OFFSET S5C73M3_REG(0x0009, 0x5000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define COMM_IMG_OUTPUT 0x0902
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define COMM_IMG_OUTPUT_HDR 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define COMM_IMG_OUTPUT_YUV 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define COMM_IMG_OUTPUT_INTERLEAVED 0x000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define COMM_STILL_PRE_FLASH 0x0a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define COMM_STILL_PRE_FLASH_FIRE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define COMM_STILL_PRE_FLASH_NON_FIRED 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define COMM_STILL_PRE_FLASH_FIRED 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define COMM_STILL_MAIN_FLASH 0x0a02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define COMM_STILL_MAIN_FLASH_CANCEL 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define COMM_STILL_MAIN_FLASH_FIRE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define COMM_ZOOM_STEP 0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define COMM_IMAGE_EFFECT 0x0b0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define COMM_IMAGE_EFFECT_NONE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define COMM_IMAGE_EFFECT_NEGATIVE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define COMM_IMAGE_EFFECT_AQUA 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define COMM_IMAGE_EFFECT_SEPIA 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define COMM_IMAGE_EFFECT_MONO 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define COMM_IMAGE_QUALITY 0x0b0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define COMM_IMAGE_QUALITY_SUPERFINE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define COMM_IMAGE_QUALITY_FINE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define COMM_IMAGE_QUALITY_NORMAL 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define COMM_FLASH_MODE 0x0b0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define COMM_FLASH_MODE_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define COMM_FLASH_MODE_ON 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define COMM_FLASH_MODE_AUTO 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define COMM_FLASH_STATUS 0x0b80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define COMM_FLASH_STATUS_OFF 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define COMM_FLASH_STATUS_ON 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define COMM_FLASH_STATUS_AUTO 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define COMM_FLASH_TORCH 0x0b12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define COMM_FLASH_TORCH_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define COMM_FLASH_TORCH_ON 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define COMM_AE_NEEDS_FLASH 0x0cba
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define COMM_AE_NEEDS_FLASH_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define COMM_AE_NEEDS_FLASH_ON 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define COMM_CHG_MODE 0x0b10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define COMM_CHG_MODE_NEW 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define COMM_CHG_MODE_SUBSAMPLING_HALF 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define COMM_CHG_MODE_SUBSAMPLING_QUARTER 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define COMM_CHG_MODE_YUV_320_240 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define COMM_CHG_MODE_YUV_640_480 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define COMM_CHG_MODE_YUV_880_720 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define COMM_CHG_MODE_YUV_960_720 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define COMM_CHG_MODE_YUV_1184_666 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define COMM_CHG_MODE_YUV_1280_720 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define COMM_CHG_MODE_YUV_1536_864 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define COMM_CHG_MODE_YUV_1600_1200 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define COMM_CHG_MODE_YUV_1632_1224 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define COMM_CHG_MODE_YUV_1920_1080 0x000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define COMM_CHG_MODE_YUV_1920_1440 0x000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define COMM_CHG_MODE_YUV_2304_1296 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define COMM_CHG_MODE_YUV_3264_2448 0x000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define COMM_CHG_MODE_YUV_352_288 0x000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define COMM_CHG_MODE_YUV_1008_672 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define COMM_CHG_MODE_JPEG_640_480 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define COMM_CHG_MODE_JPEG_800_450 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define COMM_CHG_MODE_JPEG_800_600 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define COMM_CHG_MODE_JPEG_1280_720 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define COMM_CHG_MODE_JPEG_1280_960 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define COMM_CHG_MODE_JPEG_1600_900 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define COMM_CHG_MODE_JPEG_1600_1200 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define COMM_CHG_MODE_JPEG_2048_1152 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define COMM_CHG_MODE_JPEG_2048_1536 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define COMM_CHG_MODE_JPEG_2560_1440 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define COMM_CHG_MODE_JPEG_2560_1920 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define COMM_CHG_MODE_JPEG_3264_2176 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define COMM_CHG_MODE_JPEG_1024_768 0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define COMM_CHG_MODE_JPEG_3264_1836 0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define COMM_CHG_MODE_JPEG_3264_2448 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define COMM_AF_CON 0x0e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define COMM_AF_CON_STOP 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define COMM_AF_CON_SCAN 0x0001 /* Full Search */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define COMM_AF_CON_START 0x0002 /* Fast Search */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define COMM_AF_CAL 0x0e06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define COMM_AF_TOUCH_AF 0x0e0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define REG_AF_STATUS S5C73M3_REG(0x0009, 0x5e80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define REG_CAF_STATUS_FIND_SEARCH_DIR 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define REG_CAF_STATUS_FOCUSING 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define REG_CAF_STATUS_FOCUSED 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define REG_CAF_STATUS_UNFOCUSED 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define REG_AF_STATUS_INVALID 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define REG_AF_STATUS_FOCUSING 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define REG_AF_STATUS_FOCUSED 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define REG_AF_STATUS_UNFOCUSED 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define REG_AF_TOUCH_POSITION S5C73M3_REG(0x0009, 0x5e8e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define COMM_AF_FACE_ZOOM 0x0e10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define COMM_AF_MODE 0x0e02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define COMM_AF_MODE_NORMAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define COMM_AF_MODE_MACRO 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define COMM_AF_MODE_MOVIE_CAF_START 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define COMM_AF_MODE_MOVIE_CAF_STOP 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define COMM_AF_MODE_PREVIEW_CAF_START 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define COMM_AF_MODE_PREVIEW_CAF_STOP 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define COMM_AF_SOFTLANDING 0x0e16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define COMM_AF_SOFTLANDING_ON 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define COMM_AF_SOFTLANDING_RES_COMPLETE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define COMM_FACE_DET 0x0e0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define COMM_FACE_DET_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define COMM_FACE_DET_ON 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define COMM_FACE_DET_OSD 0x0e0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define COMM_FACE_DET_OSD_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define COMM_FACE_DET_OSD_ON 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define COMM_AE_CON 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define COMM_AE_STOP 0x0000 /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define COMM_AE_START 0x0001 /* unlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define COMM_ISO 0x0c02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define COMM_ISO_AUTO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define COMM_ISO_100 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define COMM_ISO_200 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define COMM_ISO_400 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define COMM_ISO_800 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define COMM_ISO_SPORTS 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define COMM_ISO_NIGHT 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define COMM_ISO_INDOOR 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* 0x00000 (-2.0 EV)...0x0008 (2.0 EV), 0.5EV step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define COMM_EV 0x0c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define COMM_METERING 0x0c06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define COMM_METERING_CENTER 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define COMM_METERING_SPOT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define COMM_METERING_AVERAGE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define COMM_METERING_SMART 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define COMM_WDR 0x0c08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define COMM_WDR_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define COMM_WDR_ON 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define COMM_FLICKER_MODE 0x0c12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define COMM_FLICKER_NONE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define COMM_FLICKER_MANUAL_50HZ 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define COMM_FLICKER_MANUAL_60HZ 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define COMM_FLICKER_AUTO 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define COMM_FLICKER_AUTO_50HZ 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define COMM_FLICKER_AUTO_60HZ 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define COMM_FRAME_RATE 0x0c1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define COMM_FRAME_RATE_AUTO_SET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define COMM_FRAME_RATE_FIXED_30FPS 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define COMM_FRAME_RATE_FIXED_20FPS 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define COMM_FRAME_RATE_FIXED_15FPS 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define COMM_FRAME_RATE_FIXED_60FPS 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define COMM_FRAME_RATE_FIXED_120FPS 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define COMM_FRAME_RATE_FIXED_7FPS 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define COMM_FRAME_RATE_FIXED_10FPS 0x000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define COMM_FRAME_RATE_FIXED_90FPS 0x000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define COMM_FRAME_RATE_ANTI_SHAKE 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* 0x0000...0x0004 -> sharpness: 0, 1, 2, -1, -2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define COMM_SHARPNESS 0x0c14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* 0x0000...0x0004 -> saturation: 0, 1, 2, -1, -2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define COMM_SATURATION 0x0c16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* 0x0000...0x0004 -> contrast: 0, 1, 2, -1, -2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define COMM_CONTRAST 0x0c18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define COMM_SCENE_MODE 0x0c1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define COMM_SCENE_MODE_NONE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define COMM_SCENE_MODE_PORTRAIT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define COMM_SCENE_MODE_LANDSCAPE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define COMM_SCENE_MODE_SPORTS 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define COMM_SCENE_MODE_INDOOR 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define COMM_SCENE_MODE_BEACH 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define COMM_SCENE_MODE_SUNSET 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define COMM_SCENE_MODE_DAWN 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define COMM_SCENE_MODE_FALL 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define COMM_SCENE_MODE_NIGHT 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define COMM_SCENE_MODE_AGAINST_LIGHT 0x000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define COMM_SCENE_MODE_FIRE 0x000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define COMM_SCENE_MODE_TEXT 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define COMM_SCENE_MODE_CANDLE 0x000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define COMM_AE_AUTO_BRACKET 0x0b14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define COMM_AE_AUTO_BRAKET_EV05 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define COMM_AE_AUTO_BRAKET_EV10 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define COMM_AE_AUTO_BRAKET_EV15 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define COMM_AE_AUTO_BRAKET_EV20 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define COMM_SENSOR_STREAMING 0x090a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define COMM_SENSOR_STREAMING_OFF 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define COMM_SENSOR_STREAMING_ON 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define COMM_AWB_MODE 0x0d02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define COMM_AWB_MODE_INCANDESCENT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define COMM_AWB_MODE_FLUORESCENT1 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define COMM_AWB_MODE_FLUORESCENT2 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define COMM_AWB_MODE_DAYLIGHT 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define COMM_AWB_MODE_CLOUDY 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define COMM_AWB_MODE_AUTO 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define COMM_AWB_CON 0x0d00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define COMM_AWB_STOP 0x0000 /* lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define COMM_AWB_START 0x0001 /* unlock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define COMM_FW_UPDATE 0x0906
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define COMM_FW_UPDATE_NOT_READY 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define COMM_FW_UPDATE_SUCCESS 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define COMM_FW_UPDATE_FAIL 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define COMM_FW_UPDATE_BUSY 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define S5C73M3_MAX_SUPPLIES 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define S5C73M3_DEFAULT_MCLK_FREQ 24000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct s5c73m3_ctrls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct v4l2_ctrl_handler handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* exposure/exposure bias cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct v4l2_ctrl *auto_exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct v4l2_ctrl *exposure_bias;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct v4l2_ctrl *exposure_metering;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* iso/auto iso cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct v4l2_ctrl *auto_iso;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct v4l2_ctrl *iso;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct v4l2_ctrl *auto_wb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* continuous auto focus/auto focus cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct v4l2_ctrl *focus_auto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct v4l2_ctrl *af_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct v4l2_ctrl *af_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct v4l2_ctrl *af_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct v4l2_ctrl *af_distance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct v4l2_ctrl *aaa_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct v4l2_ctrl *colorfx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct v4l2_ctrl *contrast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) struct v4l2_ctrl *saturation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct v4l2_ctrl *sharpness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct v4l2_ctrl *zoom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct v4l2_ctrl *wdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct v4l2_ctrl *stabilization;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct v4l2_ctrl *jpeg_quality;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct v4l2_ctrl *scene_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) enum s5c73m3_gpio_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) STBY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) RSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) GPIO_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) enum s5c73m3_resolution_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) RES_ISP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) RES_JPEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct s5c73m3_interval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u16 fps_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct v4l2_fract interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Maximum rectangle for the interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct v4l2_frmsize_discrete size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct s5c73m3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct v4l2_subdev sensor_sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct media_pad sensor_pads[S5C73M3_NUM_PADS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct v4l2_subdev oif_sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct media_pad oif_pads[OIF_NUM_PADS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct spi_driver spidrv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct spi_device *spi_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct i2c_client *i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u32 i2c_write_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u32 i2c_read_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) struct regulator_bulk_data supplies[S5C73M3_MAX_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct s5c73m3_gpio gpio[GPIO_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* External master clock frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) u32 mclk_frequency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* Video bus type - MIPI-CSI2/parallel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) enum v4l2_mbus_type bus_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) const struct s5c73m3_frame_size *sensor_pix_size[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) const struct s5c73m3_frame_size *oif_pix_size[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u32 mbus_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) const struct s5c73m3_interval *fiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct v4l2_mbus_frame_desc frame_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* protects the struct members below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct s5c73m3_ctrls ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u8 streaming:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u8 apply_fmt:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u8 apply_fiv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u8 isp_ready:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) short power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) char sensor_fw[S5C73M3_SENSOR_FW_LEN + 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) char sensor_type[S5C73M3_SENSOR_TYPE_LEN + 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) char fw_file_version[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned int fw_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct s5c73m3_frame_size {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u8 reg_val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) extern int s5c73m3_dbg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int s5c73m3_register_spi_driver(struct s5c73m3 *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) void s5c73m3_unregister_spi_driver(struct s5c73m3 *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) int s5c73m3_spi_write(struct s5c73m3 *state, const void *addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) const unsigned int len, const unsigned int tx_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int s5c73m3_spi_read(struct s5c73m3 *state, void *addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) const unsigned int len, const unsigned int tx_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) int s5c73m3_read(struct s5c73m3 *state, u32 addr, u16 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) int s5c73m3_write(struct s5c73m3 *state, u32 addr, u16 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int s5c73m3_isp_command(struct s5c73m3 *state, u16 command, u16 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) int s5c73m3_init_controls(struct s5c73m3 *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static inline struct v4l2_subdev *ctrl_to_sensor_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) return &container_of(ctrl->handler, struct s5c73m3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) ctrls.handler)->sensor_sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static inline struct s5c73m3 *sensor_sd_to_s5c73m3(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) return container_of(sd, struct s5c73m3, sensor_sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static inline struct s5c73m3 *oif_sd_to_s5c73m3(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return container_of(sd, struct s5c73m3, oif_sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #endif /* S5C73M3_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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