^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2020 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Shunqing Chen <csq@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "rk628.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "rk628_combrxphy.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "rk628_combtxphy.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "rk628_cru.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "rk628_csi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "rk628_dsi.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include "rk628_hdmirx.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static const struct regmap_range rk628_cru_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) regmap_reg_range(CRU_CPLL_CON0, CRU_CPLL_CON4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) regmap_reg_range(CRU_GPLL_CON0, CRU_GPLL_CON4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) regmap_reg_range(CRU_MODE_CON00, CRU_MODE_CON00),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) regmap_reg_range(CRU_CLKSEL_CON00, CRU_CLKSEL_CON21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) regmap_reg_range(CRU_GATE_CON00, CRU_GATE_CON05),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) regmap_reg_range(CRU_SOFTRST_CON00, CRU_SOFTRST_CON04),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) static const struct regmap_access_table rk628_cru_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) .yes_ranges = rk628_cru_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) .n_yes_ranges = ARRAY_SIZE(rk628_cru_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static const struct regmap_range rk628_combrxphy_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) regmap_reg_range(COMBRX_REG(0x6600), COMBRX_REG(0x665b)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) regmap_reg_range(COMBRX_REG(0x66a0), COMBRX_REG(0x66db)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) regmap_reg_range(COMBRX_REG(0x66f0), COMBRX_REG(0x66ff)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) regmap_reg_range(COMBRX_REG(0x6700), COMBRX_REG(0x6790)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static const struct regmap_access_table rk628_combrxphy_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .yes_ranges = rk628_combrxphy_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .n_yes_ranges = ARRAY_SIZE(rk628_combrxphy_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static const struct regmap_range rk628_hdmirx_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) regmap_reg_range(HDMI_RX_HDMI_SETUP_CTRL, HDMI_RX_HDMI_SETUP_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) regmap_reg_range(HDMI_RX_HDMI_PCB_CTRL, HDMI_RX_HDMI_PCB_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) regmap_reg_range(HDMI_RX_HDMI_MODE_RECOVER, HDMI_RX_HDMI_ERROR_PROTECT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) regmap_reg_range(HDMI_RX_HDMI_SYNC_CTRL, HDMI_RX_HDMI_CKM_RESULT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) regmap_reg_range(HDMI_RX_HDMI_RESMPL_CTRL, HDMI_RX_HDMI_RESMPL_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) regmap_reg_range(HDMI_VM_CFG_CH2, HDMI_VM_CFG_CH2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) regmap_reg_range(HDMI_RX_HDCP_CTRL, HDMI_RX_HDCP_SETTINGS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) regmap_reg_range(HDMI_RX_HDCP_KIDX, HDMI_RX_HDCP_KIDX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) regmap_reg_range(HDMI_RX_HDCP_DBG, HDMI_RX_HDCP_AN0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) regmap_reg_range(HDMI_RX_HDCP_STS, HDMI_RX_HDCP_STS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) regmap_reg_range(HDMI_RX_MD_HCTRL1, HDMI_RX_MD_HACT_PX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) regmap_reg_range(HDMI_RX_MD_VCTRL, HDMI_RX_MD_VSC),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) regmap_reg_range(HDMI_RX_MD_VOL, HDMI_RX_MD_VTL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) regmap_reg_range(HDMI_RX_MD_IL_POL, HDMI_RX_MD_STS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) regmap_reg_range(HDMI_RX_AUD_CTRL, HDMI_RX_AUD_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) regmap_reg_range(HDMI_RX_AUD_PLL_CTRL, HDMI_RX_AUD_PLL_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) regmap_reg_range(HDMI_RX_AUD_CLK_CTRL, HDMI_RX_AUD_CLK_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) regmap_reg_range(HDMI_RX_AUD_FIFO_CTRL, HDMI_RX_AUD_FIFO_TH),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) regmap_reg_range(HDMI_RX_AUD_CHEXTR_CTRL, HDMI_RX_AUD_PAO_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) regmap_reg_range(HDMI_RX_AUD_FIFO_STS, HDMI_RX_AUD_FIFO_STS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) regmap_reg_range(HDMI_RX_AUDPLL_GEN_CTS, HDMI_RX_AUDPLL_GEN_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) regmap_reg_range(HDMI_RX_PDEC_CTRL, HDMI_RX_PDEC_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) regmap_reg_range(HDMI_RX_PDEC_AUDIODET_CTRL, HDMI_RX_PDEC_AUDIODET_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) regmap_reg_range(HDMI_RX_PDEC_ERR_FILTER, HDMI_RX_PDEC_ASP_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) regmap_reg_range(HDMI_RX_PDEC_STS, HDMI_RX_PDEC_STS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) regmap_reg_range(HDMI_RX_PDEC_GCP_AVMUTE, HDMI_RX_PDEC_GCP_AVMUTE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) regmap_reg_range(HDMI_RX_PDEC_ACR_CTS, HDMI_RX_PDEC_ACR_N),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) regmap_reg_range(HDMI_RX_PDEC_AIF_CTRL, HDMI_RX_PDEC_AIF_PB0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) regmap_reg_range(HDMI_RX_PDEC_AVI_PB, HDMI_RX_PDEC_AVI_PB),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) regmap_reg_range(HDMI_RX_HDMI20_CONTROL, HDMI_RX_CHLOCK_CONFIG),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) regmap_reg_range(HDMI_RX_SCDC_REGS1, HDMI_RX_SCDC_REGS2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) regmap_reg_range(HDMI_RX_SCDC_WRDATA0, HDMI_RX_SCDC_WRDATA0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) regmap_reg_range(HDMI_RX_PDEC_ISTS, HDMI_RX_PDEC_IEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) regmap_reg_range(HDMI_RX_AUD_FIFO_ISTS, HDMI_RX_AUD_FIFO_IEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) regmap_reg_range(HDMI_RX_MD_ISTS, HDMI_RX_MD_IEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) regmap_reg_range(HDMI_RX_HDMI_ISTS, HDMI_RX_HDMI_IEN),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) regmap_reg_range(HDMI_RX_DMI_DISABLE_IF, HDMI_RX_DMI_DISABLE_IF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const struct regmap_access_table rk628_hdmirx_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .yes_ranges = rk628_hdmirx_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .n_yes_ranges = ARRAY_SIZE(rk628_hdmirx_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const struct regmap_range rk628_key_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) regmap_reg_range(EDID_BASE, EDID_BASE + 0x400),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static const struct regmap_access_table rk628_key_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) .yes_ranges = rk628_key_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) .n_yes_ranges = ARRAY_SIZE(rk628_key_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct regmap_range rk628_combtxphy_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) regmap_reg_range(COMBTXPHY_BASE, COMBTXPHY_CON10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const struct regmap_access_table rk628_combtxphy_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) .yes_ranges = rk628_combtxphy_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) .n_yes_ranges = ARRAY_SIZE(rk628_combtxphy_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct regmap_range rk628_csi_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) regmap_reg_range(CSITX_CONFIG_DONE, CSITX_CSITX_VERSION),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) regmap_reg_range(CSITX_SYS_CTRL0_IMD, CSITX_TIMING_HPW_PADDING_NUM),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) regmap_reg_range(CSITX_VOP_PATH_CTRL, CSITX_VOP_PATH_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) regmap_reg_range(CSITX_VOP_PATH_PKT_CTRL, CSITX_VOP_PATH_PKT_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) regmap_reg_range(CSITX_CSITX_STATUS0, CSITX_LPDT_DATA_IMD),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) regmap_reg_range(CSITX_DPHY_CTRL, CSITX_DPHY_CTRL),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct regmap_access_table rk628_csi_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) .yes_ranges = rk628_csi_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) .n_yes_ranges = ARRAY_SIZE(rk628_csi_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static const struct regmap_range rk628_dsi0_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) regmap_reg_range(DSI0_BASE, DSI0_BASE + DSI_MAX_REGISTER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct regmap_access_table rk628_dsi0_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .yes_ranges = rk628_dsi0_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) .n_yes_ranges = ARRAY_SIZE(rk628_dsi0_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct regmap_range rk628_dsi1_readable_ranges[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) regmap_reg_range(DSI1_BASE, DSI1_BASE + DSI_MAX_REGISTER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const struct regmap_access_table rk628_dsi1_readable_table = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) .yes_ranges = rk628_dsi1_readable_ranges,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) .n_yes_ranges = ARRAY_SIZE(rk628_dsi1_readable_ranges),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static const struct regmap_config rk628_regmap_config[RK628_DEV_MAX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) [RK628_DEV_GRF] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .name = "grf",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .max_register = GRF_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .reg_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) [RK628_DEV_CRU] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) .name = "cru",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) .max_register = CRU_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) .reg_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) .val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) .rd_table = &rk628_cru_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) [RK628_DEV_COMBRXPHY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) .name = "combrxphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) .max_register = COMBRX_REG(0x6790),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) .reg_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) .val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) .rd_table = &rk628_combrxphy_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) [RK628_DEV_DSI0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) .name = "dsi0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .max_register = DSI0_BASE + DSI_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) .reg_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) .val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) .rd_table = &rk628_dsi0_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) [RK628_DEV_DSI1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) .name = "dsi1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .max_register = DSI1_BASE + DSI_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .reg_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .rd_table = &rk628_dsi1_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) [RK628_DEV_HDMIRX] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .name = "hdmirx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .max_register = HDMI_RX_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .reg_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .rd_table = &rk628_hdmirx_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) [RK628_DEV_ADAPTER] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .name = "adapter",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .max_register = KEY_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .reg_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .rd_table = &rk628_key_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) [RK628_DEV_COMBTXPHY] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .name = "combtxphy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .max_register = COMBTXPHY_CON10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .reg_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .rd_table = &rk628_combtxphy_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) [RK628_DEV_CSI] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) .name = "csi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) .reg_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) .reg_stride = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .max_register = CSI_MAX_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .reg_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .val_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .rd_table = &rk628_csi_readable_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct rk628 *rk628_i2c_register(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct rk628 *rk628;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) rk628 = devm_kzalloc(dev, sizeof(*rk628), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) if (!rk628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) rk628->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) rk628->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) for (i = 0; i < RK628_DEV_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) const struct regmap_config *config = &rk628_regmap_config[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (!config->name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) rk628->regmap[i] = devm_regmap_init_i2c(client, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) if (IS_ERR(rk628->regmap[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ret = PTR_ERR(rk628->regmap[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev_err(dev, "failed to allocate register map %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) i, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return rk628;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) EXPORT_SYMBOL(rk628_i2c_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static void calc_dsp_frm_hst_vst(const struct videomode *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) const struct videomode *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 *dsp_frame_hst, u32 *dsp_frame_vst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) u32 bp_in, bp_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 v_scale_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u64 t_frm_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u64 t_bp_in, t_bp_out, t_delta, tin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 src_pixclock, dst_pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 dsp_htotal, src_htotal, src_vtotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) src_pixclock = div_u64(1000000000000llu, src->pixelclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dst_pixclock = div_u64(1000000000000llu, dst->pixelclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) src_htotal = src->hsync_len + src->hback_porch + src->hactive +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) src->hfront_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) src_vtotal = src->vsync_len + src->vback_porch + src->vactive +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) src->vfront_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dsp_htotal = dst->hsync_len + dst->hback_porch + dst->hactive +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) dst->hfront_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) bp_in = (src->vback_porch + src->vsync_len) * src_htotal +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) src->hsync_len + src->hback_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) bp_out = (dst->vback_porch + dst->vsync_len) * dsp_htotal +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dst->hsync_len + dst->hback_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) t_bp_in = bp_in * src_pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) t_bp_out = bp_out * dst_pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) tin = src_vtotal * src_htotal * src_pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) v_scale_ratio = src->vactive / dst->vactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (v_scale_ratio <= 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) t_delta = 5 * src_htotal * src_pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) t_delta = 12 * src_htotal * src_pixclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (t_bp_in + t_delta > t_bp_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) t_frm_st = (t_bp_in + t_delta - t_bp_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) t_frm_st = tin - (t_bp_out - (t_bp_in + t_delta));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) do_div(t_frm_st, src_pixclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) *dsp_frame_hst = do_div(t_frm_st, src_htotal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) *dsp_frame_vst = t_frm_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static void rk628_post_process_scaler_init(struct rk628 *rk628,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) const struct videomode *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) const struct videomode *dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u32 dsp_frame_hst, dsp_frame_vst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 scl_hor_mode, scl_ver_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 scl_v_factor, scl_h_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 dsp_htotal, dsp_hs_end, dsp_hact_st, dsp_hact_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 dsp_vtotal, dsp_vs_end, dsp_vact_st, dsp_vact_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 dsp_hbor_end, dsp_hbor_st, dsp_vbor_end, dsp_vbor_st;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u16 bor_right = 0, bor_left = 0, bor_up = 0, bor_down = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u8 hor_down_mode = 0, ver_down_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dsp_htotal = dst->hsync_len + dst->hback_porch + dst->hactive +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) dst->hfront_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dsp_vtotal = dst->vsync_len + dst->vback_porch + dst->vactive +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) dst->vfront_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dsp_hs_end = dst->hsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) dsp_vs_end = dst->vsync_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dsp_hbor_end = dst->hsync_len + dst->hback_porch + dst->hactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) dsp_hbor_st = dst->hsync_len + dst->hback_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dsp_vbor_end = dst->vsync_len + dst->vback_porch + dst->vactive;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dsp_vbor_st = dst->vsync_len + dst->vback_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dsp_hact_st = dsp_hbor_st + bor_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dsp_hact_end = dsp_hbor_end - bor_right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dsp_vact_st = dsp_vbor_st + bor_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) dsp_vact_end = dsp_vbor_end - bor_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) calc_dsp_frm_hst_vst(src, dst, &dsp_frame_hst, &dsp_frame_vst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_dbg(rk628->dev, "dsp_frame_vst=%d, dsp_frame_hst=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dsp_frame_vst, dsp_frame_hst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (src->hactive > dst->hactive) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) scl_hor_mode = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (hor_down_mode == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if ((src->hactive - 1) / (dst->hactive - 1) > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) scl_h_factor = ((src->hactive - 1) << 14) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) (dst->hactive - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) scl_h_factor = ((src->hactive - 2) << 14) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) (dst->hactive - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) scl_h_factor = (dst->hactive << 16) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) (src->hactive - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev_dbg(rk628->dev, "horizontal scale down\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) } else if (src->hactive == dst->hactive) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) scl_hor_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) scl_h_factor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev_dbg(rk628->dev, "horizontal no scale\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) scl_hor_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) scl_h_factor = ((src->hactive - 1) << 16) / (dst->hactive - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dev_dbg(rk628->dev, "horizontal scale up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (src->vactive > dst->vactive) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) scl_ver_mode = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (ver_down_mode == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if ((src->vactive - 1) / (dst->vactive - 1) > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) scl_v_factor = ((src->vactive - 1) << 14) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) (dst->vactive - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) scl_v_factor = ((src->vactive - 2) << 14) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) (dst->vactive - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) scl_v_factor = (dst->vactive << 16) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) (src->vactive - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev_dbg(rk628->dev, "vertical scale down\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) } else if (src->vactive == dst->vactive) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) scl_ver_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) scl_v_factor = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev_dbg(rk628->dev, "vertical no scale\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) scl_ver_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) scl_v_factor = ((src->vactive - 1) << 16) / (dst->vactive - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) dev_dbg(rk628->dev, "vertical scale up\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) rk628_i2c_update_bits(rk628, GRF_RGB_DEC_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) SW_HRES_MASK, SW_HRES(src->hactive));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) rk628_i2c_write(rk628, GRF_SCALER_CON0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) SCL_VER_DOWN_MODE(ver_down_mode) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) SCL_HOR_DOWN_MODE(hor_down_mode) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) SCL_VER_MODE(scl_ver_mode) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) SCL_HOR_MODE(scl_hor_mode) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) SCL_EN(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) rk628_i2c_write(rk628, GRF_SCALER_CON1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) SCL_V_FACTOR(scl_v_factor) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) SCL_H_FACTOR(scl_h_factor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) rk628_i2c_write(rk628, GRF_SCALER_CON2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DSP_FRAME_VST(dsp_frame_vst) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) DSP_FRAME_HST(dsp_frame_hst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) rk628_i2c_write(rk628, GRF_SCALER_CON3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DSP_HS_END(dsp_hs_end) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) DSP_HTOTAL(dsp_htotal));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) rk628_i2c_write(rk628, GRF_SCALER_CON4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) DSP_HACT_END(dsp_hact_end) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) DSP_HACT_ST(dsp_hact_st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) rk628_i2c_write(rk628, GRF_SCALER_CON5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) DSP_VS_END(dsp_vs_end) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) DSP_VTOTAL(dsp_vtotal));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) rk628_i2c_write(rk628, GRF_SCALER_CON6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) DSP_VACT_END(dsp_vact_end) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) DSP_VACT_ST(dsp_vact_st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) rk628_i2c_write(rk628, GRF_SCALER_CON7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) DSP_HBOR_END(dsp_hbor_end) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) DSP_HBOR_ST(dsp_hbor_st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) rk628_i2c_write(rk628, GRF_SCALER_CON8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) DSP_VBOR_END(dsp_vbor_end) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) DSP_VBOR_ST(dsp_vbor_st));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) void rk628_post_process_en(struct rk628 *rk628,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct videomode *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct videomode *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u64 *dst_pclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u64 dst_rate, src_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u64 dst_htotal, src_htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) src_rate = src->pixelclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dst_htotal = dst->hactive + dst->hfront_porch + dst->hsync_len + dst->hback_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dst_rate = src_rate * dst->vactive * dst_htotal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) src_htotal = src->hactive + src->hfront_porch + src->hsync_len + src->hback_porch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) do_div(dst_rate, (src->vactive * src_htotal));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dst->pixelclock = dst_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) *dst_pclk = dst->pixelclock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_info(rk628->dev, "src %dx%d clock:%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) src->hactive, src->vactive, src->pixelclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dev_info(rk628->dev, "dst %dx%d clock:%lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) dst->hactive, dst->vactive, dst->pixelclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) dst->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) rk628_control_assert(rk628, RGU_DECODER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) rk628_control_deassert(rk628, RGU_DECODER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) rk628_clk_set_rate(rk628, CGU_CLK_RX_READ, src->pixelclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) rk628_control_assert(rk628, RGU_CLK_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) rk628_control_deassert(rk628, RGU_CLK_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) rk628_clk_set_rate(rk628, CGU_SCLK_VOP, dst->pixelclock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) rk628_control_assert(rk628, RGU_VOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) rk628_control_deassert(rk628, RGU_VOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) rk628_post_process_scaler_init(rk628, src, dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) EXPORT_SYMBOL(rk628_post_process_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) MODULE_AUTHOR("Shunqing Chen <csq@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) MODULE_DESCRIPTION("Rockchip RK628 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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