Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * pisp_dmy driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #include <linux/of_gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define DRIVER_VERSION				KERNEL_VERSION(0, 0x01, 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define V4L2_CID_DIGITAL_GAIN			V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define PISP_DMY_XVCLK_FREQ			24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define OF_CAMERA_PINCTRL_STATE_DEFAULT		"rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define OF_CAMERA_PINCTRL_STATE_SLEEP		"rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define OF_CAMERA_MODULE_REGULATORS		"rockchip,regulator-names"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define OF_CAMERA_MODULE_REGULATOR_VOLTAGES	"rockchip,regulator-voltages"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PISP_DMY_NAME				"pisp_dmy"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) struct pisp_dmy_gpio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	int pltfrm_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	const char *label;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	enum of_gpio_flags active_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) struct pisp_dmy_regulator {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	struct regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u32 min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u32 max_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) struct pisp_dmy_regulators {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u32 cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct pisp_dmy_regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) struct pisp_dmy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	struct i2c_client	*client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct clk		*xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct gpio_desc	*rst_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	struct gpio_desc	*rst2_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	struct gpio_desc	*pd_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct gpio_desc	*pd2_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct gpio_desc	*pwd_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct gpio_desc	*pwd2_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	struct pinctrl		*pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	struct pinctrl_state	*pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	struct pinctrl_state	*pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	struct v4l2_subdev	subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	struct media_pad	pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	struct mutex		mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	bool			power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct pisp_dmy_regulators regulators;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	u32			module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	const char		*module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	const char		*module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	const char		*len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define to_pisp_dmy(sd) container_of(sd, struct pisp_dmy, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) static int __pisp_dmy_power_on(struct pisp_dmy *pisp_dmy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	struct pisp_dmy_regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct device *dev = &pisp_dmy->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	if (!IS_ERR_OR_NULL(pisp_dmy->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 		ret = pinctrl_select_state(pisp_dmy->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 					   pisp_dmy->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			dev_err(dev, "could not set pins. ret=%d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	ret = clk_prepare_enable(pisp_dmy->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 		dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	if (pisp_dmy->regulators.regulator) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 		for (i = 0; i < pisp_dmy->regulators.cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			regulator = pisp_dmy->regulators.regulator + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			if (IS_ERR(regulator->regulator))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			regulator_set_voltage(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 				regulator->regulator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 				regulator->min_uV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 				regulator->max_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 			if (regulator_enable(regulator->regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 				dev_err(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 					"regulator_enable failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 				goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	usleep_range(3000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	if (!IS_ERR(pisp_dmy->pwd_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 		gpiod_direction_output(pisp_dmy->pwd_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 		usleep_range(3000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	if (!IS_ERR(pisp_dmy->pwd2_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 		gpiod_direction_output(pisp_dmy->pwd2_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 		usleep_range(3000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	if (!IS_ERR(pisp_dmy->pd_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 		gpiod_direction_output(pisp_dmy->pd_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		usleep_range(1500, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (!IS_ERR(pisp_dmy->pd2_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		gpiod_direction_output(pisp_dmy->pd2_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 		usleep_range(1500, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	if (!IS_ERR(pisp_dmy->rst_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 		gpiod_direction_output(pisp_dmy->rst_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 		usleep_range(1500, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		gpiod_direction_output(pisp_dmy->rst_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (!IS_ERR(pisp_dmy->rst2_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		gpiod_direction_output(pisp_dmy->rst2_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 		usleep_range(1500, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		gpiod_direction_output(pisp_dmy->rst2_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	clk_disable_unprepare(pisp_dmy->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static void __pisp_dmy_power_off(struct pisp_dmy *pisp_dmy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	struct pisp_dmy_regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	struct device *dev = &pisp_dmy->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	if (!IS_ERR(pisp_dmy->pd_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		gpiod_direction_output(pisp_dmy->pd_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	if (!IS_ERR(pisp_dmy->pd2_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		gpiod_direction_output(pisp_dmy->pd2_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	clk_disable_unprepare(pisp_dmy->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	if (!IS_ERR(pisp_dmy->rst_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 		gpiod_direction_output(pisp_dmy->rst_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (!IS_ERR(pisp_dmy->rst2_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		gpiod_direction_output(pisp_dmy->rst2_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	if (!IS_ERR(pisp_dmy->pwd_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 		gpiod_direction_output(pisp_dmy->pwd_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	if (!IS_ERR(pisp_dmy->pwd2_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 		gpiod_direction_output(pisp_dmy->pwd2_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	if (!IS_ERR_OR_NULL(pisp_dmy->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		ret = pinctrl_select_state(pisp_dmy->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 					   pisp_dmy->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 			dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (pisp_dmy->regulators.regulator) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		for (i = 0; i < pisp_dmy->regulators.cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			regulator = pisp_dmy->regulators.regulator + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			if (IS_ERR(regulator->regulator))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 				continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			regulator_disable(regulator->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int pisp_dmy_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct pisp_dmy *pisp_dmy = to_pisp_dmy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	mutex_lock(&pisp_dmy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	/* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (pisp_dmy->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		ret = __pisp_dmy_power_on(pisp_dmy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 			goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 		pisp_dmy->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 		__pisp_dmy_power_off(pisp_dmy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		pisp_dmy->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	mutex_unlock(&pisp_dmy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void pisp_dmy_get_module_inf(struct pisp_dmy *pisp_dmy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 				    struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	strlcpy(inf->base.sensor, PISP_DMY_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	strlcpy(inf->base.module, pisp_dmy->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	strlcpy(inf->base.lens, pisp_dmy->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static long pisp_dmy_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	struct pisp_dmy *pisp_dmy = to_pisp_dmy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		pisp_dmy_get_module_inf(pisp_dmy, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static long pisp_dmy_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 				    unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 		if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 			ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 		ret = pisp_dmy_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 		if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 			if (copy_to_user(up, inf, sizeof(*inf))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 				kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 				return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 		cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 		if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 			ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 		if (copy_from_user(cfg, up, sizeof(*cfg))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 			kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 			return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		ret = pisp_dmy_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 		kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 		ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int pisp_dmy_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	struct pisp_dmy *pisp_dmy = to_pisp_dmy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	return __pisp_dmy_power_on(pisp_dmy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int pisp_dmy_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	struct pisp_dmy *pisp_dmy = to_pisp_dmy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	__pisp_dmy_power_off(pisp_dmy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static const struct dev_pm_ops pisp_dmy_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	SET_RUNTIME_PM_OPS(pisp_dmy_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			   pisp_dmy_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) static const struct v4l2_subdev_core_ops pisp_dmy_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	.s_power = pisp_dmy_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	.ioctl = pisp_dmy_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	.compat_ioctl32 = pisp_dmy_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static const struct v4l2_subdev_ops pisp_dmy_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 	.core = &pisp_dmy_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int pisp_dmy_analyze_dts(struct pisp_dmy *pisp_dmy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 	int elem_size, elem_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	const char *str = "";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	struct property *prop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	struct pisp_dmy_regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	struct device *dev = &pisp_dmy->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	struct device_node *np = of_node_get(dev->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 	pisp_dmy->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	if (IS_ERR(pisp_dmy->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 		dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	ret = clk_set_rate(pisp_dmy->xvclk, PISP_DMY_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 		dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	if (clk_get_rate(pisp_dmy->xvclk) != PISP_DMY_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 		dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 	pisp_dmy->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	if (!IS_ERR(pisp_dmy->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		pisp_dmy->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 			pinctrl_lookup_state(pisp_dmy->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 					     OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 		if (IS_ERR(pisp_dmy->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 			dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 		pisp_dmy->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 			pinctrl_lookup_state(pisp_dmy->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 					     OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		if (IS_ERR(pisp_dmy->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 			dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 		dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	elem_size = of_property_count_elems_of_size(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 		np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		OF_CAMERA_MODULE_REGULATOR_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 		sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	prop = of_find_property(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 		np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 		OF_CAMERA_MODULE_REGULATORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	if (elem_size > 0 && !IS_ERR_OR_NULL(prop)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 		pisp_dmy->regulators.regulator =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 			devm_kzalloc(&pisp_dmy->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 				     elem_size * sizeof(struct pisp_dmy_regulator),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 				     GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		if (!pisp_dmy->regulators.regulator) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 			dev_err(dev, "could not malloc pisp_dmy_regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 		pisp_dmy->regulators.cnt = elem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 		str = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 		elem_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) 		regulator = pisp_dmy->regulators.regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 		do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 			str = of_prop_next_string(prop, str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 			if (!str) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 				dev_err(dev, "%s is not match %s in dts\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 					OF_CAMERA_MODULE_REGULATORS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 					OF_CAMERA_MODULE_REGULATOR_VOLTAGES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 				break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 			}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 			regulator->regulator =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 				devm_regulator_get_optional(dev, str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 			if (IS_ERR(regulator->regulator))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 				dev_err(dev, "devm_regulator_get %s failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 					str);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 			of_property_read_u32_index(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 				np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 				OF_CAMERA_MODULE_REGULATOR_VOLTAGES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 				elem_index++,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 				&regulator->min_uV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 			regulator->max_uV = regulator->min_uV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 			regulator++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 		} while (--elem_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 	pisp_dmy->pd_gpio = devm_gpiod_get(dev, "pd", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	if (IS_ERR(pisp_dmy->pd_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 		dev_warn(dev, "can not find pd-gpios, error %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 			 PTR_ERR(pisp_dmy->pd_gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 	pisp_dmy->pd2_gpio = devm_gpiod_get(dev, "pd2", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 	if (IS_ERR(pisp_dmy->pd2_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		dev_warn(dev, "can not find pd2-gpios, error %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 			 PTR_ERR(pisp_dmy->pd2_gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	pisp_dmy->rst_gpio = devm_gpiod_get(dev, "rst", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 	if (IS_ERR(pisp_dmy->rst_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 		dev_warn(dev, "can not find rst-gpios, error %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 			 PTR_ERR(pisp_dmy->rst_gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	pisp_dmy->rst2_gpio = devm_gpiod_get(dev, "rst2", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	if (IS_ERR(pisp_dmy->rst2_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 		dev_warn(dev, "can not find rst2-gpios, error %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 			 PTR_ERR(pisp_dmy->rst2_gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	pisp_dmy->pwd_gpio = devm_gpiod_get(dev, "pwd", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	if (IS_ERR(pisp_dmy->pwd_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		dev_warn(dev, "can not find pwd-gpios, error %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 			 PTR_ERR(pisp_dmy->pwd_gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	pisp_dmy->pwd2_gpio = devm_gpiod_get(dev, "pwd2", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 	if (IS_ERR(pisp_dmy->pwd2_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 		dev_warn(dev, "can not find pwd2-gpios, error %ld\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 			 PTR_ERR(pisp_dmy->pwd2_gpio));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int pisp_dmy_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 			const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	struct pisp_dmy *pisp_dmy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 		 DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 		 (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 		 DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 	pisp_dmy = devm_kzalloc(dev, sizeof(*pisp_dmy), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	if (!pisp_dmy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 	ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 				   &pisp_dmy->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 				       &pisp_dmy->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 				       &pisp_dmy->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 				       &pisp_dmy->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 		dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	pisp_dmy->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 	ret = pisp_dmy_analyze_dts(pisp_dmy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 		dev_err(dev, "Failed to analyze dts\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	mutex_init(&pisp_dmy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	sd = &pisp_dmy->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 	v4l2_i2c_subdev_init(sd, client, &pisp_dmy_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	__pisp_dmy_power_on(pisp_dmy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static int pisp_dmy_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	struct pisp_dmy *pisp_dmy = to_pisp_dmy(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 	mutex_destroy(&pisp_dmy->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 		__pisp_dmy_power_off(pisp_dmy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) static const struct of_device_id pisp_dmy_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	{ .compatible = "pisp_dmy" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) MODULE_DEVICE_TABLE(of, pisp_dmy_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const struct i2c_device_id pisp_dmy_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	{ "pisp_dmy", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 	{ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) static struct i2c_driver pisp_dmy_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 		.name = PISP_DMY_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 		.pm = &pisp_dmy_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 		.of_match_table = of_match_ptr(pisp_dmy_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	.probe		= &pisp_dmy_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	.remove		= &pisp_dmy_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	.id_table	= pisp_dmy_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 	return i2c_add_driver(&pisp_dmy_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 	i2c_del_driver(&pisp_dmy_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) MODULE_DESCRIPTION("preisp dummy sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) MODULE_LICENSE("GPL v2");