^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ov9750 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X03 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X04 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X05 add function g_mbus_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OV9750_LINK_FREQ_400MHZ 400000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OV9750_PIXEL_RATE (OV9750_LINK_FREQ_400MHZ * 2 * 2 / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OV9750_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CHIP_ID 0x9750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OV9750_REG_CHIP_ID 0x300B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OV9750_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OV9750_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OV9750_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OV9750_REG_EXPOSURE 0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OV9750_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OV9750_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OV9750_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OV9750_REG_GAIN_H 0x3508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OV9750_REG_GAIN_L 0x3509
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OV9750_GAIN_H_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OV9750_GAIN_L_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OV9750_GAIN_MIN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OV9750_GAIN_MAX 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OV9750_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OV9750_GAIN_DEFAULT 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OV9750_REG_TEST_PATTERN 0x5e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OV9750_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OV9750_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OV9750_REG_VTS 0x380e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define REG_DELAY 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OV9750_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OV9750_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OV9750_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OV9750_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OV9750_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OV9750_NAME "ov9750"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const char * const ov9750_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OV9750_NUM_SUPPLIES ARRAY_SIZE(ov9750_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct ov9750_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct ov9750 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct regulator_bulk_data supplies[OV9750_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) const struct ov9750_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define to_ov9750(sd) container_of(sd, struct ov9750, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static const struct regval ov9750_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {REG_DELAY, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) {REG_DELAY, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {0x0300, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {0x0302, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) {0x0303, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {0x0304, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0x0305, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x0306, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x030a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0x030b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x030d, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x030e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x030f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x0312, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x031e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x3000, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x3002, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x3005, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x3011, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x3016, 0x53},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x3018, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x301a, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x301b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x301c, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x301d, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x301e, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x3022, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x3031, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x3032, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x303c, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x303e, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x3040, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x3041, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x3042, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x3104, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x3106, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x3107, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x3500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x3501, 0x3d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x3502, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x3503, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x3504, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x3505, 0x83},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x3508, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3509, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x3600, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x3601, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x3602, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3610, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3611, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3612, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3613, 0x5a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3614, 0x91},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3615, 0x79},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3617, 0x57},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3621, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3622, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3623, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3625, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3633, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3634, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3635, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3636, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3650, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3652, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3654, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x3653, 0x34},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3655, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3656, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3657, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x365a, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x365b, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x365e, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x365f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3668, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x366a, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x366d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x366e, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3702, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3703, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3704, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3705, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3706, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3709, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x370a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x370b, 0x7d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3714, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x371a, 0x5e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3730, 0x82},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3733, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x373e, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3755, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3758, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x375b, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x3772, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3773, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3774, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3775, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3776, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x37a8, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x37b5, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x37c2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x37c5, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x37c7, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x37c8, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x37d1, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3803, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3804, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3805, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x3806, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x3807, 0xcb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3808, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3809, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x380a, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x380b, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x380c, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x380d, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x380e, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x380f, 0xdc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3810, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3811, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x3812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3813, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3814, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3815, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x3816, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3817, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3818, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x3819, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x3820, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3821, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3826, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x3827, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x382a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x382b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3836, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x3838, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x3861, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x3862, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x3863, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x3b00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x3c00, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x3c01, 0xab},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x3c02, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x3c03, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x3c04, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x3c05, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x3c06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x3c07, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3c0c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x3c0d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x3c0e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3c0f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3c40, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x3c41, 0xa3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x3c43, 0x7d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x3c56, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x3c80, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x3c82, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x3c83, 0x61},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x3d85, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x3f08, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3f0a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x3f0b, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x4000, 0xcd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x4003, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x4009, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x4010, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x4011, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x4017, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x4040, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x4041, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x4303, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x4307, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x4500, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x4502, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x4503, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x4508, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x450b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x450c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x4600, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x4601, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x4700, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x4704, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x4705, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x4837, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x484a, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x5000, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x5001, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x5002, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x5004, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x5006, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x5007, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x5008, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x5009, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x502a, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x5901, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x5a01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x5a03, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x5a04, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x5a05, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x5a06, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x5a07, 0xb0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x5a08, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x5e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x5e10, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x300f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x3733, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x3610, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x3611, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x3635, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x3636, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x3620, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x3614, 0x96},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x481f, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x3788, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x3789, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x378a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x378b, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x3799, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * max_framerate 60fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * mipi_datarate per lane 800Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) static const struct regval ov9750_1280x960_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static const struct ov9750_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .height = 960,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) .exp_def = 0x03D0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .hts_def = 0x0654,//0x32A*2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .vts_def = 0x03DC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .reg_list = ov9750_1280x960_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) OV9750_LINK_FREQ_400MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static const char * const ov9750_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static int ov9750_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int ov9750_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (unlikely(regs[i].addr == REG_DELAY))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) usleep_range(regs[i].val, regs[i].val * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ret = ov9750_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) OV9750_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int ov9750_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int ov9750_get_reso_dist(const struct ov9750_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct ov9750_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ov9750_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dist = ov9750_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static int ov9750_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct ov9750 *ov9750 = to_ov9750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) const struct ov9750_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) mutex_lock(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mode = ov9750_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) mutex_unlock(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ov9750->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) __v4l2_ctrl_modify_range(ov9750->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) __v4l2_ctrl_modify_range(ov9750->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) OV9750_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mutex_unlock(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int ov9750_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct ov9750 *ov9750 = to_ov9750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) const struct ov9750_mode *mode = ov9750->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mutex_lock(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) mutex_unlock(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) mutex_unlock(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int ov9750_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int ov9750_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int ov9750_enable_test_pattern(struct ov9750 *ov9750, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) val = ((pattern - 1) < 2) | OV9750_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) val = OV9750_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return ov9750_write_reg(ov9750->client, OV9750_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) OV9750_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static int ov9750_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct ov9750 *ov9750 = to_ov9750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) const struct ov9750_mode *mode = ov9750->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) mutex_lock(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) mutex_unlock(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static void ov9750_get_module_inf(struct ov9750 *ov9750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) strlcpy(inf->base.sensor, OV9750_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) strlcpy(inf->base.module, ov9750->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) strlcpy(inf->base.lens, ov9750->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static long ov9750_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct ov9750 *ov9750 = to_ov9750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ov9750_get_module_inf(ov9750, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ret = ov9750_write_reg(ov9750->client, OV9750_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) OV9750_REG_VALUE_08BIT, OV9750_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ret = ov9750_write_reg(ov9750->client, OV9750_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) OV9750_REG_VALUE_08BIT, OV9750_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static long ov9750_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ret = ov9750_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = ov9750_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static int __ov9750_start_stream(struct ov9750 *ov9750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ret = ov9750_write_array(ov9750->client, ov9750->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) mutex_unlock(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) ret = v4l2_ctrl_handler_setup(&ov9750->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) mutex_lock(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return ov9750_write_reg(ov9750->client, OV9750_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) OV9750_REG_VALUE_08BIT, OV9750_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static int __ov9750_stop_stream(struct ov9750 *ov9750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return ov9750_write_reg(ov9750->client, OV9750_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) OV9750_REG_VALUE_08BIT, OV9750_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static int ov9750_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct ov9750 *ov9750 = to_ov9750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) struct i2c_client *client = ov9750->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) mutex_lock(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (on == ov9750->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ret = __ov9750_start_stream(ov9750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) __ov9750_stop_stream(ov9750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ov9750->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) mutex_unlock(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static int ov9750_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct ov9750 *ov9750 = to_ov9750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct i2c_client *client = ov9750->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mutex_lock(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (ov9750->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) ret = ov9750_write_array(ov9750->client, ov9750_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ov9750->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) ov9750->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) mutex_unlock(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static inline u32 ov9750_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return DIV_ROUND_UP(cycles, OV9750_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static int __ov9750_power_on(struct ov9750 *ov9750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct device *dev = &ov9750->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (!IS_ERR_OR_NULL(ov9750->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ret = pinctrl_select_state(ov9750->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ov9750->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ret = clk_set_rate(ov9750->xvclk, OV9750_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (clk_get_rate(ov9750->xvclk) != OV9750_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ret = clk_prepare_enable(ov9750->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (!IS_ERR(ov9750->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) gpiod_set_value_cansleep(ov9750->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ret = regulator_bulk_enable(OV9750_NUM_SUPPLIES, ov9750->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (!IS_ERR(ov9750->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) gpiod_set_value_cansleep(ov9750->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (!IS_ERR(ov9750->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) gpiod_set_value_cansleep(ov9750->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) delay_us = ov9750_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) clk_disable_unprepare(ov9750->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) static void __ov9750_power_off(struct ov9750 *ov9750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (!IS_ERR(ov9750->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) gpiod_set_value_cansleep(ov9750->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) clk_disable_unprepare(ov9750->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (!IS_ERR(ov9750->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) gpiod_set_value_cansleep(ov9750->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (!IS_ERR_OR_NULL(ov9750->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = pinctrl_select_state(ov9750->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ov9750->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) dev_dbg(&ov9750->client->dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) regulator_bulk_disable(OV9750_NUM_SUPPLIES, ov9750->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) static int ov9750_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) struct ov9750 *ov9750 = to_ov9750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return __ov9750_power_on(ov9750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static int ov9750_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct ov9750 *ov9750 = to_ov9750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) __ov9750_power_off(ov9750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) static int ov9750_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) struct ov9750 *ov9750 = to_ov9750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) const struct ov9750_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) mutex_lock(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) mutex_unlock(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) static int ov9750_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static int ov9750_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) val = 1 << (OV9750_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) config->type = V4L2_MBUS_CSI2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static const struct dev_pm_ops ov9750_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) SET_RUNTIME_PM_OPS(ov9750_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ov9750_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static const struct v4l2_subdev_internal_ops ov9750_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) .open = ov9750_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static const struct v4l2_subdev_core_ops ov9750_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) .s_power = ov9750_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) .ioctl = ov9750_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) .compat_ioctl32 = ov9750_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static const struct v4l2_subdev_video_ops ov9750_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .s_stream = ov9750_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .g_frame_interval = ov9750_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .g_mbus_config = ov9750_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static const struct v4l2_subdev_pad_ops ov9750_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .enum_mbus_code = ov9750_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .enum_frame_size = ov9750_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) .enum_frame_interval = ov9750_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .get_fmt = ov9750_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) .set_fmt = ov9750_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static const struct v4l2_subdev_ops ov9750_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .core = &ov9750_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .video = &ov9750_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .pad = &ov9750_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) static int ov9750_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) struct ov9750 *ov9750 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) struct ov9750, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct i2c_client *client = ov9750->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) max = ov9750->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) __v4l2_ctrl_modify_range(ov9750->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ov9750->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ov9750->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ov9750->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ret = ov9750_write_reg(ov9750->client, OV9750_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) OV9750_REG_VALUE_24BIT, ctrl->val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ret = ov9750_write_reg(ov9750->client, OV9750_REG_GAIN_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) OV9750_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) (ctrl->val >> 8) & OV9750_GAIN_H_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ret |= ov9750_write_reg(ov9750->client, OV9750_REG_GAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) OV9750_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ctrl->val & OV9750_GAIN_L_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ret = ov9750_write_reg(ov9750->client, OV9750_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) OV9750_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ctrl->val + ov9750->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) ret = ov9750_enable_test_pattern(ov9750, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static const struct v4l2_ctrl_ops ov9750_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .s_ctrl = ov9750_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static int ov9750_initialize_controls(struct ov9750 *ov9750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) const struct ov9750_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) handler = &ov9750->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) mode = ov9750->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) handler->lock = &ov9750->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) 0, OV9750_PIXEL_RATE, 1, OV9750_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) ov9750->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) if (ov9750->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) ov9750->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ov9750->vblank = v4l2_ctrl_new_std(handler, &ov9750_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) OV9750_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) ov9750->exposure = v4l2_ctrl_new_std(handler, &ov9750_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) V4L2_CID_EXPOSURE, OV9750_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) exposure_max, OV9750_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ov9750->anal_gain = v4l2_ctrl_new_std(handler, &ov9750_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) V4L2_CID_ANALOGUE_GAIN, OV9750_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) OV9750_GAIN_MAX, OV9750_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) OV9750_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) ov9750->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) &ov9750_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ARRAY_SIZE(ov9750_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) 0, 0, ov9750_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) dev_err(&ov9750->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) ov9750->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static int ov9750_check_sensor_id(struct ov9750 *ov9750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct device *dev = &ov9750->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) ret = ov9750_read_reg(client, OV9750_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) OV9750_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) dev_info(dev, "Detected OV%04x sensor\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static int ov9750_configure_regulators(struct ov9750 *ov9750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) for (i = 0; i < OV9750_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ov9750->supplies[i].supply = ov9750_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return devm_regulator_bulk_get(&ov9750->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) OV9750_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ov9750->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static int ov9750_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct ov9750 *ov9750;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ov9750 = devm_kzalloc(dev, sizeof(*ov9750), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (!ov9750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) &ov9750->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) &ov9750->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) &ov9750->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) &ov9750->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) ov9750->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ov9750->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) ov9750->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (IS_ERR(ov9750->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) ov9750->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (IS_ERR(ov9750->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ov9750->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (IS_ERR(ov9750->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ov9750->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (!IS_ERR(ov9750->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) ov9750->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) pinctrl_lookup_state(ov9750->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (IS_ERR(ov9750->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) ov9750->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) pinctrl_lookup_state(ov9750->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (IS_ERR(ov9750->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) ret = ov9750_configure_regulators(ov9750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) mutex_init(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) sd = &ov9750->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) v4l2_i2c_subdev_init(sd, client, &ov9750_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ret = ov9750_initialize_controls(ov9750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) ret = __ov9750_power_on(ov9750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) ret = ov9750_check_sensor_id(ov9750, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) sd->internal_ops = &ov9750_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ov9750->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ret = media_entity_pads_init(&sd->entity, 1, &ov9750->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (strcmp(ov9750->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) ov9750->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) OV9750_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) __ov9750_power_off(ov9750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) v4l2_ctrl_handler_free(&ov9750->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) mutex_destroy(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) static int ov9750_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) struct ov9750 *ov9750 = to_ov9750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) v4l2_ctrl_handler_free(&ov9750->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) mutex_destroy(&ov9750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) __ov9750_power_off(ov9750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static const struct of_device_id ov9750_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) { .compatible = "ovti,ov9750" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) MODULE_DEVICE_TABLE(of, ov9750_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static const struct i2c_device_id ov9750_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) { "ovti,ov9750", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) static struct i2c_driver ov9750_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) .name = OV9750_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) .pm = &ov9750_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .of_match_table = of_match_ptr(ov9750_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .probe = &ov9750_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .remove = &ov9750_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .id_table = ov9750_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return i2c_add_driver(&ov9750_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) i2c_del_driver(&ov9750_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) MODULE_DESCRIPTION("OmniVision ov9750 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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