^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OmniVision OV96xx Camera Header File
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __DRIVERS_MEDIA_VIDEO_OV9640_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __DRIVERS_MEDIA_VIDEO_OV9640_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define OV9640_GAIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define OV9640_BLUE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define OV9640_RED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define OV9640_VFER 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define OV9640_COM1 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define OV9640_BAVE 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define OV9640_GEAVE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OV9640_RSID 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define OV9640_RAVE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define OV9640_COM2 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define OV9640_PID 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define OV9640_VER 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define OV9640_COM3 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define OV9640_COM4 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define OV9640_COM5 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define OV9640_COM6 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define OV9640_AECH 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OV9640_CLKRC 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OV9640_COM7 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define OV9640_COM8 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OV9640_COM9 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define OV9640_COM10 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* 0x16 - RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OV9640_HSTART 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OV9640_HSTOP 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OV9640_VSTART 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OV9640_VSTOP 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OV9640_PSHFT 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OV9640_MIDH 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OV9640_MIDL 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OV9640_MVFP 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OV9640_LAEC 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OV9640_BOS 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OV9640_GBOS 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OV9640_GROS 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OV9640_ROS 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OV9640_AEW 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OV9640_AEB 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OV9640_VPT 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OV9640_BBIAS 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OV9640_GBBIAS 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /* 0x29 - RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OV9640_EXHCH 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OV9640_EXHCL 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OV9640_RBIAS 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OV9640_ADVFL 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OV9640_ADVFH 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OV9640_YAVE 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OV9640_HSYST 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OV9640_HSYEN 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OV9640_HREF 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OV9640_CHLF 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OV9640_ARBLM 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* 0x35..0x36 - RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OV9640_ADC 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OV9640_ACOM 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OV9640_OFON 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OV9640_TSLB 0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OV9640_COM11 0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OV9640_COM12 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OV9640_COM13 0x3d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OV9640_COM14 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OV9640_EDGE 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OV9640_COM15 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OV9640_COM16 0x41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OV9640_COM17 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* 0x43..0x4e - RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OV9640_MTX1 0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OV9640_MTX2 0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OV9640_MTX3 0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OV9640_MTX4 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OV9640_MTX5 0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OV9640_MTX6 0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OV9640_MTX7 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OV9640_MTX8 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OV9640_MTX9 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OV9640_MTXS 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* 0x59..0x61 - RESERVED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OV9640_LCC1 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OV9640_LCC2 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OV9640_LCC3 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OV9640_LCC4 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OV9640_LCC5 0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OV9640_MANU 0x67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OV9640_MANV 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OV9640_HV 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OV9640_MBD 0x6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OV9640_DBLV 0x6b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OV9640_GSP 0x6c /* ... till 0x7b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define OV9640_GST 0x7c /* ... till 0x8a */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OV9640_CLKRC_DPLL_EN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OV9640_CLKRC_DIRECT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OV9640_CLKRC_DIV(x) ((x) & 0x3f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OV9640_PSHFT_VAL(x) ((x) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OV9640_ACOM_2X_ANALOG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OV9640_ACOM_RSVD 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define OV9640_MVFP_V 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OV9640_MVFP_H 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OV9640_COM1_HREF_NOSKIP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define OV9640_COM1_HREF_2SKIP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define OV9640_COM1_HREF_3SKIP 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define OV9640_COM1_QQFMT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define OV9640_COM2_SSM 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define OV9640_COM3_VP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OV9640_COM4_QQ_VP 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define OV9640_COM4_RSVD 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define OV9640_COM5_SYSCLK 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define OV9640_COM5_LONGEXP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define OV9640_COM6_OPT_BLC 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OV9640_COM6_ADBLC_BIAS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OV9640_COM6_FMT_RST 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define OV9640_COM6_ADBLC_OPTEN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OV9640_COM7_RAW_RGB 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OV9640_COM7_RGB 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define OV9640_COM7_QCIF 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OV9640_COM7_QVGA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define OV9640_COM7_CIF 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OV9640_COM7_VGA 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define OV9640_COM7_SCCB_RESET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define OV9640_TSLB_YVYU_YUYV 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define OV9640_TSLB_YUYV_UYVY 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define OV9640_COM12_YUV_AVG 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define OV9640_COM12_RSVD 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define OV9640_COM13_GAMMA_NONE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define OV9640_COM13_GAMMA_Y 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define OV9640_COM13_GAMMA_RAW 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define OV9640_COM13_RGB_AVG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define OV9640_COM13_MATRIX_EN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define OV9640_COM13_Y_DELAY_EN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define OV9640_COM13_YUV_DLY(x) ((x) & 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define OV9640_COM15_OR_00FF 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define OV9640_COM15_OR_01FE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define OV9640_COM15_OR_10F0 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define OV9640_COM15_RGB_NORM 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define OV9640_COM15_RGB_565 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define OV9640_COM15_RGB_555 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define OV9640_COM16_RB_AVG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define OV9640_V2 0x9648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define OV9640_V3 0x9649
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define VERSION(pid, ver) (((pid) << 8) | ((ver) & 0xFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* supported resolutions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) W_QQCIF = 88,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) W_QQVGA = 160,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) W_QCIF = 176,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) W_QVGA = 320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) W_CIF = 352,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) W_VGA = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) W_SXGA = 1280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define H_SXGA 960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Misc. structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct ov9640_reg_alt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 com7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u8 com12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 com13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u8 com15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct ov9640_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct ov9640_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct v4l2_clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct gpio_desc *gpio_power;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct gpio_desc *gpio_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) int model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) int revision;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #endif /* __DRIVERS_MEDIA_VIDEO_OV9640_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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