^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OmniVision OV96xx Camera Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on ov772x camera driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2008 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Kuninori Morimoto <morimoto.kuninori@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Based on ov7670 and soc_camera_platform driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * transition from soc_camera to pxa_camera based on mt9m111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Copyright (C) 2008 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include "ov9640.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define to_ov9640_sensor(sd) container_of(sd, struct ov9640_priv, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* default register setup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static const struct ov9640_reg ov9640_regs_dflt[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) { OV9640_COM5, OV9640_COM5_SYSCLK | OV9640_COM5_LONGEXP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) { OV9640_COM6, OV9640_COM6_OPT_BLC | OV9640_COM6_ADBLC_BIAS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) OV9640_COM6_FMT_RST | OV9640_COM6_ADBLC_OPTEN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) { OV9640_PSHFT, OV9640_PSHFT_VAL(0x01) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) { OV9640_ACOM, OV9640_ACOM_2X_ANALOG | OV9640_ACOM_RSVD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) { OV9640_TSLB, OV9640_TSLB_YUYV_UYVY },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) { OV9640_COM16, OV9640_COM16_RB_AVG },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Gamma curve P */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) { 0x6c, 0x40 }, { 0x6d, 0x30 }, { 0x6e, 0x4b }, { 0x6f, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) { 0x70, 0x70 }, { 0x71, 0x70 }, { 0x72, 0x70 }, { 0x73, 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) { 0x74, 0x60 }, { 0x75, 0x60 }, { 0x76, 0x50 }, { 0x77, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) { 0x78, 0x3a }, { 0x79, 0x2e }, { 0x7a, 0x28 }, { 0x7b, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Gamma curve T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) { 0x7c, 0x04 }, { 0x7d, 0x07 }, { 0x7e, 0x10 }, { 0x7f, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) { 0x80, 0x36 }, { 0x81, 0x44 }, { 0x82, 0x52 }, { 0x83, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) { 0x84, 0x6c }, { 0x85, 0x78 }, { 0x86, 0x8c }, { 0x87, 0x9e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) { 0x88, 0xbb }, { 0x89, 0xd2 }, { 0x8a, 0xe6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Configurations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * NOTE: for YUV, alter the following registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * COM12 |= OV9640_COM12_YUV_AVG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * for RGB, alter the following registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * COM7 |= OV9640_COM7_RGB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * COM13 |= OV9640_COM13_RGB_AVG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * COM15 |= proper RGB color encoding mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static const struct ov9640_reg ov9640_regs_qqcif[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x0f) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) { OV9640_COM1, OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) { OV9640_COM7, OV9640_COM7_QCIF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) { OV9640_COM12, OV9640_COM12_RSVD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) { OV9640_COM15, OV9640_COM15_OR_10F0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static const struct ov9640_reg ov9640_regs_qqvga[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) { OV9640_COM1, OV9640_COM1_QQFMT | OV9640_COM1_HREF_2SKIP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) { OV9640_COM7, OV9640_COM7_QVGA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) { OV9640_COM12, OV9640_COM12_RSVD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) { OV9640_COM15, OV9640_COM15_OR_10F0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static const struct ov9640_reg ov9640_regs_qcif[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x07) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) { OV9640_COM7, OV9640_COM7_QCIF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) { OV9640_COM12, OV9640_COM12_RSVD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) { OV9640_COM15, OV9640_COM15_OR_10F0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const struct ov9640_reg ov9640_regs_qvga[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) { OV9640_COM4, OV9640_COM4_QQ_VP | OV9640_COM4_RSVD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) { OV9640_COM7, OV9640_COM7_QVGA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) { OV9640_COM12, OV9640_COM12_RSVD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { OV9640_COM15, OV9640_COM15_OR_10F0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static const struct ov9640_reg ov9640_regs_cif[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x03) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) { OV9640_COM3, OV9640_COM3_VP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) { OV9640_COM7, OV9640_COM7_CIF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) { OV9640_COM12, OV9640_COM12_RSVD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) { OV9640_COM15, OV9640_COM15_OR_10F0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct ov9640_reg ov9640_regs_vga[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) { OV9640_COM3, OV9640_COM3_VP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { OV9640_COM7, OV9640_COM7_VGA },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { OV9640_COM12, OV9640_COM12_RSVD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { OV9640_COM15, OV9640_COM15_OR_10F0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) static const struct ov9640_reg ov9640_regs_sxga[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { OV9640_CLKRC, OV9640_CLKRC_DPLL_EN | OV9640_CLKRC_DIV(0x01) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { OV9640_COM3, OV9640_COM3_VP },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { OV9640_COM7, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { OV9640_COM12, OV9640_COM12_RSVD },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { OV9640_COM13, OV9640_COM13_GAMMA_RAW | OV9640_COM13_MATRIX_EN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { OV9640_COM15, OV9640_COM15_OR_10F0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static const struct ov9640_reg ov9640_regs_yuv[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { OV9640_MTX1, 0x58 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { OV9640_MTX2, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { OV9640_MTX3, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { OV9640_MTX4, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { OV9640_MTX5, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { OV9640_MTX6, 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { OV9640_MTX7, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { OV9640_MTX8, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { OV9640_MTX9, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { OV9640_MTXS, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct ov9640_reg ov9640_regs_rgb[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { OV9640_MTX1, 0x71 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { OV9640_MTX2, 0x3e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { OV9640_MTX3, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { OV9640_MTX4, 0x33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { OV9640_MTX5, 0x72 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { OV9640_MTX6, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { OV9640_MTX7, 0x2b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { OV9640_MTX8, 0x66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { OV9640_MTX9, 0xd2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { OV9640_MTXS, 0x65 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const u32 ov9640_codes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MEDIA_BUS_FMT_RGB565_2X8_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* read a register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int ov9640_reg_read(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 data = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) .len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) .buf = &data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) msg.flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) *val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* write a register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) static int ov9640_reg_write(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u8 _val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned char data[2] = { reg, val };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .buf = data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* we have to read the register back ... no idea why, maybe HW bug */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ret = ov9640_reg_read(client, reg, &_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "Failed reading back register 0x%02x!\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Read a register, alter its bits, write it back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int ov9640_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 unset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = ov9640_reg_read(client, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "[Read]-Modify-Write of register %02x failed!\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) val |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) val &= ~unset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ret = ov9640_reg_write(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "Read-Modify-[Write] of register %02x failed!\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* Soft reset the camera. This has nothing to do with the RESET pin! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int ov9640_reset(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ret = ov9640_reg_write(client, OV9640_COM7, OV9640_COM7_SCCB_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "An error occurred while entering soft reset!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Start/Stop streaming from the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int ov9640_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Set status of additional camera capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int ov9640_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct ov9640_priv *priv = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct ov9640_priv, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) return ov9640_reg_rmw(client, OV9640_MVFP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) OV9640_MVFP_V, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return ov9640_reg_rmw(client, OV9640_MVFP, 0, OV9640_MVFP_V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return ov9640_reg_rmw(client, OV9640_MVFP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) OV9640_MVFP_H, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ov9640_reg_rmw(client, OV9640_MVFP, 0, OV9640_MVFP_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int ov9640_get_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (reg->reg & ~0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) reg->size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ret = ov9640_reg_read(client, reg->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) reg->val = (__u64)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int ov9640_set_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (reg->reg & ~0xff || reg->val & ~0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return ov9640_reg_write(client, reg->reg, reg->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int ov9640_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct ov9640_priv *priv = to_ov9640_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) gpiod_set_value(priv->gpio_power, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) ret = v4l2_clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) gpiod_set_value(priv->gpio_reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) gpiod_set_value(priv->gpio_reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) v4l2_clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) gpiod_set_value(priv->gpio_power, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* select nearest higher resolution for capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void ov9640_res_roundup(u32 *width, u32 *height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) enum { QQCIF, QQVGA, QCIF, QVGA, CIF, VGA, SXGA };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static const u32 res_x[] = { 88, 160, 176, 320, 352, 640, 1280 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const u32 res_y[] = { 72, 120, 144, 240, 288, 480, 960 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) for (i = 0; i < ARRAY_SIZE(res_x); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (res_x[i] >= *width && res_y[i] >= *height) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) *width = res_x[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) *height = res_y[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) *width = res_x[SXGA];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) *height = res_y[SXGA];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Prepare necessary register changes depending on color encoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static void ov9640_alter_regs(u32 code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct ov9640_reg_alt *alt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) switch (code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) case MEDIA_BUS_FMT_UYVY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) alt->com12 = OV9640_COM12_YUV_AVG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) alt->com13 = OV9640_COM13_Y_DELAY_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) OV9640_COM13_YUV_DLY(0x01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) alt->com7 = OV9640_COM7_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) alt->com13 = OV9640_COM13_RGB_AVG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) alt->com15 = OV9640_COM15_RGB_555;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) case MEDIA_BUS_FMT_RGB565_2X8_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) alt->com7 = OV9640_COM7_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) alt->com13 = OV9640_COM13_RGB_AVG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) alt->com15 = OV9640_COM15_RGB_565;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Setup registers according to resolution and color encoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int ov9640_write_regs(struct i2c_client *client, u32 width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u32 code, struct ov9640_reg_alt *alts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) const struct ov9640_reg *ov9640_regs, *matrix_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) unsigned int ov9640_regs_len, matrix_regs_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* select register configuration for given resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) switch (width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) case W_QQCIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ov9640_regs = ov9640_regs_qqcif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqcif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case W_QQVGA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ov9640_regs = ov9640_regs_qqvga;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qqvga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) case W_QCIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ov9640_regs = ov9640_regs_qcif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qcif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) case W_QVGA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) ov9640_regs = ov9640_regs_qvga;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ov9640_regs_len = ARRAY_SIZE(ov9640_regs_qvga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) case W_CIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) ov9640_regs = ov9640_regs_cif;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) ov9640_regs_len = ARRAY_SIZE(ov9640_regs_cif);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) case W_VGA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) ov9640_regs = ov9640_regs_vga;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ov9640_regs_len = ARRAY_SIZE(ov9640_regs_vga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) case W_SXGA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ov9640_regs = ov9640_regs_sxga;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) ov9640_regs_len = ARRAY_SIZE(ov9640_regs_sxga);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_err(&client->dev, "Failed to select resolution!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /* select color matrix configuration for given color encoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (code == MEDIA_BUS_FMT_UYVY8_2X8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) matrix_regs = ov9640_regs_yuv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) matrix_regs_len = ARRAY_SIZE(ov9640_regs_yuv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) matrix_regs = ov9640_regs_rgb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) matrix_regs_len = ARRAY_SIZE(ov9640_regs_rgb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* write register settings into the module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) for (i = 0; i < ov9640_regs_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) val = ov9640_regs[i].val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) switch (ov9640_regs[i].reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) case OV9640_COM7:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) val |= alts->com7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) case OV9640_COM12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) val |= alts->com12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) case OV9640_COM13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) val |= alts->com13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) case OV9640_COM15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) val |= alts->com15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) ret = ov9640_reg_write(client, ov9640_regs[i].reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* write color matrix configuration into the module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) for (i = 0; i < matrix_regs_len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) ret = ov9640_reg_write(client, matrix_regs[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) matrix_regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* program default register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static int ov9640_prog_dflt(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) for (i = 0; i < ARRAY_SIZE(ov9640_regs_dflt); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = ov9640_reg_write(client, ov9640_regs_dflt[i].reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) ov9640_regs_dflt[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* wait for the changes to actually happen, 140ms are not enough yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) msleep(150);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* set the format we will capture in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static int ov9640_s_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct v4l2_mbus_framefmt *mf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct ov9640_reg_alt alts = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) ov9640_alter_regs(mf->code, &alts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ov9640_reset(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ret = ov9640_prog_dflt(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return ov9640_write_regs(client, mf->width, mf->code, &alts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static int ov9640_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct v4l2_mbus_framefmt *mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) ov9640_res_roundup(&mf->width, &mf->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) switch (mf->code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) case MEDIA_BUS_FMT_RGB565_2X8_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mf->colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mf->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) case MEDIA_BUS_FMT_UYVY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) mf->colorspace = V4L2_COLORSPACE_JPEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return ov9640_s_fmt(sd, mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) cfg->try_fmt = *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int ov9640_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (code->pad || code->index >= ARRAY_SIZE(ov9640_codes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) code->code = ov9640_codes[code->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) static int ov9640_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) sel->r.left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) sel->r.top = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) switch (sel->target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) case V4L2_SEL_TGT_CROP_BOUNDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) case V4L2_SEL_TGT_CROP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) sel->r.width = W_SXGA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) sel->r.height = H_SXGA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) static int ov9640_video_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct ov9640_priv *priv = to_ov9640_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u8 pid, ver, midh, midl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) const char *devname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ret = ov9640_s_power(&priv->subdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * check and show product ID and manufacturer ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) ret = ov9640_reg_read(client, OV9640_PID, &pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ret = ov9640_reg_read(client, OV9640_VER, &ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) ret = ov9640_reg_read(client, OV9640_MIDH, &midh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ret = ov9640_reg_read(client, OV9640_MIDL, &midl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) switch (VERSION(pid, ver)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) case OV9640_V2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) devname = "ov9640";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) priv->revision = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) case OV9640_V3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) devname = "ov9640";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) priv->revision = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_err(&client->dev, "Product ID error %x:%x\n", pid, ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) dev_info(&client->dev, "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) devname, pid, ver, midh, midl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) ret = v4l2_ctrl_handler_setup(&priv->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) ov9640_s_power(&priv->subdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static const struct v4l2_ctrl_ops ov9640_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .s_ctrl = ov9640_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static const struct v4l2_subdev_core_ops ov9640_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) .g_register = ov9640_get_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) .s_register = ov9640_set_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) .s_power = ov9640_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Request bus settings on camera side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int ov9640_get_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct v4l2_mbus_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) cfg->flags = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) V4L2_MBUS_DATA_ACTIVE_HIGH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) cfg->type = V4L2_MBUS_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static const struct v4l2_subdev_video_ops ov9640_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) .s_stream = ov9640_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static const struct v4l2_subdev_pad_ops ov9640_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) .enum_mbus_code = ov9640_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) .get_selection = ov9640_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) .set_fmt = ov9640_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .get_mbus_config = ov9640_get_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static const struct v4l2_subdev_ops ov9640_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .core = &ov9640_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .video = &ov9640_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .pad = &ov9640_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) * i2c_driver function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) static int ov9640_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) const struct i2c_device_id *did)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct ov9640_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) priv->gpio_power = devm_gpiod_get(&client->dev, "Camera power",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (IS_ERR(priv->gpio_power)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = PTR_ERR(priv->gpio_power);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) priv->gpio_reset = devm_gpiod_get(&client->dev, "Camera reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (IS_ERR(priv->gpio_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ret = PTR_ERR(priv->gpio_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) v4l2_i2c_subdev_init(&priv->subdev, client, &ov9640_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) v4l2_ctrl_handler_init(&priv->hdl, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) v4l2_ctrl_new_std(&priv->hdl, &ov9640_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) v4l2_ctrl_new_std(&priv->hdl, &ov9640_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (priv->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ret = priv->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) goto ectrlinit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) priv->subdev.ctrl_handler = &priv->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) priv->clk = v4l2_clk_get(&client->dev, "mclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret = PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) goto ectrlinit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = ov9640_video_probe(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) goto eprobe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) priv->subdev.dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) ret = v4l2_async_register_subdev(&priv->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) goto eprobe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) eprobe:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) v4l2_clk_put(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ectrlinit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) v4l2_ctrl_handler_free(&priv->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static int ov9640_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct ov9640_priv *priv = to_ov9640_sensor(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) v4l2_clk_put(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) v4l2_async_unregister_subdev(&priv->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) v4l2_ctrl_handler_free(&priv->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static const struct i2c_device_id ov9640_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) { "ov9640", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) MODULE_DEVICE_TABLE(i2c, ov9640_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static struct i2c_driver ov9640_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .name = "ov9640",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .probe = ov9640_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .remove = ov9640_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .id_table = ov9640_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) module_i2c_driver(ov9640_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) MODULE_DESCRIPTION("OmniVision OV96xx CMOS Image Sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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