^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ov9281 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X03 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X04 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X05 add function g_mbus_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OV9281_LINK_FREQ_400MHZ 400000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OV9281_PIXEL_RATE (OV9281_LINK_FREQ_400MHZ * 2 * 2 / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OV9281_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CHIP_ID 0x9281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OV9281_REG_CHIP_ID 0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OV9281_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OV9281_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OV9281_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OV9281_REG_EXPOSURE 0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OV9281_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OV9281_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OV9281_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OV9281_REG_GAIN_H 0x3508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OV9281_REG_GAIN_L 0x3509
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OV9281_GAIN_H_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OV9281_GAIN_H_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OV9281_GAIN_L_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OV9281_GAIN_MIN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OV9281_GAIN_MAX 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OV9281_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OV9281_GAIN_DEFAULT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OV9281_REG_TEST_PATTERN 0x5e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OV9281_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OV9281_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OV9281_REG_VTS 0x380e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OV9281_AEC_STROBE_REG 0x3927
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OV9281_AEC_STROBE_REG_H 0x3927
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OV9281_AEC_STROBE_REG_L 0x3928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OV9282_AEC_GROUP_UPDATE_ADDRESS 0x3208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OV9282_AEC_GROUP_UPDATE_START_DATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OV9282_AEC_GROUP_UPDATE_END_DATA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OV9282_AEC_GROUP_UPDATE_END_LAUNCH 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OV9281_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OV9281_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OV9281_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OV9281_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OV9281_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OV9281_NAME "ov9281"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) //for SL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OV9282_FPS 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OV9282_FLIP_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define EXP_DEFAULT_TIME_US 3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OV9282_DEFAULT_GAIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OV9282_VTS_30_FPS 0xe48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OV9282_HTS_30_FPS 0x2d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define FPS_HTS_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #if FPS_HTS_MODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define OV9282_VTS OV9282_VTS_30_FPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OV9282_HTS (OV9282_HTS_30_FPS * 30 / OV9282_FPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OV9282_VTS (OV9282_HTS_30_FPS * 30 / OV9282_FPS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OV9282_HTS OV9282_VTS_30_FPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TIME_MS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define OV9282_EXP_TIME_REG ((uint16_t)(EXP_DEFAULT_TIME_US / 1000 * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) OV9282_FPS * OV9282_VTS / TIME_MS) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define OV9282_STROBE_TIME_REG (OV9282_EXP_TIME_REG >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static const char * const ov9281_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define OV9281_NUM_SUPPLIES ARRAY_SIZE(ov9281_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct ov9281_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct ov9281 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct regulator_bulk_data supplies[OV9281_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct v4l2_ctrl *strobe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) bool is_thunderboot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) bool is_thunderboot_ng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) bool is_first_streamoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) const struct ov9281_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define to_ov9281(sd) container_of(sd, struct ov9281, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) static const struct regval ov9281_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * max_framerate 120fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * mipi_datarate per lane 800Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static const struct regval ov9281_1280x800_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x0302, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x030d, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x030e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3004, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3006, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3011, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3013, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3022, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3023, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x302c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x302f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3030, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3039, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x303a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x303f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3501, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3502, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x3503, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3505, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3507, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3508, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3509, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3610, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3611, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3620, 0x6f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3632, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3633, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3662, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3666, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x366f, 0x5a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3680, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3712, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x372d, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3731, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3732, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3778, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x377d, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3788, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3789, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x378a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x378b, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3799, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x3803, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3804, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3805, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3806, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3807, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3808, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3809, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x380a, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x380b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x380c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x380d, 0xd8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x380e, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x380f, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3810, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3811, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3813, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3814, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x3815, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x3820, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3881, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x38b1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3920, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x4003, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x4008, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x4009, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x400c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x400d, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x4010, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x4043, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x4307, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x4317, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x4501, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x4507, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x4509, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x450a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x4601, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x470f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x4f07, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x4800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x5000, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x5001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x5e00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x5d00, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x5d01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const struct regval ov9281_1280x800_30fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x0103, 0x01},/* software sleep */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x0100, 0x00},/* software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* use 20171222 strobe ok data ok */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x0302, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x030d, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x030e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x3004, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x3005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3011, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3013, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x3022, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x3030, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x3039, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x303a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x3500, 0x00}, //exposure[19:16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x3501, 0x2a}, //exposure[15:8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x3502, 0x90}, //exposure[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x3503, 0x08}, //exposure change delay 1 frame,gain change select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3505, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x3507, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3508, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3509, ((OV9282_DEFAULT_GAIN & 0x0f) << 4)}, //gain (gain<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3610, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x3611, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x3620, 0x6f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x3632, 0x56},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x3633, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x3662, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x3666, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x366f, 0x5a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x3680, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x3712, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x372d, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x3731, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x3732, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x3778, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x377d, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x3788, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x3789, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x378a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x378b, 0x4a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x3799, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x3803, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x3804, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x3805, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x3806, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x3807, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x3808, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x3809, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x380a, 0x03}, /* 1280x800 output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x380b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x380c, (OV9282_HTS >> 8)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x380d, (OV9282_HTS & 0xff)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x380e, OV9282_VTS >> 8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x380f, OV9282_VTS & 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x3810, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x3811, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x3812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x3813, 0x08}, /* 1280x800 v offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x3814, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x3815, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #if OV9282_FLIP_ENABLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x3820, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x3821, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x3820, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x3881, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x38b1, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x3920, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x4003, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x4008, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x4009, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x400c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x400d, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x4010, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x4043, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x4307, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x4317, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x4501, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x4507, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x4509, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x450a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x4601, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x470f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x4f07, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x4800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x5000, 0x9f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x5001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x5e00, 0x00}, //color bar
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x5d00, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x5d01, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* for vsync width 630us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x4311, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x4312, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) //{0x0100, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* for strobe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x3006, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /* exposure control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x3500, 0x00}, //exposure[19:16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x3501, OV9282_EXP_TIME_REG >> 8}, //exposure[15:8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x3502, OV9282_EXP_TIME_REG & 0xff}, //exposure[7:0] //low4 bit fraction bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) /* for strobe control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) //{0x3921,0x00}, //bit[7] shift direction, default 0 positive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x3924, 0x00}, //strobe shift[7:0]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x3925, 0x00}, //span[31:24]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x3926, 0x00}, //span[23:16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x3927, OV9282_STROBE_TIME_REG >> 8}, //span[15:8]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x3928, OV9282_STROBE_TIME_REG & 0xff},//span[7:0] exposure 0xa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static const struct ov9281_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) .height = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) .exp_def = 0x0320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) .hts_def = 0x02d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) .vts_def = 0x0e48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) .reg_list = ov9281_1280x800_30fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .height = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .denominator = 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) .exp_def = 0x0320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) .hts_def = 0x0b60,//0x2d8*4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .vts_def = 0x038e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) .reg_list = ov9281_1280x800_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) OV9281_LINK_FREQ_400MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) static const char * const ov9281_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int ov9281_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static int ov9281_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) ret = ov9281_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) OV9281_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int ov9281_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) static int ov9281_get_reso_dist(const struct ov9281_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static const struct ov9281_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ov9281_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) dist = ov9281_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) static int ov9281_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct ov9281 *ov9281 = to_ov9281(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) const struct ov9281_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) mutex_lock(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) mode = ov9281_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) fmt->format.code = MEDIA_BUS_FMT_Y10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) mutex_unlock(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ov9281->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) __v4l2_ctrl_modify_range(ov9281->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) __v4l2_ctrl_modify_range(ov9281->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) OV9281_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) mutex_unlock(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static int ov9281_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct ov9281 *ov9281 = to_ov9281(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) const struct ov9281_mode *mode = ov9281->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) mutex_lock(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) mutex_unlock(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) fmt->format.code = MEDIA_BUS_FMT_Y10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) mutex_unlock(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int ov9281_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) code->code = MEDIA_BUS_FMT_Y10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int ov9281_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (fse->code != MEDIA_BUS_FMT_Y10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static int ov9281_enable_test_pattern(struct ov9281 *ov9281, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) val = (pattern - 1) | OV9281_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) val = OV9281_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return ov9281_write_reg(ov9281->client, OV9281_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) OV9281_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static int ov9281_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct ov9281 *ov9281 = to_ov9281(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) const struct ov9281_mode *mode = ov9281->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) mutex_lock(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) mutex_unlock(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static void ov9281_get_module_inf(struct ov9281 *ov9281,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) strlcpy(inf->base.sensor, OV9281_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) strlcpy(inf->base.module, ov9281->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) strlcpy(inf->base.lens, ov9281->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static long ov9281_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct ov9281 *ov9281 = to_ov9281(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ov9281_get_module_inf(ov9281, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) ret = ov9281_write_reg(ov9281->client, OV9281_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) OV9281_REG_VALUE_08BIT, OV9281_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ret = ov9281_write_reg(ov9281->client, OV9281_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) OV9281_REG_VALUE_08BIT, OV9281_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static long ov9281_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) ret = ov9281_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ret = ov9281_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ret = ov9281_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static int __ov9281_start_stream(struct ov9281 *ov9281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (!ov9281->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) ret = ov9281_write_array(ov9281->client, ov9281->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mutex_unlock(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) ret = v4l2_ctrl_handler_setup(&ov9281->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) mutex_lock(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return ov9281_write_reg(ov9281->client, OV9281_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) OV9281_REG_VALUE_08BIT, OV9281_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static int __ov9281_stop_stream(struct ov9281 *ov9281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (ov9281->is_thunderboot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ov9281->is_first_streamoff = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return ov9281_write_reg(ov9281->client, OV9281_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) OV9281_REG_VALUE_08BIT, OV9281_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static int ov9281_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct ov9281 *ov9281 = to_ov9281(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct i2c_client *client = ov9281->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) mutex_lock(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) if (on == ov9281->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ret = __ov9281_start_stream(ov9281);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) __ov9281_stop_stream(ov9281);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ov9281->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) mutex_unlock(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static int ov9281_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct ov9281 *ov9281 = to_ov9281(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) struct i2c_client *client = ov9281->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) mutex_lock(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (ov9281->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ret = ov9281_write_array(ov9281->client, ov9281_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ov9281->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) ov9281->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) mutex_unlock(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static inline u32 ov9281_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return DIV_ROUND_UP(cycles, OV9281_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) static int __ov9281_power_on(struct ov9281 *ov9281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct device *dev = &ov9281->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /* No need when thunderboot. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (ov9281->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (!IS_ERR_OR_NULL(ov9281->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ret = pinctrl_select_state(ov9281->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) ov9281->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ret = clk_set_rate(ov9281->xvclk, OV9281_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (clk_get_rate(ov9281->xvclk) != OV9281_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ret = clk_prepare_enable(ov9281->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (!IS_ERR(ov9281->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) gpiod_set_value_cansleep(ov9281->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ret = regulator_bulk_enable(OV9281_NUM_SUPPLIES, ov9281->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (!IS_ERR(ov9281->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) gpiod_set_value_cansleep(ov9281->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (!IS_ERR(ov9281->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) gpiod_set_value_cansleep(ov9281->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) delay_us = ov9281_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) clk_disable_unprepare(ov9281->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static void __ov9281_power_off(struct ov9281 *ov9281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) struct device *dev = &ov9281->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (ov9281->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (ov9281->is_first_streamoff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ov9281->is_thunderboot = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ov9281->is_first_streamoff = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (!IS_ERR(ov9281->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) gpiod_set_value_cansleep(ov9281->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) clk_disable_unprepare(ov9281->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (!IS_ERR(ov9281->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) gpiod_set_value_cansleep(ov9281->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (!IS_ERR_OR_NULL(ov9281->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ret = pinctrl_select_state(ov9281->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ov9281->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) regulator_bulk_disable(OV9281_NUM_SUPPLIES, ov9281->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static int ov9281_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct ov9281 *ov9281 = to_ov9281(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) return __ov9281_power_on(ov9281);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static int ov9281_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct ov9281 *ov9281 = to_ov9281(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) __ov9281_power_off(ov9281);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static int ov9281_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct ov9281 *ov9281 = to_ov9281(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) const struct ov9281_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) mutex_lock(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) try_fmt->code = MEDIA_BUS_FMT_Y10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) mutex_unlock(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static int ov9281_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (fie->code != MEDIA_BUS_FMT_Y10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static int ov9281_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) val = 1 << (OV9281_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static const struct dev_pm_ops ov9281_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) SET_RUNTIME_PM_OPS(ov9281_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) ov9281_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static const struct v4l2_subdev_internal_ops ov9281_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .open = ov9281_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static const struct v4l2_subdev_core_ops ov9281_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .s_power = ov9281_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .ioctl = ov9281_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) .compat_ioctl32 = ov9281_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static const struct v4l2_subdev_video_ops ov9281_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .s_stream = ov9281_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .g_frame_interval = ov9281_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) static const struct v4l2_subdev_pad_ops ov9281_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) .enum_mbus_code = ov9281_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .enum_frame_size = ov9281_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) .enum_frame_interval = ov9281_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .get_fmt = ov9281_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .set_fmt = ov9281_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .get_mbus_config = ov9281_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) static const struct v4l2_subdev_ops ov9281_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) .core = &ov9281_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) .video = &ov9281_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) .pad = &ov9281_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static int ov9281_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) struct ov9281 *ov9281 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct ov9281, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct i2c_client *client = ov9281->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) max = ov9281->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) __v4l2_ctrl_modify_range(ov9281->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ov9281->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ov9281->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) ov9281->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ov9281_write_reg(ov9281->client, OV9282_AEC_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) OV9281_REG_VALUE_08BIT, OV9282_AEC_GROUP_UPDATE_START_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ret = ov9281_write_reg(ov9281->client, OV9281_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) OV9281_REG_VALUE_24BIT, ctrl->val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) ov9281_write_reg(ov9281->client, OV9282_AEC_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) OV9281_REG_VALUE_08BIT, OV9282_AEC_GROUP_UPDATE_END_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) ov9281_write_reg(ov9281->client, OV9282_AEC_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) OV9281_REG_VALUE_08BIT, OV9282_AEC_GROUP_UPDATE_END_LAUNCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) ret = ov9281_write_reg(ov9281->client, OV9281_REG_GAIN_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) OV9281_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) (ctrl->val >> OV9281_GAIN_H_SHIFT) & OV9281_GAIN_H_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret |= ov9281_write_reg(ov9281->client, OV9281_REG_GAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) OV9281_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) ctrl->val & OV9281_GAIN_L_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ret = ov9281_write_reg(ov9281->client, OV9281_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) OV9281_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) ctrl->val + ov9281->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) ret = ov9281_write_reg(ov9281->client, OV9281_AEC_STROBE_REG_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) OV9281_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) (ctrl->val >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) ret |= ov9281_write_reg(ov9281->client, OV9281_AEC_STROBE_REG_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) OV9281_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ctrl->val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ret = ov9281_enable_test_pattern(ov9281, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static const struct v4l2_ctrl_ops ov9281_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .s_ctrl = ov9281_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) static int ov9281_initialize_controls(struct ov9281 *ov9281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) const struct ov9281_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) handler = &ov9281->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) mode = ov9281->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) handler->lock = &ov9281->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) 0, OV9281_PIXEL_RATE, 1, OV9281_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ov9281->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) if (ov9281->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ov9281->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) ov9281->vblank = v4l2_ctrl_new_std(handler, &ov9281_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) OV9281_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ov9281->exposure = v4l2_ctrl_new_std(handler, &ov9281_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) V4L2_CID_EXPOSURE, OV9281_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) exposure_max, OV9281_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ov9281->anal_gain = v4l2_ctrl_new_std(handler, &ov9281_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) V4L2_CID_ANALOGUE_GAIN, OV9281_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) OV9281_GAIN_MAX, OV9281_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) OV9281_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ov9281->strobe = v4l2_ctrl_new_std(handler, &ov9281_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) V4L2_CID_BRIGHTNESS, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) exposure_max/16, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) 0xc8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) ov9281->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) &ov9281_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ARRAY_SIZE(ov9281_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) 0, 0, ov9281_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) dev_err(&ov9281->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) ov9281->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) static int ov9281_check_sensor_id(struct ov9281 *ov9281,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) struct device *dev = &ov9281->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (ov9281->is_thunderboot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) dev_info(dev, "Enable thunderboot mode, skip sensor id check\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ret = ov9281_read_reg(client, OV9281_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) OV9281_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) static int ov9281_configure_regulators(struct ov9281 *ov9281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) for (i = 0; i < OV9281_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ov9281->supplies[i].supply = ov9281_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) return devm_regulator_bulk_get(&ov9281->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) OV9281_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) ov9281->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) static int ov9281_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct ov9281 *ov9281;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) ov9281 = devm_kzalloc(dev, sizeof(*ov9281), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (!ov9281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) &ov9281->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) &ov9281->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) &ov9281->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) &ov9281->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ov9281->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) ov9281->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) ov9281->is_thunderboot = IS_ENABLED(CONFIG_VIDEO_ROCKCHIP_THUNDER_BOOT_ISP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) ov9281->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (IS_ERR(ov9281->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ov9281->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (IS_ERR(ov9281->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) ov9281->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_ASIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (IS_ERR(ov9281->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) ov9281->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (!IS_ERR(ov9281->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) ov9281->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) pinctrl_lookup_state(ov9281->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (IS_ERR(ov9281->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) ov9281->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) pinctrl_lookup_state(ov9281->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (IS_ERR(ov9281->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) ret = ov9281_configure_regulators(ov9281);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) mutex_init(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) sd = &ov9281->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) v4l2_i2c_subdev_init(sd, client, &ov9281_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ret = ov9281_initialize_controls(ov9281);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) ret = __ov9281_power_on(ov9281);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ret = ov9281_check_sensor_id(ov9281, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) sd->internal_ops = &ov9281_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ov9281->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) ret = media_entity_pads_init(&sd->entity, 1, &ov9281->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (strcmp(ov9281->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ov9281->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) OV9281_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) __ov9281_power_off(ov9281);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) v4l2_ctrl_handler_free(&ov9281->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) mutex_destroy(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) static int ov9281_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) struct ov9281 *ov9281 = to_ov9281(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) v4l2_ctrl_handler_free(&ov9281->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) mutex_destroy(&ov9281->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) __ov9281_power_off(ov9281);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) static const struct of_device_id ov9281_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) { .compatible = "ovti,ov9281" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) MODULE_DEVICE_TABLE(of, ov9281_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) static const struct i2c_device_id ov9281_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) { "ovti,ov9281", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) static struct i2c_driver ov9281_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) .name = OV9281_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .pm = &ov9281_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .of_match_table = of_match_ptr(ov9281_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .probe = &ov9281_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .remove = &ov9281_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .id_table = ov9281_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) return i2c_add_driver(&ov9281_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) i2c_del_driver(&ov9281_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) MODULE_DESCRIPTION("OmniVision ov9281 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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