^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ov7750 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X04 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X05 add function g_mbus_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* 45Mhz * 4 Binning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OV7750_PIXEL_RATE (49 * 1000 * 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OV7750_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CHIP_ID 0x7750
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OV7750_REG_CHIP_ID 0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OV7750_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OV7750_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OV7750_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OV7750_REG_EXPOSURE 0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OV7750_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OV7750_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OV7750_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OV7750_REG_GAIN_H 0x350a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OV7750_REG_GAIN_L 0x350b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OV7750_GAIN_H_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OV7750_GAIN_H_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OV7750_GAIN_L_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OV7750_GAIN_MIN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OV7750_GAIN_MAX 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OV7750_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OV7750_GAIN_DEFAULT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OV7750_REG_TEST_PATTERN 0x5e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OV7750_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OV7750_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OV7750_REG_VTS 0x380e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OV7750_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OV7750_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OV7750_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OV7750_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OV7750_REG_MANUAL_CTL 0x3503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OV7750_CHIP_REVISION_REG 0x3029
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OV7750_R1F 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OV7750_EXP_MARGIN_LIMIT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OF_CAMERA_PINCTRL_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OF_CAMERA_PINCTRL_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OV7750_NAME "ov7750"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OV7750_LANES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static const struct regval *ov7750_global_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static const char * const ov7750_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OV7750_NUM_SUPPLIES ARRAY_SIZE(ov7750_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct ov7750_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct ov7750 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct regulator_bulk_data supplies[OV7750_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const struct ov7750_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define to_ov7750(sd) container_of(sd, struct ov7750, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Rev: 1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static const struct regval ov7750_global_regs_r1f[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0x3005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x3012, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x3013, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x3014, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x3016, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x3017, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x3018, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x301a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x301b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x301c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x3023, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x3037, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x3098, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x3099, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x309a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x309b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x30b0, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x30b1, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x30b3, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x30b4, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x30b5, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x3106, 0xda},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x3500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x3501, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x3502, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x3503, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x3509, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x350b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x3600, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x3602, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x3620, 0xb7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x3622, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x3626, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x3627, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x3630, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x3631, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3634, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x3636, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x3662, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x3663, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3664, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3666, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3669, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x366a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x366b, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3673, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3674, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3675, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3705, 0xc1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3709, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x373c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3742, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3757, 0xb3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3788, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x37a8, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x37a9, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3801, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3803, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3804, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3805, 0x8b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3806, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3807, 0xeb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3808, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x380a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x380b, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* line length_pclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x380c, 0x03}, //{0x380c, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x380d, 0xa0}, //{0x380d, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* frame_length_line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x380e, 0x07}, //{0x380e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x380f, 0xd0}, //{0x380f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3810, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3811, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3813, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3814, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3815, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3820, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x382f, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3832, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3833, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x3834, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3835, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3837, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3b80, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3b81, 0xa5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3b82, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3b83, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x3b84, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x3b85, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x3b86, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x3b87, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3b88, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3b89, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3b8a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3b8b, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3b8c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3b8d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3b8e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x3b8f, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x3b94, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3b95, 0xf2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3b96, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3c00, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3c01, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3c02, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3c03, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x3c04, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3c05, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3c06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3c07, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x3c0c, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3c0d, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3c0e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3c0f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x4001, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x4004, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x4005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x404e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x4241, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x4242, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x4300, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x4301, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x4501, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x4600, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x4601, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x4801, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x4806, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x4819, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x4823, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x4837, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x4a0d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x4a47, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x4a49, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x4a4b, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x5000, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x5001, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {REG_NULL, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * Rev: xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static const struct regval ov7750_global_regs_rxx[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {REG_NULL, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * max_framerate 60fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * mipi_datarate per lane 400Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static const struct regval ov7750_640x480_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3501, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3502, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x3503, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x3509, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x350b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x3600, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x3602, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x3620, 0xb7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x3622, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x3626, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x3627, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x3630, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x3631, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x3634, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x3636, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x3662, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x3663, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x3664, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x3666, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x3669, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x366a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x366b, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x3673, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x3674, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x3675, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x3705, 0xc1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x3709, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x373c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x3742, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x3757, 0xb3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x3788, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x37a8, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x37a9, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* vga */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x3801, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x3803, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x3804, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x3805, 0x8b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x3806, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x3807, 0xeb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* vaga end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x3808, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x380a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x380b, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x380c, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x380d, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x380e, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x380f, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x3810, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x3811, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x3812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x3813, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x3814, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x3815, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x3820, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x382f, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x3832, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x3833, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x3834, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x3835, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x3837, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {REG_NULL, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const struct ov7750_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) .width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) .exp_def = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) .hts_def = 0x03a0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) .vts_def = 0x07d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) .reg_list = ov7750_640x480_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define OV7750_LINK_FREQ_400MHZ 400000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) OV7750_LINK_FREQ_400MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static const char * const ov7750_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static int ov7750_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static int ov7750_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ret = ov7750_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) OV7750_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static int ov7750_read_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static int ov7750_get_reso_dist(const struct ov7750_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static const struct ov7750_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) ov7750_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dist = ov7750_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static int ov7750_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct ov7750 *ov7750 = to_ov7750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) const struct ov7750_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) mutex_lock(&ov7750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) mode = ov7750_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) mutex_unlock(&ov7750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ov7750->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) __v4l2_ctrl_modify_range(ov7750->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) __v4l2_ctrl_modify_range(ov7750->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) OV7750_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) mutex_unlock(&ov7750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static int ov7750_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct ov7750 *ov7750 = to_ov7750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) const struct ov7750_mode *mode = ov7750->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mutex_lock(&ov7750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) mutex_unlock(&ov7750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) mutex_unlock(&ov7750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) static int ov7750_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static int ov7750_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int ov7750_enable_test_pattern(struct ov7750 *ov7750, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) val = (pattern - 1) | OV7750_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) val = OV7750_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return ov7750_write_reg(ov7750->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) OV7750_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) OV7750_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static void ov7750_get_module_inf(struct ov7750 *ov7750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) strlcpy(inf->base.sensor, OV7750_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) strlcpy(inf->base.module, ov7750->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) strlcpy(inf->base.lens, ov7750->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static long ov7750_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct ov7750 *ov7750 = to_ov7750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) ov7750_get_module_inf(ov7750, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ret = ov7750_write_reg(ov7750->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) OV7750_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) OV7750_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) OV7750_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ret = ov7750_write_reg(ov7750->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) OV7750_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) OV7750_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) OV7750_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ret = -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static long ov7750_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ret = ov7750_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ret = ov7750_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ret = ov7750_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int __ov7750_start_stream(struct ov7750 *ov7750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) ret = ov7750_write_array(ov7750->client, ov7750->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) mutex_unlock(&ov7750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ret = v4l2_ctrl_handler_setup(&ov7750->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) mutex_lock(&ov7750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return ov7750_write_reg(ov7750->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) OV7750_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) OV7750_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) OV7750_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static int __ov7750_stop_stream(struct ov7750 *ov7750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return ov7750_write_reg(ov7750->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) OV7750_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) OV7750_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) OV7750_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static int ov7750_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct ov7750 *ov7750 = to_ov7750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct i2c_client *client = ov7750->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) mutex_lock(&ov7750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (on == ov7750->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ret = __ov7750_start_stream(ov7750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) __ov7750_stop_stream(ov7750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) ov7750->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mutex_unlock(&ov7750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static int ov7750_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct ov7750 *ov7750 = to_ov7750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct i2c_client *client = ov7750->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) mutex_lock(&ov7750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (ov7750->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret = ov7750_write_array(ov7750->client, ov7750_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ov7750->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) ov7750->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) mutex_unlock(&ov7750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) static inline u32 ov7750_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return DIV_ROUND_UP(cycles, OV7750_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static int __ov7750_power_on(struct ov7750 *ov7750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct device *dev = &ov7750->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!IS_ERR_OR_NULL(ov7750->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ret = pinctrl_select_state(ov7750->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) ov7750->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ret = clk_set_rate(ov7750->xvclk, OV7750_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (clk_get_rate(ov7750->xvclk) != OV7750_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ret = clk_prepare_enable(ov7750->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (!IS_ERR(ov7750->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) gpiod_set_value_cansleep(ov7750->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ret = regulator_bulk_enable(OV7750_NUM_SUPPLIES, ov7750->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (!IS_ERR(ov7750->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) gpiod_set_value_cansleep(ov7750->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (!IS_ERR(ov7750->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) gpiod_set_value_cansleep(ov7750->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) delay_us = ov7750_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) clk_disable_unprepare(ov7750->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static void __ov7750_power_off(struct ov7750 *ov7750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct device *dev = &ov7750->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (!IS_ERR(ov7750->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) gpiod_set_value_cansleep(ov7750->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) clk_disable_unprepare(ov7750->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (!IS_ERR(ov7750->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) gpiod_set_value_cansleep(ov7750->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (!IS_ERR_OR_NULL(ov7750->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ret = pinctrl_select_state(ov7750->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ov7750->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) regulator_bulk_disable(OV7750_NUM_SUPPLIES, ov7750->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static int ov7750_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct ov7750 *ov7750 = to_ov7750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return __ov7750_power_on(ov7750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) static int ov7750_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct ov7750 *ov7750 = to_ov7750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) __ov7750_power_off(ov7750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) static int ov7750_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) struct ov7750 *ov7750 = to_ov7750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) const struct ov7750_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) mutex_lock(&ov7750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) mutex_unlock(&ov7750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static int ov7750_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static int ov7750_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) val = 1 << (OV7750_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) config->type = V4L2_MBUS_CSI2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) static const struct dev_pm_ops ov7750_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) SET_RUNTIME_PM_OPS(ov7750_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ov7750_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static const struct v4l2_subdev_internal_ops ov7750_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .open = ov7750_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static const struct v4l2_subdev_core_ops ov7750_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) .s_power = ov7750_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) .ioctl = ov7750_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .compat_ioctl32 = ov7750_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static const struct v4l2_subdev_video_ops ov7750_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .s_stream = ov7750_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .g_mbus_config = ov7750_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) static const struct v4l2_subdev_pad_ops ov7750_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) .enum_mbus_code = ov7750_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) .enum_frame_size = ov7750_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) .enum_frame_interval = ov7750_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .get_fmt = ov7750_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .set_fmt = ov7750_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) static const struct v4l2_subdev_ops ov7750_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .core = &ov7750_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .video = &ov7750_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) .pad = &ov7750_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static int ov7750_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct ov7750 *ov7750 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct ov7750, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) struct i2c_client *client = ov7750->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) max = ov7750->cur_mode->height + ctrl->val -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) OV7750_EXP_MARGIN_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) __v4l2_ctrl_modify_range(ov7750->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ov7750->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ov7750->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ov7750->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ret = ov7750_write_reg(ov7750->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) OV7750_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) OV7750_REG_VALUE_24BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) ctrl->val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ret = ov7750_write_reg(ov7750->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) OV7750_REG_GAIN_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) OV7750_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) (ctrl->val >> OV7750_GAIN_H_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) OV7750_GAIN_H_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) ret |= ov7750_write_reg(ov7750->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) OV7750_REG_GAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) OV7750_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ctrl->val & OV7750_GAIN_L_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ret = ov7750_write_reg(ov7750->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) OV7750_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) OV7750_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) ctrl->val + ov7750->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ret = ov7750_enable_test_pattern(ov7750, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static const struct v4l2_ctrl_ops ov7750_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .s_ctrl = ov7750_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) static int ov7750_initialize_controls(struct ov7750 *ov7750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) const struct ov7750_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) handler = &ov7750->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) mode = ov7750->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) handler->lock = &ov7750->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) 0, OV7750_PIXEL_RATE, 1, OV7750_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ov7750->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (ov7750->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) ov7750->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) ov7750->vblank = v4l2_ctrl_new_std(handler, &ov7750_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) OV7750_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) exposure_max = mode->vts_def - OV7750_EXP_MARGIN_LIMIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ov7750->exposure = v4l2_ctrl_new_std(handler, &ov7750_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) V4L2_CID_EXPOSURE, OV7750_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) exposure_max, OV7750_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ov7750->anal_gain = v4l2_ctrl_new_std(handler, &ov7750_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) V4L2_CID_ANALOGUE_GAIN, OV7750_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) OV7750_GAIN_MAX, OV7750_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) OV7750_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) ov7750->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) &ov7750_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ARRAY_SIZE(ov7750_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) 0, 0, ov7750_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) dev_err(&ov7750->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ov7750->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static int ov7750_check_sensor_id(struct ov7750 *ov7750,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) struct device *dev = &ov7750->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) ret = ov7750_read_reg(client, OV7750_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) OV7750_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) dev_err(dev, "Unexpected sensor id(%04x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) ret = ov7750_read_reg(client, OV7750_CHIP_REVISION_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) OV7750_REG_VALUE_08BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) dev_err(dev, "Read chip revision register error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) id &= 0xf0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (id == OV7750_R1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ov7750_global_regs = ov7750_global_regs_r1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ov7750_global_regs = ov7750_global_regs_rxx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) dev_info(dev, "Detected OV%04x sensor, REVISION 0x%x\n", CHIP_ID, id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static int ov7750_configure_regulators(struct ov7750 *ov7750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) for (i = 0; i < OV7750_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ov7750->supplies[i].supply = ov7750_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return devm_regulator_bulk_get(&ov7750->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) OV7750_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ov7750->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static int ov7750_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) struct ov7750 *ov7750;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ov7750 = devm_kzalloc(dev, sizeof(*ov7750), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (!ov7750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) &ov7750->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) &ov7750->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) &ov7750->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) &ov7750->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) ov7750->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) ov7750->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) ov7750->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (IS_ERR(ov7750->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ov7750->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (IS_ERR(ov7750->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ov7750->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (IS_ERR(ov7750->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) ret = ov7750_configure_regulators(ov7750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ov7750->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (!IS_ERR(ov7750->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) ov7750->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) pinctrl_lookup_state(ov7750->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) OF_CAMERA_PINCTRL_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if (IS_ERR(ov7750->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ov7750->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) pinctrl_lookup_state(ov7750->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) OF_CAMERA_PINCTRL_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (IS_ERR(ov7750->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) mutex_init(&ov7750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) sd = &ov7750->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) v4l2_i2c_subdev_init(sd, client, &ov7750_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) ret = ov7750_initialize_controls(ov7750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) ret = __ov7750_power_on(ov7750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) ret = ov7750_check_sensor_id(ov7750, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) sd->internal_ops = &ov7750_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) ov7750->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) ret = media_entity_pads_init(&sd->entity, 1, &ov7750->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (strcmp(ov7750->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) ov7750->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) OV7750_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) __ov7750_power_off(ov7750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) v4l2_ctrl_handler_free(&ov7750->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) mutex_destroy(&ov7750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static int ov7750_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) struct ov7750 *ov7750 = to_ov7750(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) v4l2_ctrl_handler_free(&ov7750->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) mutex_destroy(&ov7750->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) __ov7750_power_off(ov7750);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static const struct of_device_id ov7750_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) { .compatible = "ovti,ov7750" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) MODULE_DEVICE_TABLE(of, ov7750_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static const struct i2c_device_id ov7750_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) { "ovti,ov7750", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static struct i2c_driver ov7750_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) .name = OV7750_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) .pm = &ov7750_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) .of_match_table = of_match_ptr(ov7750_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) .probe = &ov7750_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) .remove = &ov7750_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) .id_table = ov7750_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return i2c_add_driver(&ov7750_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) i2c_del_driver(&ov7750_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) MODULE_DESCRIPTION("OmniVision ov7750 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags