^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ov772x Camera Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Jacopo Mondi <jacopo+renesas@jmondi.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2008 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Kuninori Morimoto <morimoto.kuninori@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Based on ov7670 and soc_camera_platform driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (C) 2008 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/i2c/ov772x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-image-sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * register offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GAIN 0x00 /* AGC - Gain control gain setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BLUE 0x01 /* AWB - Blue channel gain setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define RED 0x02 /* AWB - Red channel gain setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GREEN 0x03 /* AWB - Green channel gain setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define COM1 0x04 /* Common control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BAVG 0x05 /* U/B Average Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GAVG 0x06 /* Y/Gb Average Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RAVG 0x07 /* V/R Average Level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AECH 0x08 /* Exposure Value - AEC MSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define COM2 0x09 /* Common control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PID 0x0A /* Product ID Number MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VER 0x0B /* Product ID Number LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define COM3 0x0C /* Common control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define COM4 0x0D /* Common control 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define COM5 0x0E /* Common control 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define COM6 0x0F /* Common control 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AEC 0x10 /* Exposure Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLKRC 0x11 /* Internal clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define COM7 0x12 /* Common control 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define COM8 0x13 /* Common control 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define COM9 0x14 /* Common control 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define COM10 0x15 /* Common control 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define REG16 0x16 /* Register 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HSTART 0x17 /* Horizontal sensor size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HSIZE 0x18 /* Horizontal frame (HREF column) end high 8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define VSTART 0x19 /* Vertical frame (row) start high 8-bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define VSIZE 0x1A /* Vertical sensor size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PSHFT 0x1B /* Data format - pixel delay select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MIDH 0x1C /* Manufacturer ID byte - high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MIDL 0x1D /* Manufacturer ID byte - low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LAEC 0x1F /* Fine AEC value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define COM11 0x20 /* Common control 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BDBASE 0x22 /* Banding filter Minimum AEC value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DBSTEP 0x23 /* Banding filter Maximum Setp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define AEW 0x24 /* AGC/AEC - Stable operating region (upper limit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define AEB 0x25 /* AGC/AEC - Stable operating region (lower limit) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define VPT 0x26 /* AGC/AEC Fast mode operating region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REG28 0x28 /* Register 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HOUTSIZE 0x29 /* Horizontal data output size MSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define EXHCH 0x2A /* Dummy pixel insert MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define EXHCL 0x2B /* Dummy pixel insert LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define VOUTSIZE 0x2C /* Vertical data output size MSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ADVFL 0x2D /* LSB of insert dummy lines in Vertical direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ADVFH 0x2E /* MSG of insert dummy lines in Vertical direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define YAVE 0x2F /* Y/G Channel Average value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define LUMHTH 0x30 /* Histogram AEC/AGC Luminance high level threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LUMLTH 0x31 /* Histogram AEC/AGC Luminance low level threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HREF 0x32 /* Image start and size control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DM_LNL 0x33 /* Dummy line low 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DM_LNH 0x34 /* Dummy line high 8 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ADOFF_B 0x35 /* AD offset compensation value for B channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ADOFF_R 0x36 /* AD offset compensation value for R channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ADOFF_GB 0x37 /* AD offset compensation value for Gb channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ADOFF_GR 0x38 /* AD offset compensation value for Gr channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OFF_B 0x39 /* Analog process B channel offset value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OFF_R 0x3A /* Analog process R channel offset value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OFF_GB 0x3B /* Analog process Gb channel offset value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OFF_GR 0x3C /* Analog process Gr channel offset value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define COM12 0x3D /* Common control 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define COM13 0x3E /* Common control 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define COM14 0x3F /* Common control 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define COM15 0x40 /* Common control 15*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define COM16 0x41 /* Common control 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TGT_B 0x42 /* BLC blue channel target value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TGT_R 0x43 /* BLC red channel target value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TGT_GB 0x44 /* BLC Gb channel target value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TGT_GR 0x45 /* BLC Gr channel target value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* for ov7720 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define LCC0 0x46 /* Lens correction control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define LCC1 0x47 /* Lens correction option 1 - X coordinate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define LCC2 0x48 /* Lens correction option 2 - Y coordinate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define LCC3 0x49 /* Lens correction option 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define LCC4 0x4A /* Lens correction option 4 - radius of the circular */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define LCC5 0x4B /* Lens correction option 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LCC6 0x4C /* Lens correction option 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* for ov7725 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define LC_CTR 0x46 /* Lens correction control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define LC_XC 0x47 /* X coordinate of lens correction center relative */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define LC_YC 0x48 /* Y coordinate of lens correction center relative */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define LC_COEF 0x49 /* Lens correction coefficient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define LC_RADI 0x4A /* Lens correction radius */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define LC_COEFB 0x4B /* Lens B channel compensation coefficient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define LC_COEFR 0x4C /* Lens R channel compensation coefficient */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define FIXGAIN 0x4D /* Analog fix gain amplifer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AREF0 0x4E /* Sensor reference control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define AREF1 0x4F /* Sensor reference current control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define AREF2 0x50 /* Analog reference control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define AREF3 0x51 /* ADC reference control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AREF4 0x52 /* ADC reference control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define AREF5 0x53 /* ADC reference control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define AREF6 0x54 /* Analog reference control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define AREF7 0x55 /* Analog reference control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define UFIX 0x60 /* U channel fixed value output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define VFIX 0x61 /* V channel fixed value output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AWBB_BLK 0x62 /* AWB option for advanced AWB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AWB_CTRL0 0x63 /* AWB control byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define DSP_CTRL1 0x64 /* DSP control byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define DSP_CTRL2 0x65 /* DSP control byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define DSP_CTRL3 0x66 /* DSP control byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define DSP_CTRL4 0x67 /* DSP control byte 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AWB_BIAS 0x68 /* AWB BLC level clip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AWB_CTRL1 0x69 /* AWB control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AWB_CTRL2 0x6A /* AWB control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AWB_CTRL3 0x6B /* AWB control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AWB_CTRL4 0x6C /* AWB control 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AWB_CTRL5 0x6D /* AWB control 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AWB_CTRL6 0x6E /* AWB control 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AWB_CTRL7 0x6F /* AWB control 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AWB_CTRL8 0x70 /* AWB control 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AWB_CTRL9 0x71 /* AWB control 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AWB_CTRL10 0x72 /* AWB control 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AWB_CTRL11 0x73 /* AWB control 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AWB_CTRL12 0x74 /* AWB control 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define AWB_CTRL13 0x75 /* AWB control 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AWB_CTRL14 0x76 /* AWB control 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AWB_CTRL15 0x77 /* AWB control 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AWB_CTRL16 0x78 /* AWB control 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define AWB_CTRL17 0x79 /* AWB control 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define AWB_CTRL18 0x7A /* AWB control 18 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define AWB_CTRL19 0x7B /* AWB control 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define AWB_CTRL20 0x7C /* AWB control 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AWB_CTRL21 0x7D /* AWB control 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GAM1 0x7E /* Gamma Curve 1st segment input end point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GAM2 0x7F /* Gamma Curve 2nd segment input end point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GAM3 0x80 /* Gamma Curve 3rd segment input end point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GAM4 0x81 /* Gamma Curve 4th segment input end point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GAM5 0x82 /* Gamma Curve 5th segment input end point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GAM6 0x83 /* Gamma Curve 6th segment input end point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define GAM7 0x84 /* Gamma Curve 7th segment input end point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GAM8 0x85 /* Gamma Curve 8th segment input end point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GAM9 0x86 /* Gamma Curve 9th segment input end point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define GAM10 0x87 /* Gamma Curve 10th segment input end point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define GAM11 0x88 /* Gamma Curve 11th segment input end point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define GAM12 0x89 /* Gamma Curve 12th segment input end point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define GAM13 0x8A /* Gamma Curve 13th segment input end point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define GAM14 0x8B /* Gamma Curve 14th segment input end point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GAM15 0x8C /* Gamma Curve 15th segment input end point */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SLOP 0x8D /* Gamma curve highest segment slope */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DNSTH 0x8E /* De-noise threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define EDGE_STRNGT 0x8F /* Edge strength control when manual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define EDGE_TRSHLD 0x90 /* Edge threshold control when manual mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define DNSOFF 0x91 /* Auto De-noise threshold control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define EDGE_UPPER 0x92 /* Edge strength upper limit when Auto mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define EDGE_LOWER 0x93 /* Edge strength lower limit when Auto mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MTX1 0x94 /* Matrix coefficient 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MTX2 0x95 /* Matrix coefficient 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MTX3 0x96 /* Matrix coefficient 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MTX4 0x97 /* Matrix coefficient 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MTX5 0x98 /* Matrix coefficient 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MTX6 0x99 /* Matrix coefficient 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MTX_CTRL 0x9A /* Matrix control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define BRIGHT 0x9B /* Brightness control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CNTRST 0x9C /* Contrast contrast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CNTRST_CTRL 0x9D /* Contrast contrast center */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define UVAD_J0 0x9E /* Auto UV adjust contrast 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define UVAD_J1 0x9F /* Auto UV adjust contrast 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SCAL0 0xA0 /* Scaling control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SCAL1 0xA1 /* Scaling control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SCAL2 0xA2 /* Scaling control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define FIFODLYM 0xA3 /* FIFO manual mode delay control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define FIFODLYA 0xA4 /* FIFO auto mode delay control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SDE 0xA6 /* Special digital effect control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define USAT 0xA7 /* U component saturation control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define VSAT 0xA8 /* V component saturation control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* for ov7720 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define HUE0 0xA9 /* Hue control 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define HUE1 0xAA /* Hue control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* for ov7725 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define HUECOS 0xA9 /* Cosine value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define HUESIN 0xAA /* Sine value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SIGN 0xAB /* Sign bit for Hue and contrast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define DSPAUTO 0xAC /* DSP auto function ON/OFF control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * register detail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* COM2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SOFT_SLEEP_MODE 0x10 /* Soft sleep mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Output drive capability */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define OCAP_1x 0x00 /* 1x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define OCAP_2x 0x01 /* 2x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define OCAP_3x 0x02 /* 3x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define OCAP_4x 0x03 /* 4x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* COM3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SWAP_MASK (SWAP_RGB | SWAP_YUV | SWAP_ML)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IMG_MASK (VFLIP_IMG | HFLIP_IMG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define VFLIP_IMG 0x80 /* Vertical flip image ON/OFF selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define HFLIP_IMG 0x40 /* Horizontal mirror image ON/OFF selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define SWAP_RGB 0x20 /* Swap B/R output sequence in RGB mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define SWAP_YUV 0x10 /* Swap Y/UV output sequence in YUV mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define SWAP_ML 0x08 /* Swap output MSB/LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Tri-state option for output clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define NOTRI_CLOCK 0x04 /* 0: Tri-state at this period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* 1: No tri-state at this period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Tri-state option for output data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define NOTRI_DATA 0x02 /* 0: Tri-state at this period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* 1: No tri-state at this period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define SCOLOR_TEST 0x01 /* Sensor color bar test pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* COM4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) /* PLL frequency control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PLL_BYPASS 0x00 /* 00: Bypass PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PLL_4x 0x40 /* 01: PLL 4x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PLL_6x 0x80 /* 10: PLL 6x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PLL_8x 0xc0 /* 11: PLL 8x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* AEC evaluate window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define AEC_FULL 0x00 /* 00: Full window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define AEC_1p2 0x10 /* 01: 1/2 window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define AEC_1p4 0x20 /* 10: 1/4 window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define AEC_2p3 0x30 /* 11: Low 2/3 window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define COM4_RESERVED 0x01 /* Reserved bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* COM5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define AFR_ON_OFF 0x80 /* Auto frame rate control ON/OFF selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define AFR_SPPED 0x40 /* Auto frame rate control speed selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* Auto frame rate max rate control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define AFR_NO_RATE 0x00 /* No reduction of frame rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define AFR_1p2 0x10 /* Max reduction to 1/2 frame rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define AFR_1p4 0x20 /* Max reduction to 1/4 frame rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define AFR_1p8 0x30 /* Max reduction to 1/8 frame rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Auto frame rate active point control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define AF_2x 0x00 /* Add frame when AGC reaches 2x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define AF_4x 0x04 /* Add frame when AGC reaches 4x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define AF_8x 0x08 /* Add frame when AGC reaches 8x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define AF_16x 0x0c /* Add frame when AGC reaches 16x gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* AEC max step control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define AEC_NO_LIMIT 0x01 /* 0 : AEC incease step has limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* 1 : No limit to AEC increase step */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* CLKRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Input clock divider register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CLKRC_RESERVED 0x80 /* Reserved bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CLKRC_DIV(n) ((n) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* COM7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* SCCB Register Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SCCB_RESET 0x80 /* 0 : No change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* 1 : Resets all registers to default */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* Resolution selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SLCT_MASK 0x40 /* Mask of VGA or QVGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SLCT_VGA 0x00 /* 0 : VGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define SLCT_QVGA 0x40 /* 1 : QVGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define ITU656_ON_OFF 0x20 /* ITU656 protocol ON/OFF selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define SENSOR_RAW 0x10 /* Sensor RAW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* RGB output format control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define FMT_MASK 0x0c /* Mask of color format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define FMT_GBR422 0x00 /* 00 : GBR 4:2:2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define FMT_RGB565 0x04 /* 01 : RGB 565 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define FMT_RGB555 0x08 /* 10 : RGB 555 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define FMT_RGB444 0x0c /* 11 : RGB 444 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* Output format control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define OFMT_MASK 0x03 /* Mask of output format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define OFMT_YUV 0x00 /* 00 : YUV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define OFMT_P_BRAW 0x01 /* 01 : Processed Bayer RAW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define OFMT_RGB 0x02 /* 10 : RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define OFMT_BRAW 0x03 /* 11 : Bayer RAW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* COM8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define FAST_ALGO 0x80 /* Enable fast AGC/AEC algorithm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* AEC Setp size limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define UNLMT_STEP 0x40 /* 0 : Step size is limited */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* 1 : Unlimited step size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define BNDF_ON_OFF 0x20 /* Banding filter ON/OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define AEC_BND 0x10 /* Enable AEC below banding value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define AEC_ON_OFF 0x08 /* Fine AEC ON/OFF control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define AGC_ON 0x04 /* AGC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define AWB_ON 0x02 /* AWB Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define AEC_ON 0x01 /* AEC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* COM9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define BASE_AECAGC 0x80 /* Histogram or average based AEC/AGC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Automatic gain ceiling - maximum AGC value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define GAIN_2x 0x00 /* 000 : 2x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define GAIN_4x 0x10 /* 001 : 4x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define GAIN_8x 0x20 /* 010 : 8x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define GAIN_16x 0x30 /* 011 : 16x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define GAIN_32x 0x40 /* 100 : 32x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define GAIN_64x 0x50 /* 101 : 64x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define GAIN_128x 0x60 /* 110 : 128x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define DROP_VSYNC 0x04 /* Drop VSYNC output of corrupt frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define DROP_HREF 0x02 /* Drop HREF output of corrupt frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* COM11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SGLF_ON_OFF 0x02 /* Single frame ON/OFF selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define SGLF_TRIG 0x01 /* Single frame transfer trigger */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* HREF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define HREF_VSTART_SHIFT 6 /* VSTART LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define HREF_HSTART_SHIFT 4 /* HSTART 2 LSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define HREF_VSIZE_SHIFT 2 /* VSIZE LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define HREF_HSIZE_SHIFT 0 /* HSIZE 2 LSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* EXHCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define EXHCH_VSIZE_SHIFT 2 /* VOUTSIZE LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define EXHCH_HSIZE_SHIFT 0 /* HOUTSIZE 2 LSBs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* DSP_CTRL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define FIFO_ON 0x80 /* FIFO enable/disable selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define UV_ON_OFF 0x40 /* UV adjust function ON/OFF selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define YUV444_2_422 0x20 /* YUV444 to 422 UV channel option selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define CLR_MTRX_ON_OFF 0x10 /* Color matrix ON/OFF selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define INTPLT_ON_OFF 0x08 /* Interpolation ON/OFF selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define GMM_ON_OFF 0x04 /* Gamma function ON/OFF selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define AUTO_BLK_ON_OFF 0x02 /* Black defect auto correction ON/OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define AUTO_WHT_ON_OFF 0x01 /* White define auto correction ON/OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* DSP_CTRL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define UV_MASK 0x80 /* UV output sequence option */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define UV_ON 0x80 /* ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define UV_OFF 0x00 /* OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define CBAR_MASK 0x20 /* DSP Color bar mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define CBAR_ON 0x20 /* ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define CBAR_OFF 0x00 /* OFF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* DSP_CTRL4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DSP_OFMT_YUV 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define DSP_OFMT_RGB 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define DSP_OFMT_RAW8 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define DSP_OFMT_RAW10 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* DSPAUTO (DSP Auto Function ON/OFF Control) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define AWB_ACTRL 0x80 /* AWB auto threshold control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define DENOISE_ACTRL 0x40 /* De-noise auto threshold control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define EDGE_ACTRL 0x20 /* Edge enhancement auto strength control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define UV_ACTRL 0x10 /* UV adjust auto slope control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SCAL0_ACTRL 0x08 /* Auto scaling factor control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SCAL1_2_ACTRL 0x04 /* Auto scaling factor control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define OV772X_MAX_WIDTH VGA_WIDTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define OV772X_MAX_HEIGHT VGA_HEIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define OV7720 0x7720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define OV7725 0x7721
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define VERSION(pid, ver) ((pid << 8) | (ver & 0xFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * PLL multipliers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned int mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u8 com4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) } ov772x_pll[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { 1, PLL_BYPASS, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { 4, PLL_4x, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { 6, PLL_6x, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { 8, PLL_8x, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct ov772x_color_format {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) enum v4l2_colorspace colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u8 dsp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u8 dsp4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u8 com3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u8 com7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct ov772x_win_size {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned char com7_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) unsigned int sizeimage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct v4l2_rect rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct ov772x_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct ov772x_camera_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct gpio_desc *rstb_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) const struct ov772x_color_format *cfmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) const struct ov772x_win_size *win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct v4l2_ctrl *vflip_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct v4l2_ctrl *hflip_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* band_filter = COM8[5] ? 256 - BDBASE : 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct v4l2_ctrl *band_filter_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned int fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* lock to protect power_count and streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) int power_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) int streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #ifdef CONFIG_MEDIA_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * supported color format list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static const struct ov772x_color_format ov772x_cfmts[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) .code = MEDIA_BUS_FMT_YUYV8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) .dsp3 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) .dsp4 = DSP_OFMT_YUV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) .com3 = SWAP_YUV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) .com7 = OFMT_YUV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) .code = MEDIA_BUS_FMT_YVYU8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .dsp3 = UV_ON,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .dsp4 = DSP_OFMT_YUV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .com3 = SWAP_YUV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .com7 = OFMT_YUV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .code = MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .dsp3 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .dsp4 = DSP_OFMT_YUV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .com3 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .com7 = OFMT_YUV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .dsp3 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .dsp4 = DSP_OFMT_YUV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .com3 = SWAP_RGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .com7 = FMT_RGB555 | OFMT_RGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .code = MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .dsp3 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .dsp4 = DSP_OFMT_YUV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .com3 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .com7 = FMT_RGB555 | OFMT_RGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .code = MEDIA_BUS_FMT_RGB565_2X8_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .dsp3 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .dsp4 = DSP_OFMT_YUV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .com3 = SWAP_RGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .com7 = FMT_RGB565 | OFMT_RGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .code = MEDIA_BUS_FMT_RGB565_2X8_BE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .dsp3 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .dsp4 = DSP_OFMT_YUV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .com3 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .com7 = FMT_RGB565 | OFMT_RGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Setting DSP4 to DSP_OFMT_RAW8 still gives 10-bit output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * regardless of the COM7 value. We can thus only support 10-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * Bayer until someone figures it out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .code = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .dsp3 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .dsp4 = DSP_OFMT_RAW10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .com3 = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .com7 = SENSOR_RAW | OFMT_BRAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * window size list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const struct ov772x_win_size ov772x_win_sizes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .name = "VGA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .com7_bit = SLCT_VGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .sizeimage = 510 * 748,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .rect = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .left = 140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .top = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .width = VGA_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .height = VGA_HEIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .name = "QVGA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .com7_bit = SLCT_QVGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .sizeimage = 278 * 576,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .rect = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .left = 252,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .top = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .width = QVGA_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .height = QVGA_HEIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) * frame rate settings lists
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static const unsigned int ov772x_frame_intervals[] = { 5, 10, 15, 20, 30, 60 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * general function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) static struct ov772x_priv *to_ov772x(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return container_of(sd, struct ov772x_priv, subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static int ov772x_reset(struct ov772x_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) ret = regmap_write(priv->regmap, COM7, SCCB_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) usleep_range(1000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return regmap_update_bits(priv->regmap, COM2, SOFT_SLEEP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) SOFT_SLEEP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * subdev ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static int ov772x_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct ov772x_priv *priv = to_ov772x(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) if (priv->streaming == enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) ret = regmap_update_bits(priv->regmap, COM2, SOFT_SLEEP_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) enable ? 0 : SOFT_SLEEP_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) dev_dbg(&client->dev, "format %d, win %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) priv->cfmt->code, priv->win->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) priv->streaming = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static unsigned int ov772x_select_fps(struct ov772x_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct v4l2_fract *tpf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned int fps = tpf->numerator ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) tpf->denominator / tpf->numerator :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) tpf->denominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) unsigned int best_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned int diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) unsigned int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Approximate to the closest supported frame interval. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) best_diff = ~0L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) for (i = 0, idx = 0; i < ARRAY_SIZE(ov772x_frame_intervals); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) diff = abs(fps - ov772x_frame_intervals[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (diff < best_diff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) best_diff = diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return ov772x_frame_intervals[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static int ov772x_set_frame_rate(struct ov772x_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) unsigned int fps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) const struct ov772x_color_format *cfmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) const struct ov772x_win_size *win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) unsigned long fin = clk_get_rate(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) unsigned int best_diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) unsigned int fsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) unsigned int pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) unsigned int diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) u8 clkrc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u8 com4 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Use image size (with blankings) to calculate desired pixel clock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) switch (cfmt->com7 & OFMT_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) case OFMT_BRAW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) fsize = win->sizeimage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) case OFMT_RGB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) case OFMT_YUV:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) fsize = win->sizeimage * 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) pclk = fps * fsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * Pixel clock generation circuit is pretty simple:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) * Fin -> [ / CLKRC_div] -> [ * PLL_mult] -> pclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * Try to approximate the desired pixel clock testing all available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * PLL multipliers (1x, 4x, 6x, 8x) and calculate corresponding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * divisor with:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * div = PLL_mult * Fin / pclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * and re-calculate the pixel clock using it:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * pclk = Fin * PLL_mult / CLKRC_div
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * Choose the PLL_mult and CLKRC_div pair that gives a pixel clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * closer to the desired one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * The desired pixel clock is calculated using a known frame size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * (blanking included) and FPS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) best_diff = ~0L;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) for (i = 0; i < ARRAY_SIZE(ov772x_pll); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) unsigned int pll_mult = ov772x_pll[i].mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) unsigned int pll_out = pll_mult * fin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) unsigned int t_pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) unsigned int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (pll_out < pclk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) div = DIV_ROUND_CLOSEST(pll_out, pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) t_pclk = DIV_ROUND_CLOSEST(fin * pll_mult, div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) diff = abs(pclk - t_pclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (diff < best_diff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) best_diff = diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) clkrc = CLKRC_DIV(div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) com4 = ov772x_pll[i].com4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret = regmap_write(priv->regmap, COM4, com4 | COM4_RESERVED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) ret = regmap_write(priv->regmap, CLKRC, clkrc | CLKRC_RESERVED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int ov772x_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct v4l2_subdev_frame_interval *ival)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct ov772x_priv *priv = to_ov772x(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) struct v4l2_fract *tpf = &ival->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) tpf->numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) tpf->denominator = priv->fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static int ov772x_s_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct v4l2_subdev_frame_interval *ival)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct ov772x_priv *priv = to_ov772x(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct v4l2_fract *tpf = &ival->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) unsigned int fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (priv->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) fps = ov772x_select_fps(priv, tpf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * If the device is not powered up by the host driver do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * not apply any changes to H/W at this time. Instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * the frame rate will be restored right after power-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (priv->power_count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ret = ov772x_set_frame_rate(priv, fps, priv->cfmt, priv->win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) tpf->numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) tpf->denominator = fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) priv->fps = fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static int ov772x_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct ov772x_priv *priv = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct ov772x_priv, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct regmap *regmap = priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) /* v4l2_ctrl_lock() locks our own mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * If the device is not powered up by the host driver do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * not apply any controls to H/W at this time. Instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * the controls will be restored right after power-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (priv->power_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) val = ctrl->val ? VFLIP_IMG : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (priv->info && (priv->info->flags & OV772X_FLAG_VFLIP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) val ^= VFLIP_IMG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return regmap_update_bits(regmap, COM3, VFLIP_IMG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) val = ctrl->val ? HFLIP_IMG : 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (priv->info && (priv->info->flags & OV772X_FLAG_HFLIP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) val ^= HFLIP_IMG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return regmap_update_bits(regmap, COM3, HFLIP_IMG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case V4L2_CID_BAND_STOP_FILTER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (!ctrl->val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Switch the filter off, it is on now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) ret = regmap_update_bits(regmap, BDBASE, 0xff, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) ret = regmap_update_bits(regmap, COM8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) BNDF_ON_OFF, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* Switch the filter on, set AEC low limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) val = 256 - ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) ret = regmap_update_bits(regmap, COM8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) BNDF_ON_OFF, BNDF_ON_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) ret = regmap_update_bits(regmap, BDBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) 0xff, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) static int ov772x_g_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct ov772x_priv *priv = to_ov772x(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) reg->size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (reg->reg > 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = regmap_read(priv->regmap, reg->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) reg->val = (__u64)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int ov772x_s_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct ov772x_priv *priv = to_ov772x(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) if (reg->reg > 0xff ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) reg->val > 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) return regmap_write(priv->regmap, reg->reg, reg->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static int ov772x_power_on(struct ov772x_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (priv->clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ret = clk_prepare_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (priv->pwdn_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) gpiod_set_value(priv->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * FIXME: The reset signal is connected to a shared GPIO on some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * platforms (namely the SuperH Migo-R). Until a framework becomes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * available to handle this cleanly, request the GPIO temporarily
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * to avoid conflicts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) priv->rstb_gpio = gpiod_get_optional(&client->dev, "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (IS_ERR(priv->rstb_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) dev_info(&client->dev, "Unable to get GPIO \"reset\"");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return PTR_ERR(priv->rstb_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (priv->rstb_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) gpiod_set_value(priv->rstb_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) gpiod_set_value(priv->rstb_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) gpiod_put(priv->rstb_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static int ov772x_power_off(struct ov772x_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) clk_disable_unprepare(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (priv->pwdn_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) gpiod_set_value(priv->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static int ov772x_set_params(struct ov772x_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) const struct ov772x_color_format *cfmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) const struct ov772x_win_size *win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) static int ov772x_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) struct ov772x_priv *priv = to_ov772x(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) /* If the power count is modified from 0 to != 0 or from != 0 to 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * update the power state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (priv->power_count == !on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ret = ov772x_power_on(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * Restore the format, the frame rate, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * the controls
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ret = ov772x_set_params(priv, priv->cfmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) priv->win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ret = ov772x_power_off(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* Update the power count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) priv->power_count += on ? 1 : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) WARN(priv->power_count < 0, "Unbalanced power count\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) WARN(priv->power_count > 1, "Duplicated s_power call\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static const struct ov772x_win_size *ov772x_select_win(u32 width, u32 height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) const struct ov772x_win_size *win = &ov772x_win_sizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) u32 best_diff = UINT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) for (i = 0; i < ARRAY_SIZE(ov772x_win_sizes); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) u32 diff = abs(width - ov772x_win_sizes[i].rect.width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) + abs(height - ov772x_win_sizes[i].rect.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (diff < best_diff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) best_diff = diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) win = &ov772x_win_sizes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) static void ov772x_select_params(const struct v4l2_mbus_framefmt *mf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) const struct ov772x_color_format **cfmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) const struct ov772x_win_size **win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) /* Select a format. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) *cfmt = &ov772x_cfmts[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) for (i = 0; i < ARRAY_SIZE(ov772x_cfmts); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (mf->code == ov772x_cfmts[i].code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) *cfmt = &ov772x_cfmts[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /* Select a window size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) *win = ov772x_select_win(mf->width, mf->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) static int ov772x_edgectrl(struct ov772x_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) struct regmap *regmap = priv->regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (!priv->info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (priv->info->edgectrl.strength & OV772X_MANUAL_EDGE_CTRL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * Manual Edge Control Mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * Edge auto strength bit is set by default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * Remove it when manual mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ret = regmap_update_bits(regmap, DSPAUTO, EDGE_ACTRL, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) ret = regmap_update_bits(regmap, EDGE_TRSHLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) OV772X_EDGE_THRESHOLD_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) priv->info->edgectrl.threshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ret = regmap_update_bits(regmap, EDGE_STRNGT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) OV772X_EDGE_STRENGTH_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) priv->info->edgectrl.strength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) } else if (priv->info->edgectrl.upper > priv->info->edgectrl.lower) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * Auto Edge Control Mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * Set upper and lower limit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) ret = regmap_update_bits(regmap, EDGE_UPPER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) OV772X_EDGE_UPPER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) priv->info->edgectrl.upper);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) ret = regmap_update_bits(regmap, EDGE_LOWER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) OV772X_EDGE_LOWER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) priv->info->edgectrl.lower);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static int ov772x_set_params(struct ov772x_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) const struct ov772x_color_format *cfmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) const struct ov772x_win_size *win)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) /* Reset hardware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ov772x_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) /* Edge Ctrl. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ret = ov772x_edgectrl(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* Format and window size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ret = regmap_write(priv->regmap, HSTART, win->rect.left >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) goto ov772x_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) ret = regmap_write(priv->regmap, HSIZE, win->rect.width >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) goto ov772x_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ret = regmap_write(priv->regmap, VSTART, win->rect.top >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) goto ov772x_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) ret = regmap_write(priv->regmap, VSIZE, win->rect.height >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) goto ov772x_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ret = regmap_write(priv->regmap, HOUTSIZE, win->rect.width >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) goto ov772x_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) ret = regmap_write(priv->regmap, VOUTSIZE, win->rect.height >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) goto ov772x_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) ret = regmap_write(priv->regmap, HREF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ((win->rect.top & 1) << HREF_VSTART_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ((win->rect.left & 3) << HREF_HSTART_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ((win->rect.height & 1) << HREF_VSIZE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ((win->rect.width & 3) << HREF_HSIZE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) goto ov772x_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) ret = regmap_write(priv->regmap, EXHCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ((win->rect.height & 1) << EXHCH_VSIZE_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) ((win->rect.width & 3) << EXHCH_HSIZE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) goto ov772x_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) /* Set DSP_CTRL3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) val = cfmt->dsp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ret = regmap_update_bits(priv->regmap, DSP_CTRL3, UV_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) goto ov772x_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /* DSP_CTRL4: AEC reference point and DSP output format. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (cfmt->dsp4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) ret = regmap_write(priv->regmap, DSP_CTRL4, cfmt->dsp4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) goto ov772x_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* Set COM3. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) val = cfmt->com3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (priv->info && (priv->info->flags & OV772X_FLAG_VFLIP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) val |= VFLIP_IMG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (priv->info && (priv->info->flags & OV772X_FLAG_HFLIP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) val |= HFLIP_IMG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (priv->vflip_ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) val ^= VFLIP_IMG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (priv->hflip_ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) val ^= HFLIP_IMG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) ret = regmap_update_bits(priv->regmap, COM3, SWAP_MASK | IMG_MASK, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) goto ov772x_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) /* COM7: Sensor resolution and output format control. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ret = regmap_write(priv->regmap, COM7, win->com7_bit | cfmt->com7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) goto ov772x_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) /* COM4, CLKRC: Set pixel clock and framerate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) ret = ov772x_set_frame_rate(priv, priv->fps, cfmt, win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) goto ov772x_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) /* Set COM8. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (priv->band_filter_ctrl->val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) unsigned short band_filter = priv->band_filter_ctrl->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ret = regmap_update_bits(priv->regmap, COM8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) BNDF_ON_OFF, BNDF_ON_OFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ret = regmap_update_bits(priv->regmap, BDBASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) 0xff, 256 - band_filter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) goto ov772x_set_fmt_error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ov772x_set_fmt_error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) ov772x_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static int ov772x_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct ov772x_priv *priv = to_ov772x(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) sel->r.left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) sel->r.top = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) switch (sel->target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) case V4L2_SEL_TGT_CROP_BOUNDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) case V4L2_SEL_TGT_CROP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) sel->r.width = priv->win->rect.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) sel->r.height = priv->win->rect.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static int ov772x_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) struct v4l2_mbus_framefmt *mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct ov772x_priv *priv = to_ov772x(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) mf->width = priv->win->rect.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) mf->height = priv->win->rect.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) mf->code = priv->cfmt->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) mf->colorspace = priv->cfmt->colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static int ov772x_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) struct ov772x_priv *priv = to_ov772x(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct v4l2_mbus_framefmt *mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) const struct ov772x_color_format *cfmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) const struct ov772x_win_size *win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) ov772x_select_params(mf, &cfmt, &win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) mf->code = cfmt->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) mf->width = win->rect.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) mf->height = win->rect.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) mf->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) mf->colorspace = cfmt->colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) mf->ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) mf->quantization = V4L2_QUANTIZATION_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) mf->xfer_func = V4L2_XFER_FUNC_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) cfg->try_fmt = *mf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) mutex_lock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (priv->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * If the device is not powered up by the host driver do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * not apply any changes to H/W at this time. Instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) * the format will be restored right after power-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (priv->power_count > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) ret = ov772x_set_params(priv, cfmt, win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) priv->win = win;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) priv->cfmt = cfmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) mutex_unlock(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) static int ov772x_video_probe(struct ov772x_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct i2c_client *client = v4l2_get_subdevdata(&priv->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) int pid, ver, midh, midl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) const char *devname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) ret = ov772x_power_on(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) /* Check and show product ID and manufacturer ID. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) ret = regmap_read(priv->regmap, PID, &pid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ret = regmap_read(priv->regmap, VER, &ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) switch (VERSION(pid, ver)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) case OV7720:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) devname = "ov7720";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) case OV7725:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) devname = "ov7725";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) "Product ID error %x:%x\n", pid, ver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ret = regmap_read(priv->regmap, MIDH, &midh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) ret = regmap_read(priv->regmap, MIDL, &midl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) dev_info(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) "%s Product ID %0x:%0x Manufacturer ID %x:%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) devname, pid, ver, midh, midl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) ret = v4l2_ctrl_handler_setup(&priv->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) ov772x_power_off(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static const struct v4l2_ctrl_ops ov772x_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .s_ctrl = ov772x_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static const struct v4l2_subdev_core_ops ov772x_subdev_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .log_status = v4l2_ctrl_subdev_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .unsubscribe_event = v4l2_event_subdev_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .g_register = ov772x_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) .s_register = ov772x_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) .s_power = ov772x_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) static int ov772x_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (fie->pad || fie->index >= ARRAY_SIZE(ov772x_frame_intervals))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (fie->width != VGA_WIDTH && fie->width != QVGA_WIDTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (fie->height != VGA_HEIGHT && fie->height != QVGA_HEIGHT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) fie->interval.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) fie->interval.denominator = ov772x_frame_intervals[fie->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) static int ov772x_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (code->pad || code->index >= ARRAY_SIZE(ov772x_cfmts))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) code->code = ov772x_cfmts[code->index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) static const struct v4l2_subdev_video_ops ov772x_subdev_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) .s_stream = ov772x_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) .s_frame_interval = ov772x_s_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) .g_frame_interval = ov772x_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static const struct v4l2_subdev_pad_ops ov772x_subdev_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) .enum_frame_interval = ov772x_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) .enum_mbus_code = ov772x_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) .get_selection = ov772x_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) .get_fmt = ov772x_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) .set_fmt = ov772x_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static const struct v4l2_subdev_ops ov772x_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) .core = &ov772x_subdev_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) .video = &ov772x_subdev_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) .pad = &ov772x_subdev_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) * i2c_driver function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) static int ov772x_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct ov772x_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) static const struct regmap_config ov772x_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) .val_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) .max_register = DSPAUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (!client->dev.of_node && !client->dev.platform_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) "Missing ov772x platform data for non-DT device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) priv->regmap = devm_regmap_init_sccb(client, &ov772x_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) if (IS_ERR(priv->regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) dev_err(&client->dev, "Failed to allocate register map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) return PTR_ERR(priv->regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) priv->info = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) mutex_init(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) v4l2_i2c_subdev_init(&priv->subdev, client, &ov772x_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) priv->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) v4l2_ctrl_handler_init(&priv->hdl, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /* Use our mutex for the controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) priv->hdl.lock = &priv->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) priv->vflip_ctrl = v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) priv->hflip_ctrl = v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) priv->band_filter_ctrl = v4l2_ctrl_new_std(&priv->hdl, &ov772x_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) V4L2_CID_BAND_STOP_FILTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) 0, 256, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) priv->subdev.ctrl_handler = &priv->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (priv->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) ret = priv->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) goto error_mutex_destroy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) priv->clk = clk_get(&client->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) dev_err(&client->dev, "Unable to get xclk clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) ret = PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) goto error_ctrl_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) priv->pwdn_gpio = gpiod_get_optional(&client->dev, "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (IS_ERR(priv->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) dev_info(&client->dev, "Unable to get GPIO \"powerdown\"");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) ret = PTR_ERR(priv->pwdn_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) goto error_clk_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) ret = ov772x_video_probe(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) goto error_gpio_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #ifdef CONFIG_MEDIA_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) priv->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) priv->subdev.entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) ret = media_entity_pads_init(&priv->subdev.entity, 1, &priv->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) goto error_gpio_put;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) priv->cfmt = &ov772x_cfmts[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) priv->win = &ov772x_win_sizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) priv->fps = 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) ret = v4l2_async_register_subdev(&priv->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) goto error_entity_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) error_entity_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) media_entity_cleanup(&priv->subdev.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) error_gpio_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (priv->pwdn_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) gpiod_put(priv->pwdn_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) error_clk_put:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) clk_put(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) error_ctrl_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) v4l2_ctrl_handler_free(&priv->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) error_mutex_destroy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) mutex_destroy(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) static int ov772x_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) struct ov772x_priv *priv = to_ov772x(i2c_get_clientdata(client));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) media_entity_cleanup(&priv->subdev.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) clk_put(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (priv->pwdn_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) gpiod_put(priv->pwdn_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) v4l2_async_unregister_subdev(&priv->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) v4l2_ctrl_handler_free(&priv->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) mutex_destroy(&priv->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) static const struct i2c_device_id ov772x_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) { "ov772x", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) MODULE_DEVICE_TABLE(i2c, ov772x_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) static const struct of_device_id ov772x_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) { .compatible = "ovti,ov7725", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) { .compatible = "ovti,ov7720", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) MODULE_DEVICE_TABLE(of, ov772x_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) static struct i2c_driver ov772x_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) .name = "ov772x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) .of_match_table = ov772x_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .probe_new = ov772x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .remove = ov772x_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .id_table = ov772x_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) module_i2c_driver(ov772x_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) MODULE_DESCRIPTION("V4L2 driver for OV772x image sensor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) MODULE_AUTHOR("Kuninori Morimoto");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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