Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * ov7725 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2018 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define REG_CHIP_ID_H			0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define REG_CHIP_ID_L			0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CHIP_ID_H			0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CHIP_ID_L			0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define REG_NULL			0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define ov7725_XVCLK_FREQ		24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) static const char * const ov7725_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	"avdd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	"dovdd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	"dvdd",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define ov7725_NUM_SUPPLIES ARRAY_SIZE(ov7725_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u8 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) struct ov7725_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) struct ov7725 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct i2c_client	*client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct clk		*xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	struct gpio_desc	*reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	struct gpio_desc	*pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct regulator_bulk_data supplies[ov7725_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	bool			streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	struct mutex		mutex; /* lock to serialize v4l2 callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct v4l2_subdev	subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	struct media_pad	pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	const struct ov7725_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define to_ov7725(sd) container_of(sd, struct ov7725, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* 30fps at 24MHz input clock,4x maximum gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static struct regval ov7725_640x480_30fps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	{0x12, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	{0x3d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	{0x17, 0x25}, /* Raw: 0x17,0x22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	{0x18, 0xa4}, /* Raw: 0x18,0xa4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	{0x19, 0x06}, /* Raw: 0x19,0x07 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	{0x1a, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	{0x32, 0x60}, /* Raw: 0x32,0x00 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	{0x29, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	{0x2c, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	{0x2a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	{0x11, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	{0x42, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	{0x4d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	{0x63, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	{0x64, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	{0x65, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	{0x66, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	{0x67, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	{0x13, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	{0x0d, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	{0x0f, 0xc5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	{0x14, 0x17}, /* 0x14,0x11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	{0x22, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	{0x23, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	{0x24, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	{0x25, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	{0x26, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	{0x2b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	{0x6b, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	{0x13, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	{0x90, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	{0x91, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	{0x92, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	{0x93, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	{0x94, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	{0x95, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	{0x96, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	{0x97, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	{0x98, 0x2f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	{0x99, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	{0x9a, 0x9e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	{0x9b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	{0x9c, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	{0x9e, 0x81},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	{0xa6, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	{0x7e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	{0x7f, 0x16},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	{0x80, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	{0x81, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	{0x82, 0x61},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	{0x83, 0x6f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	{0x84, 0x7b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	{0x85, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	{0x86, 0x8e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	{0x87, 0x97},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	{0x88, 0xa4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	{0x89, 0xaf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	{0x8a, 0xc5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	{0x8b, 0xd7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	{0x8c, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	{0x8d, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	{0x33, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	{0x22, 0x99},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	{0x23, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	{0x4a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	{0x49, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	{0x47, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	{0x4b, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	{0x4c, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	{0x46, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	{0x0e, 0x65},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	{0x0c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	{REG_NULL, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static struct regval ov7725_1600x1200_7fps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	{REG_NULL, 0x0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) static const struct ov7725_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 		.width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 		.height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		.reg_list = ov7725_640x480_30fps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		.width = 1600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		.height = 1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		.reg_list = ov7725_1600x1200_7fps,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static int ov7725_write_reg(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	ret = i2c_smbus_write_byte_data(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 		dev_err(&client->dev, "write reg error: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static int ov7725_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		ret = ov7725_write_reg(client, regs[i].addr, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static inline u8 ov7725_read_reg(struct i2c_client *client, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	return i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static int ov7725_get_reso_dist(const struct ov7725_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 		abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static const struct ov7725_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ov7725_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 		dist = ov7725_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int ov7725_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			   struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			   struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	struct ov7725 *ov7725 = to_ov7725(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	const struct ov7725_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	mutex_lock(&ov7725->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	mode = ov7725_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	fmt->format.code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	fmt->format.colorspace = V4L2_COLORSPACE_JPEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 		*v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 		mutex_unlock(&ov7725->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 		return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		ov7725->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	mutex_unlock(&ov7725->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int ov7725_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 			   struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			   struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	struct ov7725 *ov7725 = to_ov7725(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	const struct ov7725_mode *mode = ov7725->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	mutex_lock(&ov7725->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 		fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 		mutex_unlock(&ov7725->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 		return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 		fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 		fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		fmt->format.code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 		fmt->format.colorspace = V4L2_COLORSPACE_JPEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	mutex_unlock(&ov7725->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static int ov7725_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 				  struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 				  struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	if (code->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	code->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static int ov7725_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 				    struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 				    struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	u32 index = fse->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	if (index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	fse->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	fse->min_width  = supported_modes[index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	fse->max_width  = supported_modes[index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	fse->max_height = supported_modes[index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	fse->min_height = supported_modes[index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static int __ov7725_power_on(struct ov7725 *ov7725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	struct device *dev = &ov7725->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	if (!IS_ERR(ov7725->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 		gpiod_set_value_cansleep(ov7725->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	ret = regulator_bulk_enable(ov7725_NUM_SUPPLIES, ov7725->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 		dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	if (!IS_ERR(ov7725->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 		ret = clk_prepare_enable(ov7725->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	if (!IS_ERR(ov7725->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 		gpiod_set_value_cansleep(ov7725->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	if (!IS_ERR(ov7725->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		gpiod_set_value_cansleep(ov7725->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static void __ov7725_power_off(struct ov7725 *ov7725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	if (!IS_ERR(ov7725->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		gpiod_set_value_cansleep(ov7725->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 	if (!IS_ERR(ov7725->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 		gpiod_set_value_cansleep(ov7725->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	if (!IS_ERR(ov7725->xvclk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 		clk_disable_unprepare(ov7725->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	regulator_bulk_disable(ov7725_NUM_SUPPLIES, ov7725->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int ov7725_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	struct ov7725 *ov7725 = to_ov7725(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	struct i2c_client *client = ov7725->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 	mutex_lock(&ov7725->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 	on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	if (on == ov7725->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 		ret = pm_runtime_get_sync(&ov7725->client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 			pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 			goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		ret = ov7725_write_array(ov7725->client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) 					  ov7725->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 		if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 			pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 			goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	ov7725->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 	mutex_unlock(&ov7725->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static int ov7725_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	struct ov7725 *ov7725 = to_ov7725(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 	struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 	const struct ov7725_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	mutex_lock(&ov7725->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 	try_fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 	try_fmt->colorspace = V4L2_COLORSPACE_JPEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	mutex_unlock(&ov7725->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static int ov7725_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	struct ov7725 *ov7725 = to_ov7725(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	return __ov7725_power_on(ov7725);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static int ov7725_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	struct ov7725 *ov7725 = to_ov7725(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	__ov7725_power_off(ov7725);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static const struct dev_pm_ops ov7725_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	SET_RUNTIME_PM_OPS(ov7725_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 			   ov7725_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const struct v4l2_subdev_video_ops ov7725_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	.s_stream = ov7725_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const struct v4l2_subdev_pad_ops ov7725_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	.enum_mbus_code = ov7725_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	.enum_frame_size = ov7725_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	.get_fmt = ov7725_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 	.set_fmt = ov7725_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) static const struct v4l2_subdev_ops ov7725_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	.video	= &ov7725_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	.pad	= &ov7725_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) static const struct v4l2_subdev_internal_ops ov7725_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 	.open = ov7725_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static int ov7725_check_sensor_id(struct ov7725 *ov7725,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 				  struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	struct device *dev = &ov7725->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 	u8 id_h = 0, id_l = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	id_h = ov7725_read_reg(client, REG_CHIP_ID_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	id_l = ov7725_read_reg(client, REG_CHIP_ID_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 	if (id_h != CHIP_ID_H && id_l != CHIP_ID_L) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 		dev_err(dev, "Wrong camera sensor id(0x%02x%02x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 			id_h, id_l);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 	dev_info(dev, "Detected ov7725 (0x%02x%02x) sensor\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 		CHIP_ID_H, CHIP_ID_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int ov7725_configure_regulators(struct ov7725 *ov7725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) 	u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	for (i = 0; i < ov7725_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 		ov7725->supplies[i].supply = ov7725_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 	return devm_regulator_bulk_get(&ov7725->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 				       ov7725_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 				       ov7725->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static int ov7725_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 			 const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	struct ov7725 *ov7725;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	ov7725 = devm_kzalloc(dev, sizeof(*ov7725), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) 	if (!ov7725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 		return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 	ov7725->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	ov7725->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 	ov7725->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) 	if (IS_ERR(ov7725->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 		dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 	ret = clk_set_rate(ov7725->xvclk, ov7725_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 		dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	if (clk_get_rate(ov7725->xvclk) != ov7725_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 		dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 	ov7725->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	if (IS_ERR(ov7725->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 		dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 	ov7725->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	if (IS_ERR(ov7725->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 		dev_warn(dev, "Failed to get ov7725-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	ret = ov7725_configure_regulators(ov7725);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		dev_warn(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	mutex_init(&ov7725->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	v4l2_i2c_subdev_init(&ov7725->subdev, client, &ov7725_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	ret = __ov7725_power_on(ov7725);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 		goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	ret = ov7725_check_sensor_id(ov7725, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 		goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	ov7725->subdev.internal_ops = &ov7725_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	ov7725->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	ov7725->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	ov7725->subdev.entity.type = MEDIA_ENT_T_V4L2_SUBDEV_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	ret = media_entity_init(&ov7725->subdev.entity, 1, &ov7725->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 		goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 	ret = v4l2_async_register_subdev(&ov7725->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 		dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 		goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 	pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 	pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	media_entity_cleanup(&ov7725->subdev.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	__ov7725_power_off(ov7725);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 	mutex_destroy(&ov7725->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) static int ov7725_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	struct ov7725 *ov7725 = to_ov7725(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 	v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 	media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	mutex_destroy(&ov7725->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 	if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 		__ov7725_power_off(ov7725);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static const struct of_device_id ov7725_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 	{ .compatible = "ovti,ov7725" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) MODULE_DEVICE_TABLE(of, ov7725_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static const struct i2c_device_id ov7725_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	{"ovti,ov7251", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) 	{},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static struct i2c_driver ov7725_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 	.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 		.name = "ov7725",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 		.pm = &ov7725_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 		.of_match_table = of_match_ptr(ov7725_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 	.probe		= ov7725_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 	.remove		= ov7725_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	.id_table	= ov7725_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	return i2c_add_driver(&ov7725_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) 	i2c_del_driver(&ov7725_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) MODULE_DESCRIPTION("OmniVision ov7725 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) MODULE_LICENSE("GPL v2");