^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * A V4L2 driver for OmniVision OV7670 cameras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2006 One Laptop Per Child Association, Inc. Written
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * by Jonathan Corbet with substantial inspiration from Mark
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * McClelland's ovcamchip code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/videodev2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-image-sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/i2c/ov7670.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static bool debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) module_param(debug, bool, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MODULE_PARM_DESC(debug, "Debug level (0-1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * The 7670 sits on i2c with ID 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OV7670_I2C_ADDR 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PLL_FACTOR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_BLUE 0x01 /* blue gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define REG_RED 0x02 /* red gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_COM1 0x04 /* Control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define COM1_CCIR656 0x40 /* CCIR656 enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define REG_BAVE 0x05 /* U/B Average level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_GbAVE 0x06 /* Y/Gb Average level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_AECHH 0x07 /* AEC MS 5 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_RAVE 0x08 /* V/R Average level */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_COM2 0x09 /* Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define COM2_SSLEEP 0x10 /* Soft sleep mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define REG_PID 0x0a /* Product ID MSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define REG_VER 0x0b /* Product ID LSB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REG_COM3 0x0c /* Control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define COM3_SWAP 0x40 /* Byte swap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define COM3_SCALEEN 0x08 /* Enable scaling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define REG_COM4 0x0d /* Control 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_COM5 0x0e /* All "reserved" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define REG_COM6 0x0f /* Control 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define REG_AECH 0x10 /* More bits of AEC value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define REG_CLKRC 0x11 /* Clocl control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLK_EXT 0x40 /* Use external clock directly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLK_SCALE 0x3f /* Mask for internal clock scale */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define REG_COM7 0x12 /* Control 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define COM7_RESET 0x80 /* Register reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define COM7_FMT_MASK 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define COM7_FMT_VGA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define COM7_FMT_CIF 0x20 /* CIF format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define COM7_FMT_QVGA 0x10 /* QVGA format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define COM7_FMT_QCIF 0x08 /* QCIF format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define COM7_YUV 0x00 /* YUV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define COM7_BAYER 0x01 /* Bayer format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define COM7_PBAYER 0x05 /* "Processed bayer" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define REG_COM8 0x13 /* Control 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define COM8_BFILT 0x20 /* Band filter enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define COM8_AGC 0x04 /* Auto gain enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define COM8_AWB 0x02 /* White balance enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define COM8_AEC 0x01 /* Auto exposure enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define REG_COM9 0x14 /* Control 9 - gain ceiling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define REG_COM10 0x15 /* Control 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define COM10_HREF_REV 0x08 /* Reverse HREF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define COM10_VS_NEG 0x02 /* VSYNC negative */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define COM10_HS_NEG 0x01 /* HSYNC negative */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define REG_HSTART 0x17 /* Horiz start high bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define REG_HSTOP 0x18 /* Horiz stop high bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define REG_VSTART 0x19 /* Vert start high bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define REG_VSTOP 0x1a /* Vert stop high bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define REG_PSHFT 0x1b /* Pixel delay after HREF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define REG_MIDH 0x1c /* Manuf. ID high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define REG_MIDL 0x1d /* Manuf. ID low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define REG_MVFP 0x1e /* Mirror / vflip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MVFP_MIRROR 0x20 /* Mirror image */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MVFP_FLIP 0x10 /* Vertical flip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define REG_AEW 0x24 /* AGC upper limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define REG_AEB 0x25 /* AGC lower limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define REG_HSYST 0x30 /* HSYNC rising edge delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define REG_HREF 0x32 /* HREF pieces */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define REG_TSLB 0x3a /* lots of stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define REG_COM11 0x3b /* Control 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define COM11_NIGHT 0x80 /* NIght mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define COM11_NMFR 0x60 /* Two bit NM frame rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define COM11_50HZ 0x08 /* Manual 50Hz select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define COM11_EXP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define REG_COM12 0x3c /* Control 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define COM12_HREF 0x80 /* HREF always */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define REG_COM13 0x3d /* Control 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define COM13_GAMMA 0x80 /* Gamma enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define REG_COM14 0x3e /* Control 14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define REG_EDGE 0x3f /* Edge enhancement factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define REG_COM15 0x40 /* Control 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define COM15_R10F0 0x00 /* Data range 10 to F0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define COM15_R01FE 0x80 /* 01 to FE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define COM15_R00FF 0xc0 /* 00 to FF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define COM15_RGB565 0x10 /* RGB565 output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define COM15_RGB555 0x30 /* RGB555 output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define REG_COM16 0x41 /* Control 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define COM16_AWBGAIN 0x08 /* AWB gain enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define REG_COM17 0x42 /* Control 17 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define COM17_CBAR 0x08 /* DSP Color bar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * This matrix defines how the colors are generated, must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * tweaked to adjust hue and saturation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * They are nine-bit signed quantities, with the sign bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * stored in 0x58. Sign for v-red is bit 0, and up from there.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define REG_CMATRIX_BASE 0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CMATRIX_LEN 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define REG_CMATRIX_SIGN 0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define REG_BRIGHT 0x55 /* Brightness */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define REG_CONTRAS 0x56 /* Contrast control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define REG_GFIX 0x69 /* Fix gain control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define REG_DBLV 0x6b /* PLL control an debugging */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DBLV_BYPASS 0x0a /* Bypass PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DBLV_X4 0x4a /* clock x4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DBLV_X6 0x8a /* clock x6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DBLV_X8 0xca /* clock x8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define REG_SCALING_XSC 0x70 /* Test pattern and horizontal scale factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TEST_PATTTERN_0 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define REG_SCALING_YSC 0x71 /* Test pattern and vertical scale factor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TEST_PATTTERN_1 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define REG_REG76 0x76 /* OV's name */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define R76_WHTPCOR 0x40 /* White pixel correction enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define REG_RGB444 0x8c /* RGB 444 control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define R444_RGBX 0x01 /* Empty nibble at end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define REG_BD60MAX 0xab /* 60hz banding step limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) enum ov7670_model {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) MODEL_OV7670 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) MODEL_OV7675,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct ov7670_win_size {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned char com7_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) int hstart; /* Start/stop values for the camera. Note */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int hstop; /* that they do not always make complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) int vstart; /* sense to humans, but evidently the sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) int vstop; /* will do the right thing... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct regval_list *regs; /* Regs to tweak */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct ov7670_devtype {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* formats supported for each model */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct ov7670_win_size *win_sizes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) unsigned int n_win_sizes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* callbacks for frame rate control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * Information we maintain about a known sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct ov7670_format_struct; /* coming later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct ov7670_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* gain cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct v4l2_ctrl *auto_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct v4l2_ctrl *gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* exposure cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct v4l2_ctrl *auto_exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* saturation/hue cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct v4l2_ctrl *saturation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct v4l2_ctrl *hue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct v4l2_mbus_framefmt format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct ov7670_format_struct *fmt; /* Current format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct ov7670_win_size *wsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct gpio_desc *resetb_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) unsigned int mbus_config; /* Media bus configuration flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int min_width; /* Filter out smaller sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int min_height; /* Filter out smaller sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int clock_speed; /* External clock speed (MHz) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u8 clkrc; /* Clock divider value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) bool use_smbus; /* Use smbus I/O instead of I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) bool pll_bypass;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) bool pclk_hb_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) const struct ov7670_devtype *devtype; /* Device specifics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static inline struct ov7670_info *to_state(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) return container_of(sd, struct ov7670_info, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * The default register settings, as obtained from OmniVision. There
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * is really no making sense of most of these - lots of "reserved" values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * and such.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * These settings give VGA YUYV.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct regval_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) unsigned char reg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) unsigned char value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) static struct regval_list ov7670_default_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { REG_COM7, COM7_RESET },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Clock scale: 3 = 15fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * 2 = 20fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * 1 = 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { REG_TSLB, 0x04 }, /* OV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { REG_COM7, 0 }, /* VGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * Set the hardware window. These values from OV don't entirely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * make sense - hstop is less than hstart. But they work...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { REG_COM3, 0 }, { REG_COM14, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Mystery scaling numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { REG_SCALING_XSC, 0x3a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { REG_SCALING_YSC, 0x35 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { 0x72, 0x11 }, { 0x73, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { 0xa2, 0x02 }, { REG_COM10, 0x0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Gamma curve values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { 0x7a, 0x20 }, { 0x7b, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { 0x7c, 0x1e }, { 0x7d, 0x35 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { 0x7e, 0x5a }, { 0x7f, 0x69 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { 0x80, 0x76 }, { 0x81, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { 0x82, 0x88 }, { 0x83, 0x8f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { 0x84, 0x96 }, { 0x85, 0xa3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { 0x86, 0xaf }, { 0x87, 0xc4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { 0x88, 0xd7 }, { 0x89, 0xe8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* AGC and AEC parameters. Note we start by disabling those features,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) then turn them only after tweaking the values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { REG_GAIN, 0 }, { REG_AECH, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { REG_COM4, 0x40 }, /* magic reserved bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { REG_AEW, 0x95 }, { REG_AEB, 0x33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { REG_HAECC7, 0x94 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* Almost all of these are magic "reserved" values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { REG_COM5, 0x61 }, { REG_COM6, 0x4b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { 0x16, 0x02 }, { REG_MVFP, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { 0x21, 0x02 }, { 0x22, 0x91 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { 0x29, 0x07 }, { 0x33, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { 0x35, 0x0b }, { 0x37, 0x1d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { 0x38, 0x71 }, { 0x39, 0x2a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { REG_COM12, 0x78 }, { 0x4d, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { 0x4e, 0x20 }, { REG_GFIX, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { 0x6b, 0x4a }, { 0x74, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { 0x8d, 0x4f }, { 0x8e, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { 0x8f, 0 }, { 0x90, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { 0x91, 0 }, { 0x96, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { 0x9a, 0 }, { 0xb0, 0x84 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { 0xb1, 0x0c }, { 0xb2, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { 0xb3, 0x82 }, { 0xb8, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /* More reserved magic, some of which tweaks white balance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { 0x43, 0x0a }, { 0x44, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { 0x45, 0x34 }, { 0x46, 0x58 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { 0x47, 0x28 }, { 0x48, 0x3a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { 0x59, 0x88 }, { 0x5a, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { 0x5b, 0x44 }, { 0x5c, 0x67 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { 0x5d, 0x49 }, { 0x5e, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { 0x6c, 0x0a }, { 0x6d, 0x55 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { 0x6a, 0x40 }, { REG_BLUE, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { REG_RED, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* Matrix coefficients */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { 0x4f, 0x80 }, { 0x50, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { 0x51, 0 }, { 0x52, 0x22 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { 0x53, 0x5e }, { 0x54, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { 0x58, 0x9e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { 0x75, 0x05 }, { 0x76, 0xe1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { 0x4c, 0 }, { 0x77, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { REG_COM13, 0xc3 }, { 0x4b, 0x09 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { 0xc9, 0x60 }, { REG_COM16, 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { 0x56, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { 0xa4, 0x88 }, { 0x96, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { 0x97, 0x30 }, { 0x98, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { 0x99, 0x30 }, { 0x9a, 0x84 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { 0x9b, 0x29 }, { 0x9c, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { 0x9d, 0x4c }, { 0x9e, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { 0x78, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /* Extra-weird stuff. Some sort of multiplexor register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { 0x79, 0x01 }, { 0xc8, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { 0x79, 0x0f }, { 0xc8, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { 0x79, 0x10 }, { 0xc8, 0x7e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { 0x79, 0x0a }, { 0xc8, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { 0x79, 0x0b }, { 0xc8, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { 0x79, 0x0c }, { 0xc8, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { 0x79, 0x0d }, { 0xc8, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { 0x79, 0x09 }, { 0xc8, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { 0x79, 0x02 }, { 0xc8, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { 0x79, 0x03 }, { 0xc8, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { 0x79, 0x05 }, { 0xc8, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { 0x79, 0x26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { 0xff, 0xff }, /* END MARKER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * Here we'll try to encapsulate the changes for just the output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * video format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * RGB656 and YUV422 come from OV; RGB444 is homebrewed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static struct regval_list ov7670_fmt_yuv422[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { REG_COM7, 0x0 }, /* Selects YUV mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { REG_RGB444, 0 }, /* No RGB444 please */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { REG_COM1, 0 }, /* CCIR601 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { REG_COM15, COM15_R00FF },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { 0x4f, 0x80 }, /* "matrix coefficient 1" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { 0x50, 0x80 }, /* "matrix coefficient 2" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { 0x51, 0 }, /* vb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { 0x52, 0x22 }, /* "matrix coefficient 4" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { 0x53, 0x5e }, /* "matrix coefficient 5" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { 0x54, 0x80 }, /* "matrix coefficient 6" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { REG_COM13, COM13_GAMMA|COM13_UVSAT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { 0xff, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static struct regval_list ov7670_fmt_rgb565[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { REG_COM7, COM7_RGB }, /* Selects RGB mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { REG_RGB444, 0 }, /* No RGB444 please */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { REG_COM1, 0x0 }, /* CCIR601 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) { REG_COM15, COM15_RGB565 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) { 0x50, 0xb3 }, /* "matrix coefficient 2" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) { 0x51, 0 }, /* vb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) { 0x52, 0x3d }, /* "matrix coefficient 4" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) { 0x53, 0xa7 }, /* "matrix coefficient 5" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { 0x54, 0xe4 }, /* "matrix coefficient 6" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) { REG_COM13, COM13_GAMMA|COM13_UVSAT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) { 0xff, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static struct regval_list ov7670_fmt_rgb444[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { REG_COM7, COM7_RGB }, /* Selects RGB mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) { REG_COM1, 0x0 }, /* CCIR601 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { 0x50, 0xb3 }, /* "matrix coefficient 2" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) { 0x51, 0 }, /* vb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) { 0x52, 0x3d }, /* "matrix coefficient 4" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { 0x53, 0xa7 }, /* "matrix coefficient 5" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) { 0x54, 0xe4 }, /* "matrix coefficient 6" */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { 0xff, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static struct regval_list ov7670_fmt_raw[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) { REG_COM7, COM7_BAYER },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { REG_COM16, 0x3d }, /* Edge enhancement, denoise */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { 0xff, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * Low-level register I/O.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * Note that there are two versions of these. On the XO 1, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * i2c controller only does SMBUS, so that's what we use. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * ov7670 is not really an SMBUS device, though, so the communication
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * is not always entirely reliable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) unsigned char *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) ret = i2c_smbus_read_byte_data(client, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) *value = (unsigned char)ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int ret = i2c_smbus_write_byte_data(client, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (reg == REG_COM7 && (value & COM7_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) msleep(5); /* Wait for reset to run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * On most platforms, we'd rather do straight i2c I/O.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) unsigned char *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u8 data = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * Send out the register address...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) msg.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) msg.len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) msg.buf = &data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) printk(KERN_ERR "Error %d on register write\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * ...then read back the result.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) msg.flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) *value = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned char data[2] = { reg, value };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) msg.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) msg.len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) msg.buf = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (ret > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (reg == REG_COM7 && (value & COM7_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) msleep(5); /* Wait for reset to run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unsigned char *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (info->use_smbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return ov7670_read_smbus(sd, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return ov7670_read_i2c(sd, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if (info->use_smbus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return ov7670_write_smbus(sd, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) return ov7670_write_i2c(sd, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static int ov7670_update_bits(struct v4l2_subdev *sd, unsigned char reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) unsigned char mask, unsigned char value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) unsigned char orig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) ret = ov7670_read(sd, reg, &orig);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return ov7670_write(sd, reg, (orig & ~mask) | (value & mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) * Write a list of register settings; ff/ff stops the process.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) while (vals->reg_num != 0xff || vals->value != 0xff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int ret = ov7670_write(sd, vals->reg_num, vals->value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) vals++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * Stuff that knows about the sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static int ov7670_reset(struct v4l2_subdev *sd, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ov7670_write(sd, REG_COM7, COM7_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) msleep(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int ov7670_init(struct v4l2_subdev *sd, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) return ov7670_write_array(sd, ov7670_default_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) static int ov7670_detect(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) unsigned char v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) ret = ov7670_init(sd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ret = ov7670_read(sd, REG_MIDH, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (v != 0x7f) /* OV manuf. id. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ret = ov7670_read(sd, REG_MIDL, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (v != 0xa2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * OK, we know we have an OmniVision chip...but which one?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ret = ov7670_read(sd, REG_PID, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (v != 0x76) /* PID + VER = 0x76 / 0x73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) ret = ov7670_read(sd, REG_VER, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (v != 0x73) /* PID + VER = 0x76 / 0x73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * Store information about the video data format. The color matrix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * is deeply tied into the format, so keep the relevant values here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * The magic matrix numbers come from OmniVision.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static struct ov7670_format_struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) u32 mbus_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) enum v4l2_colorspace colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct regval_list *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) int cmatrix[CMATRIX_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) } ov7670_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .regs = ov7670_fmt_yuv422,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .cmatrix = { 128, -128, 0, -34, -94, 128 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .regs = ov7670_fmt_rgb444,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .cmatrix = { 179, -179, 0, -61, -176, 228 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .regs = ov7670_fmt_rgb565,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .cmatrix = { 179, -179, 0, -61, -176, 228 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) .regs = ov7670_fmt_raw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .cmatrix = { 0, 0, 0, 0, 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * Then there is the issue of window sizes. Try to capture the info here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * QCIF mode is done (by OV) in a very strange way - it actually looks like
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * VGA with weird scaling options - they do *not* use the canned QCIF mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * which is allegedly provided by the sensor. So here's the weird register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static struct regval_list ov7670_qcif_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) { REG_COM3, COM3_SCALEEN|COM3_DCWEN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) { REG_COM3, COM3_DCWEN },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) { REG_COM14, COM14_DCWEN | 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) { 0x73, 0xf1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) { 0xa2, 0x52 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) { 0x7b, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) { 0x7c, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) { 0x7d, 0x3c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) { 0x7f, 0x69 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) { REG_COM9, 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) { 0xa1, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) { 0x74, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) { 0x9a, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) { 0x43, 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) { REG_COM13, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) { 0xff, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static struct ov7670_win_size ov7670_win_sizes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* VGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .width = VGA_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .height = VGA_HEIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .com7_bit = COM7_FMT_VGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .hstart = 158, /* These values from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .hstop = 14, /* Omnivision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .vstart = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) .vstop = 490,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .regs = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /* CIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) .width = CIF_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .height = CIF_HEIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .com7_bit = COM7_FMT_CIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .hstart = 170, /* Empirically determined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .hstop = 90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .vstart = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .vstop = 494,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .regs = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* QVGA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .width = QVGA_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .height = QVGA_HEIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .com7_bit = COM7_FMT_QVGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .hstart = 168, /* Empirically determined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .hstop = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .vstart = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .vstop = 492,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .regs = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /* QCIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .width = QCIF_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .height = QCIF_HEIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .com7_bit = COM7_FMT_VGA, /* see comment above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .hstart = 456, /* Empirically determined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .hstop = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .vstart = 14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .vstop = 494,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .regs = ov7670_qcif_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static struct ov7670_win_size ov7675_win_sizes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * Currently, only VGA is supported. Theoretically it could be possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * base and tweak them empirically could be required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .width = VGA_WIDTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .height = VGA_HEIGHT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .com7_bit = COM7_FMT_VGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .hstart = 158, /* These values from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .hstop = 14, /* Omnivision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .vstart = 14, /* Empirically determined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .vstop = 494,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .regs = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static void ov7675_get_framerate(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct v4l2_fract *tpf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u32 clkrc = info->clkrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int pll_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (info->pll_bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) pll_factor = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) pll_factor = PLL_FACTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) clkrc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) clkrc = (clkrc >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) tpf->numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) tpf->denominator = (5 * pll_factor * info->clock_speed) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) (4 * clkrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static int ov7675_apply_framerate(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return ov7670_write(sd, REG_DBLV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) info->pll_bypass ? DBLV_BYPASS : DBLV_X4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static int ov7675_set_framerate(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct v4l2_fract *tpf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) u32 clkrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) int pll_factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * The formula is fps = 5/4*pixclk for YUV/RGB and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) * fps = 5/2*pixclk for RAW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * pixclk = clock_speed / (clkrc + 1) * PLLfactor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (tpf->numerator == 0 || tpf->denominator == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) clkrc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) pll_factor = info->pll_bypass ? 1 : PLL_FACTOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) /
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) (4 * tpf->denominator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) clkrc = (clkrc << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) clkrc--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * The datasheet claims that clkrc = 0 will divide the input clock by 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * but we've checked with an oscilloscope that it divides by 2 instead.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * So, if clkrc = 0 just bypass the divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (clkrc <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) clkrc = CLK_EXT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) else if (clkrc > CLK_SCALE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) clkrc = CLK_SCALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) info->clkrc = clkrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /* Recalculate frame rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ov7675_get_framerate(sd, tpf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * If the device is not powered up by the host driver do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * not apply any changes to H/W at this time. Instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * the framerate will be restored right after power-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (info->on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return ov7675_apply_framerate(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct v4l2_fract *tpf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) tpf->numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) tpf->denominator = info->clock_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) tpf->denominator /= (info->clkrc & CLK_SCALE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct v4l2_fract *tpf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) int div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (tpf->numerator == 0 || tpf->denominator == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) div = 1; /* Reset to full rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) div = (tpf->numerator * info->clock_speed) / tpf->denominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (div == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) else if (div > CLK_SCALE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) div = CLK_SCALE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) info->clkrc = (info->clkrc & 0x80) | div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) tpf->numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) tpf->denominator = info->clock_speed / div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * If the device is not powered up by the host driver do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * not apply any changes to H/W at this time. Instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * the framerate will be restored right after power-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (info->on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return ov7670_write(sd, REG_CLKRC, info->clkrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * Store a set of start/stop values into the camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) int vstart, int vstop)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) unsigned char v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * a mystery "edge offset" value in the top two bits of href.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ret += ov7670_read(sd, REG_HREF, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) ret += ov7670_write(sd, REG_HREF, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * Vertical: similar arrangement, but only 10 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ret += ov7670_read(sd, REG_VREF, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) msleep(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ret += ov7670_write(sd, REG_VREF, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) static int ov7670_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (code->pad || code->index >= N_OV7670_FMTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) code->code = ov7670_formats[code->index].mbus_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) static int ov7670_try_fmt_internal(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct v4l2_mbus_framefmt *fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct ov7670_format_struct **ret_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct ov7670_win_size **ret_wsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) int index, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct ov7670_win_size *wsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) unsigned int n_win_sizes = info->devtype->n_win_sizes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) unsigned int win_sizes_limit = n_win_sizes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) for (index = 0; index < N_OV7670_FMTS; index++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (ov7670_formats[index].mbus_code == fmt->code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (index >= N_OV7670_FMTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* default to first format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) fmt->code = ov7670_formats[0].mbus_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (ret_fmt != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) *ret_fmt = ov7670_formats + index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) * Fields: the OV devices claim to be progressive.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * Don't consider values that don't match min_height and min_width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * constraints.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (info->min_width || info->min_height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) for (i = 0; i < n_win_sizes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) wsize = info->devtype->win_sizes + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (wsize->width < info->min_width ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) wsize->height < info->min_height) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) win_sizes_limit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * Round requested image size down to the nearest
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * we support, but not below the smallest.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) for (wsize = info->devtype->win_sizes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) wsize < info->devtype->win_sizes + win_sizes_limit; wsize++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (fmt->width >= wsize->width && fmt->height >= wsize->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (wsize >= info->devtype->win_sizes + win_sizes_limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) wsize--; /* Take the smallest one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (ret_wsize != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) *ret_wsize = wsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * Note the size we'll actually handle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) fmt->width = wsize->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) fmt->height = wsize->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) fmt->colorspace = ov7670_formats[index].colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) info->format = *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static int ov7670_apply_fmt(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct ov7670_win_size *wsize = info->wsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) unsigned char com7, com10 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * COM7 is a pain in the ass, it doesn't like to be read then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) * quickly written afterward. But we have everything we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * to set it absolutely here, as long as the format-specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * register sets list it first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) com7 = info->fmt->regs[0].value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) com7 |= wsize->com7_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) ret = ov7670_write(sd, REG_COM7, com7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) * Configure the media bus through COM10 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (info->mbus_config & V4L2_MBUS_VSYNC_ACTIVE_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) com10 |= COM10_VS_NEG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if (info->mbus_config & V4L2_MBUS_HSYNC_ACTIVE_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) com10 |= COM10_HREF_REV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (info->pclk_hb_disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) com10 |= COM10_PCLK_HB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) ret = ov7670_write(sd, REG_COM10, com10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * Now write the rest of the array. Also store start/stops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ret = ov7670_write_array(sd, info->fmt->regs + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ret = ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) wsize->vstop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (wsize->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) ret = ov7670_write_array(sd, wsize->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * If we're running RGB565, we must rewrite clkrc after setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * the other parameters or the image looks poor. If we're *not*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * doing RGB565, we must not rewrite clkrc or the image looks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * *really* poor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * (Update) Now that we retain clkrc state, we should be able
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * to write it unconditionally, and that will make the frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * rate persistent too.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * Set a format.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static int ov7670_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) struct v4l2_mbus_framefmt *mbus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ret = ov7670_try_fmt_internal(sd, &format->format, NULL, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, format->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) *mbus_fmt = format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ret = ov7670_try_fmt_internal(sd, &format->format, &info->fmt, &info->wsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * If the device is not powered up by the host driver do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * not apply any changes to H/W at this time. Instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) * the frame format will be restored right after power-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (info->on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return ov7670_apply_fmt(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static int ov7670_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct v4l2_mbus_framefmt *mbus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) mbus_fmt = v4l2_subdev_get_try_format(sd, cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) format->format = *mbus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) format->format = info->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * Implement G/S_PARM. There is a "high quality" mode we could try
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) * to do someday; for now, we just do the frame rate tweak.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) static int ov7670_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct v4l2_subdev_frame_interval *ival)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) info->devtype->get_framerate(sd, &ival->interval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) static int ov7670_s_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct v4l2_subdev_frame_interval *ival)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) struct v4l2_fract *tpf = &ival->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) return info->devtype->set_framerate(sd, tpf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * Frame intervals. Since frame rates are controlled with the clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) * divider, we can only do 30/n for integer n values. So no continuous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) * or stepwise options. Here we just pick a handful of logical values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) static int ov7670_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) unsigned int n_win_sizes = info->devtype->n_win_sizes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (fie->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (fie->index >= ARRAY_SIZE(ov7670_frame_rates))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * Check if the width/height is valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) * If a minimum width/height was requested, filter out the capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) * windows that fall outside that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) for (i = 0; i < n_win_sizes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct ov7670_win_size *win = &info->devtype->win_sizes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (info->min_width && win->width < info->min_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (info->min_height && win->height < info->min_height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) if (fie->width == win->width && fie->height == win->height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) if (i == n_win_sizes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) fie->interval.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) fie->interval.denominator = ov7670_frame_rates[fie->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) * Frame size enumeration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static int ov7670_enum_frame_size(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) int num_valid = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) __u32 index = fse->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) unsigned int n_win_sizes = info->devtype->n_win_sizes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (fse->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * If a minimum width/height was requested, filter out the capture
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * windows that fall outside that.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) for (i = 0; i < n_win_sizes; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) struct ov7670_win_size *win = &info->devtype->win_sizes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) if (info->min_width && win->width < info->min_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (info->min_height && win->height < info->min_height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) if (index == ++num_valid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) fse->min_width = fse->max_width = win->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) fse->min_height = fse->max_height = win->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * Code for dealing with controls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) static int ov7670_store_cmatrix(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) int matrix[CMATRIX_LEN])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) unsigned char signbits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) * Weird crap seems to exist in the upper part of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) * the sign bits register, so let's preserve it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) signbits &= 0xc0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) for (i = 0; i < CMATRIX_LEN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) unsigned char raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (matrix[i] < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) signbits |= (1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (matrix[i] < -255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) raw = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) raw = (-1 * matrix[i]) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (matrix[i] > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) raw = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) raw = matrix[i] & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) * Hue also requires messing with the color matrix. It also requires
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) * trig functions, which tend not to be well supported in the kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) * So here is a simple table of sine values, 0-90 degrees, in steps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) * of five degrees. Values are multiplied by 1000.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * The following naive approximate trig functions require an argument
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * carefully limited to -180 <= theta <= 180.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define SIN_STEP 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static const int ov7670_sin_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) 0, 87, 173, 258, 342, 422,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) 499, 573, 642, 707, 766, 819,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) 866, 906, 939, 965, 984, 996,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) static int ov7670_sine(int theta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) int chs = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) int sine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (theta < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) theta = -theta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) chs = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (theta <= 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) sine = ov7670_sin_table[theta/SIN_STEP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) theta -= 90;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) sine = 1000 - ov7670_sin_table[theta/SIN_STEP];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return sine*chs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static int ov7670_cosine(int theta)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) theta = 90 - theta;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) if (theta > 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) theta -= 360;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) else if (theta < -180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) theta += 360;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) return ov7670_sine(theta);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) static void ov7670_calc_cmatrix(struct ov7670_info *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) int matrix[CMATRIX_LEN], int sat, int hue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) * Apply the current saturation setting first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) for (i = 0; i < CMATRIX_LEN; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * Then, if need be, rotate the hue value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (hue != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) int sinth, costh, tmpmatrix[CMATRIX_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) sinth = ov7670_sine(hue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) costh = ov7670_cosine(hue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) int matrix[CMATRIX_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) ov7670_calc_cmatrix(info, matrix, sat, hue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) ret = ov7670_store_cmatrix(sd, matrix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * Some weird registers seem to store values in a sign/magnitude format!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) static unsigned char ov7670_abs_to_sm(unsigned char v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (v > 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) return v & 0x7f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) return (128 - v) | 0x80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static int ov7670_s_brightness(struct v4l2_subdev *sd, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) unsigned char com8 = 0, v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) ov7670_read(sd, REG_COM8, &com8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) com8 &= ~COM8_AEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) ov7670_write(sd, REG_COM8, com8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) v = ov7670_abs_to_sm(value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) ret = ov7670_write(sd, REG_BRIGHT, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) static int ov7670_s_contrast(struct v4l2_subdev *sd, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) return ov7670_write(sd, REG_CONTRAS, (unsigned char) value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) static int ov7670_s_hflip(struct v4l2_subdev *sd, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) unsigned char v = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) ret = ov7670_read(sd, REG_MVFP, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) v |= MVFP_MIRROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) v &= ~MVFP_MIRROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) msleep(10); /* FIXME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) ret += ov7670_write(sd, REG_MVFP, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) static int ov7670_s_vflip(struct v4l2_subdev *sd, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) unsigned char v = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) ret = ov7670_read(sd, REG_MVFP, &v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) v |= MVFP_FLIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) v &= ~MVFP_FLIP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) msleep(10); /* FIXME */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) ret += ov7670_write(sd, REG_MVFP, v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) * the data sheet, the VREF parts should be the most significant, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) * experience shows otherwise. There seems to be little value in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) * messing with the VREF bits, so we leave them alone.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) unsigned char gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) ret = ov7670_read(sd, REG_GAIN, &gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) *value = gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) static int ov7670_s_gain(struct v4l2_subdev *sd, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) unsigned char com8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) ret = ov7670_write(sd, REG_GAIN, value & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) /* Have to turn off AGC as well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) ret = ov7670_read(sd, REG_COM8, &com8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) * Tweak autogain.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) static int ov7670_s_autogain(struct v4l2_subdev *sd, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) unsigned char com8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) ret = ov7670_read(sd, REG_COM8, &com8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) com8 |= COM8_AGC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) com8 &= ~COM8_AGC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) ret = ov7670_write(sd, REG_COM8, com8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) static int ov7670_s_exp(struct v4l2_subdev *sd, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) unsigned char com1, com8, aech, aechh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) ret = ov7670_read(sd, REG_COM1, &com1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) ov7670_read(sd, REG_COM8, &com8) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) ov7670_read(sd, REG_AECHH, &aechh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) com1 = (com1 & 0xfc) | (value & 0x03);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) aech = (value >> 2) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) ret = ov7670_write(sd, REG_COM1, com1) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) ov7670_write(sd, REG_AECH, aech) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) ov7670_write(sd, REG_AECHH, aechh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) /* Have to turn off AEC as well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) * Tweak autoexposure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static int ov7670_s_autoexp(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) enum v4l2_exposure_auto_type value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) unsigned char com8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) ret = ov7670_read(sd, REG_COM8, &com8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (value == V4L2_EXPOSURE_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) com8 |= COM8_AEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) com8 &= ~COM8_AEC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) ret = ov7670_write(sd, REG_COM8, com8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static const char * const ov7670_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) "No test output",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) "Shifting \"1\"",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) "8-bar color bar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) "Fade to gray color bar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) static int ov7670_s_test_pattern(struct v4l2_subdev *sd, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) ret = ov7670_update_bits(sd, REG_SCALING_XSC, TEST_PATTTERN_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) value & BIT(0) ? TEST_PATTTERN_0 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) return ov7670_update_bits(sd, REG_SCALING_YSC, TEST_PATTTERN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) value & BIT(1) ? TEST_PATTTERN_1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) case V4L2_CID_AUTOGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) return ov7670_g_gain(sd, &info->gain->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) struct v4l2_subdev *sd = to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) return ov7670_s_brightness(sd, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) return ov7670_s_contrast(sd, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) return ov7670_s_sat_hue(sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) info->saturation->val, info->hue->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) return ov7670_s_vflip(sd, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) return ov7670_s_hflip(sd, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) case V4L2_CID_AUTOGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) /* Only set manual gain if auto gain is not explicitly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) turned on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) if (!ctrl->val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) /* ov7670_s_gain turns off auto gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) return ov7670_s_gain(sd, info->gain->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) return ov7670_s_autogain(sd, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) case V4L2_CID_EXPOSURE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) /* Only set manual exposure if auto exposure is not explicitly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) turned on. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (ctrl->val == V4L2_EXPOSURE_MANUAL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) /* ov7670_s_exp turns off auto exposure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) return ov7670_s_exp(sd, info->exposure->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) return ov7670_s_autoexp(sd, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) return ov7670_s_test_pattern(sd, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) static const struct v4l2_ctrl_ops ov7670_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .s_ctrl = ov7670_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .g_volatile_ctrl = ov7670_g_volatile_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) unsigned char val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) ret = ov7670_read(sd, reg->reg & 0xff, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) reg->val = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) reg->size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) static void ov7670_power_on(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (info->on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) clk_prepare_enable(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (info->pwdn_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) gpiod_set_value(info->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (info->resetb_gpio) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) gpiod_set_value(info->resetb_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) gpiod_set_value(info->resetb_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) if (info->pwdn_gpio || info->resetb_gpio || info->clk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) usleep_range(3000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) info->on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) static void ov7670_power_off(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) if (!info->on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) clk_disable_unprepare(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (info->pwdn_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) gpiod_set_value(info->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) info->on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static int ov7670_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if (info->on == on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) ov7670_power_on (sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) ov7670_init(sd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) ov7670_apply_fmt(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) ov7675_apply_framerate(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) v4l2_ctrl_handler_setup(&info->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) ov7670_power_off (sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) static void ov7670_get_default_format(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) struct v4l2_mbus_framefmt *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) format->width = info->devtype->win_sizes[0].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) format->height = info->devtype->win_sizes[0].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) format->colorspace = info->fmt->colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) format->code = info->fmt->mbus_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) format->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) static int ov7670_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) struct v4l2_mbus_framefmt *format =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) ov7670_get_default_format(sd, format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) static const struct v4l2_subdev_core_ops ov7670_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .reset = ov7670_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) .init = ov7670_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) .s_power = ov7670_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) .log_status = v4l2_ctrl_subdev_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) .unsubscribe_event = v4l2_event_subdev_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) .g_register = ov7670_g_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) .s_register = ov7670_s_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) static const struct v4l2_subdev_video_ops ov7670_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) .s_frame_interval = ov7670_s_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) .g_frame_interval = ov7670_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) static const struct v4l2_subdev_pad_ops ov7670_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) .enum_frame_interval = ov7670_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) .enum_frame_size = ov7670_enum_frame_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) .enum_mbus_code = ov7670_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) .get_fmt = ov7670_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) .set_fmt = ov7670_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) static const struct v4l2_subdev_ops ov7670_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) .core = &ov7670_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) .video = &ov7670_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) .pad = &ov7670_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) static const struct v4l2_subdev_internal_ops ov7670_subdev_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) .open = ov7670_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) /* ----------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static const struct ov7670_devtype ov7670_devdata[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) [MODEL_OV7670] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) .win_sizes = ov7670_win_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) .set_framerate = ov7670_set_framerate_legacy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) .get_framerate = ov7670_get_framerate_legacy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) [MODEL_OV7675] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) .win_sizes = ov7675_win_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) .set_framerate = ov7675_set_framerate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) .get_framerate = ov7675_get_framerate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) static int ov7670_init_gpio(struct i2c_client *client, struct ov7670_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) info->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) if (IS_ERR(info->pwdn_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) dev_info(&client->dev, "can't get %s GPIO\n", "powerdown");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) return PTR_ERR(info->pwdn_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) info->resetb_gpio = devm_gpiod_get_optional(&client->dev, "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) if (IS_ERR(info->resetb_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) dev_info(&client->dev, "can't get %s GPIO\n", "reset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) return PTR_ERR(info->resetb_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) usleep_range(3000, 5000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) * ov7670_parse_dt() - Parse device tree to collect mbus configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) * properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) static int ov7670_parse_dt(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) struct ov7670_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) struct fwnode_handle *fwnode = dev_fwnode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) struct v4l2_fwnode_endpoint bus_cfg = { .bus_type = 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) struct fwnode_handle *ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) if (!fwnode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) info->pclk_hb_disable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (fwnode_property_present(fwnode, "ov7670,pclk-hb-disable"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) info->pclk_hb_disable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) ep = fwnode_graph_get_next_endpoint(fwnode, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) if (!ep)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) ret = v4l2_fwnode_endpoint_parse(ep, &bus_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) fwnode_handle_put(ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) if (bus_cfg.bus_type != V4L2_MBUS_PARALLEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) dev_err(dev, "Unsupported media bus type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) info->mbus_config = bus_cfg.bus.parallel.flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) static int ov7670_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) struct v4l2_fract tpf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) struct ov7670_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) if (info == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) sd = &info->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) v4l2_i2c_subdev_init(sd, client, &ov7670_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) sd->internal_ops = &ov7670_subdev_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) info->clock_speed = 30; /* default: a guess */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) if (dev_fwnode(&client->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) ret = ov7670_parse_dt(&client->dev, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) } else if (client->dev.platform_data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) struct ov7670_config *config = client->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) * Must apply configuration before initializing device, because it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) * selects I/O method.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) info->min_width = config->min_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) info->min_height = config->min_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) info->use_smbus = config->use_smbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (config->clock_speed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) info->clock_speed = config->clock_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) if (config->pll_bypass)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) info->pll_bypass = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) if (config->pclk_hb_disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) info->pclk_hb_disable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) info->clk = devm_clk_get(&client->dev, "xclk"); /* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (IS_ERR(info->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) ret = PTR_ERR(info->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) if (ret == -ENOENT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) info->clk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) ret = ov7670_init_gpio(client, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) ov7670_power_on(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) if (info->clk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) info->clock_speed = clk_get_rate(info->clk) / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) if (info->clock_speed < 10 || info->clock_speed > 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) goto power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) /* Make sure it's an ov7670 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) ret = ov7670_detect(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) v4l_dbg(1, debug, client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) "chip found @ 0x%x (%s) is not an ov7670 chip.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) goto power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) v4l_info(client, "chip found @ 0x%02x (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) client->addr << 1, client->adapter->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) info->devtype = &ov7670_devdata[id->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) info->fmt = &ov7670_formats[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) info->wsize = &info->devtype->win_sizes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) ov7670_get_default_format(sd, &info->format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) info->clkrc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) /* Set default frame rate to 30 fps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) tpf.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) tpf.denominator = 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) info->devtype->set_framerate(sd, &tpf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) v4l2_ctrl_handler_init(&info->hdl, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) V4L2_CID_CONTRAST, 0, 127, 1, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) V4L2_CID_SATURATION, 0, 256, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) V4L2_CID_HUE, -180, 180, 5, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) V4L2_CID_GAIN, 0, 255, 1, 128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) V4L2_CID_EXPOSURE, 0, 65535, 1, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) V4L2_EXPOSURE_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) v4l2_ctrl_new_std_menu_items(&info->hdl, &ov7670_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) ARRAY_SIZE(ov7670_test_pattern_menu) - 1, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) ov7670_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) sd->ctrl_handler = &info->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (info->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) ret = info->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) goto hdl_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) * We have checked empirically that hw allows to read back the gain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) * value chosen by auto gain but that's not the case for auto exposure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) v4l2_ctrl_auto_cluster(2, &info->auto_exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) V4L2_EXPOSURE_MANUAL, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) v4l2_ctrl_cluster(2, &info->saturation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) info->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) info->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) ret = media_entity_pads_init(&info->sd.entity, 1, &info->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) goto hdl_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) v4l2_ctrl_handler_setup(&info->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) ret = v4l2_async_register_subdev(&info->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) goto entity_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) ov7670_power_off(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) entity_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) media_entity_cleanup(&info->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) hdl_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) v4l2_ctrl_handler_free(&info->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) ov7670_power_off(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) static int ov7670_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) struct ov7670_info *info = to_state(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) v4l2_ctrl_handler_free(&info->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) media_entity_cleanup(&info->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) ov7670_power_off(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) static const struct i2c_device_id ov7670_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) { "ov7670", MODEL_OV7670 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) { "ov7675", MODEL_OV7675 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) MODULE_DEVICE_TABLE(i2c, ov7670_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) static const struct of_device_id ov7670_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) { .compatible = "ovti,ov7670", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) MODULE_DEVICE_TABLE(of, ov7670_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) static struct i2c_driver ov7670_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) .name = "ov7670",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) .of_match_table = of_match_ptr(ov7670_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) .probe = ov7670_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) .remove = ov7670_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) .id_table = ov7670_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) module_i2c_driver(ov7670_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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