^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ov7251 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 first version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) //#define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OV7251_LANES 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OV7251_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OV7251_LINK_FREQ_240 240000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PIXEL_RATE_WITH_240M_10BIT (OV7251_LINK_FREQ_240 * 2 * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) OV7251_LANES / OV7251_BITS_PER_SAMPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OV7251_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CHIP_ID 0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OV7251_REG_CHIP_ID 0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OV7251_REG_MOD_VENDOR_ID 0x3d10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OV7251_REG_OPT_LOAD_CTRL 0x3d81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OV7251_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OV7251_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OV7251_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OV7251_REG_EXPOSURE 0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OV7251_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OV7251_EXPOSURE_STEP 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OV7251_VTS_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OV7251_REG_ANALOG_GAIN 0x350a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ANALOG_GAIN_MASK 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ANALOG_GAIN_MIN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ANALOG_GAIN_MAX 0x3e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ANALOG_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ANALOG_GAIN_DEFAULT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OV7251_REG_TEST_PATTERN 0x5e00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OV7251_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OV7251_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OV7251_REG_VTS 0x380e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OV7251_MIRROR_REG 0x3821
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OV7251_FLIP_REG 0x3820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OV7251_FETCH_MIRROR(VAL, ENABLE) (ENABLE ? VAL | 0x01 : VAL & 0xf9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OV7251_FETCH_FLIP(VAL, ENABLE) (ENABLE ? VAL | 0x01 : VAL & 0x9f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REG_DELAY 0xFFFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OV7251_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OV7251_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OV7251_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OV7251_NAME "ov7251"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const char * const ov7251_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OV7251_NUM_SUPPLIES ARRAY_SIZE(ov7251_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct ov7251_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct ov7251 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct regulator_bulk_data supplies[OV7251_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) const struct ov7251_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct v4l2_fract cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define to_ov7251(sd) container_of(sd, struct ov7251, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static const struct regval ov7251_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static __maybe_unused const struct regval ov7251_640x480_120fps_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x3005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x3012, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x3013, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x3014, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x3016, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x3017, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x3018, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x301a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x301b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x301c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x3023, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x3037, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x3098, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x3099, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x309a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x309b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x30b0, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x30b1, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x30b3, 0x64},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x30b4, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x30b5, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x3106, 0xda},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x3500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x3501, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x3502, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x3503, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x3509, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x350b, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x3600, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x3602, 0x62},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3620, 0xb7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x3622, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x3626, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x3627, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3630, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3631, 0x35},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3634, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3636, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3662, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3663, 0x70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3664, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3666, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3669, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x366a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x366b, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3673, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3674, 0xef},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3675, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3705, 0xc1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3709, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x373c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3742, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x3757, 0xb3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3788, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x37a8, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x37a9, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3801, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3803, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3804, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3805, 0x8b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3806, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3807, 0xeb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3808, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x380a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x380b, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x380c, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x380d, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x380e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x380f, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3810, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3811, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3813, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3814, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3815, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3820, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x382f, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3832, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3833, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3834, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3835, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3837, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3b80, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x3b81, 0xa5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x3b82, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x3b83, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x3b84, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3b85, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3b86, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3b87, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3b88, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3b89, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3b8a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3b8b, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x3b8c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x3b8d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3b8e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3b8f, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3b94, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3b95, 0xf2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3b96, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3c00, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x3c01, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3c02, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3c03, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3c04, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x3c05, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3c06, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3c07, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3c0c, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x3c0d, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3c0e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3c0f, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x4001, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x4004, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x4005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x404e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x4300, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x4301, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x4501, 0x48},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x4600, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x4601, 0x4e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x4801, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x4806, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x4819, 0xaa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x4823, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x4837, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x4a0d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x4a47, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x4a49, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x4a4b, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x5000, 0x85},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x5001, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * mipi_datarate per lane 630Mbps, 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static __maybe_unused const struct regval ov7251_setting_vga_30fps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { 0x3005, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { 0x3012, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { 0x3013, 0xd2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { 0x3014, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { 0x3016, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { 0x3017, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { 0x3018, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { 0x301a, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { 0x301b, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { 0x301c, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { 0x3023, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { 0x3037, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { 0x3098, 0x04 }, /* pll2 pre divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 0x3099, 0x28 }, /* pll2 multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { 0x309a, 0x05 }, /* pll2 sys divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { 0x309b, 0x04 }, /* pll2 adc divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { 0x309d, 0x00 }, /* pll2 divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { 0x30b0, 0x0a }, /* pll1 pix divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { 0x30b1, 0x01 }, /* pll1 divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { 0x30b3, 0x64 }, /* pll1 multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { 0x30b4, 0x03 }, /* pll1 pre divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { 0x30b5, 0x05 }, /* pll1 mipi divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { 0x3106, 0xda },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { 0x3503, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { 0x3509, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { 0x3600, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { 0x3602, 0x62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { 0x3620, 0xb7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { 0x3622, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { 0x3626, 0x21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { 0x3627, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { 0x3630, 0x44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { 0x3631, 0x35 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { 0x3634, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { 0x3636, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { 0x3662, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { 0x3663, 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { 0x3664, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { 0x3666, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { 0x3669, 0x1a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { 0x366a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { 0x366b, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { 0x3673, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { 0x3674, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { 0x3675, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { 0x3705, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { 0x3709, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { 0x373c, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { 0x3742, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { 0x3757, 0xb3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { 0x3788, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { 0x37a8, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { 0x37a9, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { 0x3800, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { 0x3801, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { 0x3802, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { 0x3803, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { 0x3804, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { 0x3805, 0x8b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { 0x3806, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { 0x3807, 0xeb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { 0x3808, 0x02 }, /* width high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { 0x3809, 0x80 }, /* width low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { 0x380a, 0x01 }, /* height high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { 0x380b, 0xe0 }, /* height low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { 0x380c, 0x03 }, /* total horiz timing high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { 0x380d, 0xa0 }, /* total horiz timing low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { 0x380e, 0x06 }, /* total vertical timing high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { 0x380f, 0xbc }, /* total vertical timing low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { 0x3810, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { 0x3811, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { 0x3812, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { 0x3813, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { 0x3814, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { 0x3815, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { 0x3820, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { 0x3821, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { 0x382f, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { 0x3832, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { 0x3833, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { 0x3834, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { 0x3835, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { 0x3837, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { 0x3b80, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { 0x3b81, 0xa5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { 0x3b82, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { 0x3b83, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { 0x3b84, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { 0x3b85, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { 0x3b86, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { 0x3b87, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { 0x3b88, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { 0x3b89, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { 0x3b8a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { 0x3b8b, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { 0x3b8c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { 0x3b8d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { 0x3b8e, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { 0x3b8f, 0x1a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) { 0x3b94, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { 0x3b95, 0xf2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { 0x3b96, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { 0x3c00, 0x89 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) { 0x3c01, 0x63 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { 0x3c02, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) { 0x3c03, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { 0x3c04, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { 0x3c05, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { 0x3c06, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { 0x3c07, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { 0x3c0c, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { 0x3c0d, 0xd0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { 0x3c0e, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { 0x3c0f, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { 0x4001, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { 0x4004, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { 0x4005, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { 0x404e, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { 0x4300, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { 0x4301, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { 0x4315, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { 0x4501, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { 0x4600, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { 0x4601, 0x4e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { 0x4801, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { 0x4806, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { 0x4819, 0xaa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) { 0x4823, 0x3e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { 0x4837, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) { 0x4a0d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) { 0x4a47, 0x7f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) { 0x4a49, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) { 0x4a4b, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) { 0x5000, 0x85 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { 0x5001, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {REG_NULL, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static __maybe_unused const struct regval ov7251_setting_vga_60fps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) { 0x3005, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { 0x3012, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { 0x3013, 0xd2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) { 0x3014, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { 0x3016, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) { 0x3017, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) { 0x3018, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { 0x301a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) { 0x301b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) { 0x301c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { 0x3023, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) { 0x3037, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) { 0x3098, 0x04 }, /* pll2 pre divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { 0x3099, 0x28 }, /* pll2 multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) { 0x309a, 0x05 }, /* pll2 sys divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) { 0x309b, 0x04 }, /* pll2 adc divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) { 0x309d, 0x00 }, /* pll2 divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) { 0x30b0, 0x0a }, /* pll1 pix divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) { 0x30b1, 0x01 }, /* pll1 divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { 0x30b3, 0x64 }, /* pll1 multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { 0x30b4, 0x03 }, /* pll1 pre divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { 0x30b5, 0x05 }, /* pll1 mipi divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { 0x3106, 0xda },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { 0x3503, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { 0x3509, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { 0x3600, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { 0x3602, 0x62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { 0x3620, 0xb7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) { 0x3622, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { 0x3626, 0x21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { 0x3627, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) { 0x3630, 0x44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) { 0x3631, 0x35 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { 0x3634, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { 0x3636, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { 0x3662, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { 0x3663, 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { 0x3664, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) { 0x3666, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { 0x3669, 0x1a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { 0x366a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) { 0x366b, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { 0x3673, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { 0x3674, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { 0x3675, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { 0x3705, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) { 0x3709, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { 0x373c, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) { 0x3742, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { 0x3757, 0xb3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) { 0x3788, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { 0x37a8, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { 0x37a9, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { 0x3800, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { 0x3801, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { 0x3802, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) { 0x3803, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) { 0x3804, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) { 0x3805, 0x8b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) { 0x3806, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) { 0x3807, 0xeb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) { 0x3808, 0x02 }, /* width high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) { 0x3809, 0x80 }, /* width low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { 0x380a, 0x01 }, /* height high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) { 0x380b, 0xe0 }, /* height low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { 0x380c, 0x03 }, /* total horiz timing high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) { 0x380d, 0xa0 }, /* total horiz timing low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) { 0x380e, 0x03 }, /* total vertical timing high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) { 0x380f, 0x5c }, /* total vertical timing low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) { 0x3810, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) { 0x3811, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) { 0x3812, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) { 0x3813, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) { 0x3814, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) { 0x3815, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) { 0x3820, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) { 0x3821, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) { 0x382f, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) { 0x3832, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) { 0x3833, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) { 0x3834, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) { 0x3835, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) { 0x3837, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) { 0x3b80, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) { 0x3b81, 0xa5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) { 0x3b82, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) { 0x3b83, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) { 0x3b84, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) { 0x3b85, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) { 0x3b86, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) { 0x3b87, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) { 0x3b88, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) { 0x3b89, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) { 0x3b8a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) { 0x3b8b, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) { 0x3b8c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) { 0x3b8d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) { 0x3b8e, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) { 0x3b8f, 0x1a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) { 0x3b94, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) { 0x3b95, 0xf2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) { 0x3b96, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) { 0x3c00, 0x89 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) { 0x3c01, 0x63 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) { 0x3c02, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) { 0x3c03, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) { 0x3c04, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) { 0x3c05, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) { 0x3c06, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) { 0x3c07, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) { 0x3c0c, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) { 0x3c0d, 0xd0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) { 0x3c0e, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) { 0x3c0f, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) { 0x4001, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) { 0x4004, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) { 0x4005, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) { 0x404e, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) { 0x4300, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) { 0x4301, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) { 0x4315, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) { 0x4501, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) { 0x4600, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) { 0x4601, 0x4e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) { 0x4801, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { 0x4806, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) { 0x4819, 0xaa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) { 0x4823, 0x3e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) { 0x4837, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) { 0x4a0d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) { 0x4a47, 0x7f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) { 0x4a49, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) { 0x4a4b, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) { 0x5000, 0x85 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) { 0x5001, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {REG_NULL, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static __maybe_unused const struct regval ov7251_setting_vga_90fps[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) { 0x3005, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) { 0x3012, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) { 0x3013, 0xd2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) { 0x3014, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) { 0x3016, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) { 0x3017, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) { 0x3018, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) { 0x301a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) { 0x301b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) { 0x301c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) { 0x3023, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) { 0x3037, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) { 0x3098, 0x04 }, /* pll2 pre divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) { 0x3099, 0x28 }, /* pll2 multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) { 0x309a, 0x05 }, /* pll2 sys divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) { 0x309b, 0x04 }, /* pll2 adc divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) { 0x309d, 0x00 }, /* pll2 divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) { 0x30b0, 0x0a }, /* pll1 pix divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) { 0x30b1, 0x01 }, /* pll1 divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { 0x30b3, 0x64 }, /* pll1 multiplier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) { 0x30b4, 0x03 }, /* pll1 pre divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) { 0x30b5, 0x05 }, /* pll1 mipi divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) { 0x3106, 0xda },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) { 0x3503, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) { 0x3509, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) { 0x3600, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) { 0x3602, 0x62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) { 0x3620, 0xb7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) { 0x3622, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) { 0x3626, 0x21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) { 0x3627, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) { 0x3630, 0x44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) { 0x3631, 0x35 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) { 0x3634, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) { 0x3636, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) { 0x3662, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) { 0x3663, 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) { 0x3664, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) { 0x3666, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) { 0x3669, 0x1a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) { 0x366a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) { 0x366b, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) { 0x3673, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) { 0x3674, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) { 0x3675, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) { 0x3705, 0xc1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) { 0x3709, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) { 0x373c, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) { 0x3742, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) { 0x3757, 0xb3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) { 0x3788, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) { 0x37a8, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) { 0x37a9, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) { 0x3800, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) { 0x3801, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) { 0x3802, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) { 0x3803, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) { 0x3804, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) { 0x3805, 0x8b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) { 0x3806, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) { 0x3807, 0xeb },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) { 0x3808, 0x02 }, /* width high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) { 0x3809, 0x80 }, /* width low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) { 0x380a, 0x01 }, /* height high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) { 0x380b, 0xe0 }, /* height low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) { 0x380c, 0x03 }, /* total horiz timing high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) { 0x380d, 0xa0 }, /* total horiz timing low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) { 0x380e, 0x02 }, /* total vertical timing high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) { 0x380f, 0x3c }, /* total vertical timing low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) { 0x3810, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) { 0x3811, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) { 0x3812, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) { 0x3813, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) { 0x3814, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) { 0x3815, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) { 0x3820, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) { 0x3821, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) { 0x382f, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) { 0x3832, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) { 0x3833, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) { 0x3834, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) { 0x3835, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) { 0x3837, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) { 0x3b80, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) { 0x3b81, 0xa5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) { 0x3b82, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) { 0x3b83, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) { 0x3b84, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) { 0x3b85, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) { 0x3b86, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) { 0x3b87, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) { 0x3b88, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) { 0x3b89, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) { 0x3b8a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) { 0x3b8b, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) { 0x3b8c, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) { 0x3b8d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) { 0x3b8e, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) { 0x3b8f, 0x1a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) { 0x3b94, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) { 0x3b95, 0xf2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) { 0x3b96, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) { 0x3c00, 0x89 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) { 0x3c01, 0x63 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) { 0x3c02, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) { 0x3c03, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) { 0x3c04, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) { 0x3c05, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) { 0x3c06, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) { 0x3c07, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) { 0x3c0c, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) { 0x3c0d, 0xd0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) { 0x3c0e, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) { 0x3c0f, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) { 0x4001, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) { 0x4004, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) { 0x4005, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) { 0x404e, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) { 0x4300, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) { 0x4301, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) { 0x4315, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) { 0x4501, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) { 0x4600, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) { 0x4601, 0x4e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) { 0x4801, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) { 0x4806, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) { 0x4819, 0xaa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) { 0x4823, 0x3e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) { 0x4837, 0x19 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) { 0x4a0d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) { 0x4a47, 0x7f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) { 0x4a49, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) { 0x4a4b, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) { 0x5000, 0x85 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) { 0x5001, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {REG_NULL, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static const struct ov7251_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .denominator = 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .exp_def = 0x00f8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .hts_def = 0x03a1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .vts_def = 0x021a,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .bus_fmt = MEDIA_BUS_FMT_SBGGR10_1X10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) .reg_list = ov7251_640x480_120fps_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) OV7251_LINK_FREQ_240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static const char * const ov7251_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static int ov7251_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static int ov7251_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ret = ov7251_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) OV7251_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static int ov7251_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) static int ov7251_get_reso_dist(const struct ov7251_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static const struct ov7251_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) ov7251_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) dist = ov7251_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static int ov7251_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) struct ov7251 *ov7251 = to_ov7251(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) const struct ov7251_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) mutex_lock(&ov7251->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) mode = ov7251_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) mutex_unlock(&ov7251->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ov7251->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) __v4l2_ctrl_modify_range(ov7251->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) __v4l2_ctrl_modify_range(ov7251->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) OV7251_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) ov7251->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) mutex_unlock(&ov7251->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static int ov7251_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) struct ov7251 *ov7251 = to_ov7251(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) const struct ov7251_mode *mode = ov7251->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) mutex_lock(&ov7251->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) mutex_unlock(&ov7251->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) fmt->format.code = mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* format info: width/height/data type/virctual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) mutex_unlock(&ov7251->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static int ov7251_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct ov7251 *ov7251 = to_ov7251(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) code->code = ov7251->cur_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static int ov7251_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (fse->code != supported_modes[0].bus_fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) static int ov7251_enable_test_pattern(struct ov7251 *ov7251, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) val = (pattern - 1) | OV7251_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) val = OV7251_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) return ov7251_write_reg(ov7251->client, OV7251_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) OV7251_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) static int ov7251_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct ov7251 *ov7251 = to_ov7251(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) const struct ov7251_mode *mode = ov7251->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) mutex_lock(&ov7251->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (ov7251->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) fi->interval = ov7251->cur_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) mutex_unlock(&ov7251->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static int ov7251_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct ov7251 *ov7251 = to_ov7251(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) const struct ov7251_mode *mode = ov7251->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) u32 val = 1 << (OV7251_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) val |= V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) val |= V4L2_MBUS_CSI2_CHANNEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static void ov7251_get_module_inf(struct ov7251 *ov7251,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) strscpy(inf->base.sensor, OV7251_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) strscpy(inf->base.module, ov7251->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) strscpy(inf->base.lens, ov7251->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static long ov7251_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct ov7251 *ov7251 = to_ov7251(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ov7251_get_module_inf(ov7251, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) hdr->hdr_mode = ov7251->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) w = ov7251->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) h = ov7251->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) ov7251->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (i == ARRAY_SIZE(supported_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) dev_err(&ov7251->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) w = ov7251->cur_mode->hts_def - ov7251->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) h = ov7251->cur_mode->vts_def - ov7251->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) __v4l2_ctrl_modify_range(ov7251->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) __v4l2_ctrl_modify_range(ov7251->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) OV7251_VTS_MAX - ov7251->cur_mode->height, 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ret = ov7251_write_reg(ov7251->client, OV7251_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) OV7251_REG_VALUE_08BIT, OV7251_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) ret = ov7251_write_reg(ov7251->client, OV7251_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) OV7251_REG_VALUE_08BIT, OV7251_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) static long ov7251_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) ret = ov7251_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (copy_to_user(up, inf, sizeof(*inf)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) ret = ov7251_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (copy_to_user(up, hdr, sizeof(*hdr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) ret = ov7251_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) ret = ov7251_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ret = ov7251_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static int __ov7251_start_stream(struct ov7251 *ov7251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ret = ov7251_write_array(ov7251->client, ov7251->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) ret = __v4l2_ctrl_handler_setup(&ov7251->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return ov7251_write_reg(ov7251->client, OV7251_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) OV7251_REG_VALUE_08BIT, OV7251_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) static int __ov7251_stop_stream(struct ov7251 *ov7251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return ov7251_write_reg(ov7251->client, OV7251_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) OV7251_REG_VALUE_08BIT, OV7251_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) static int ov7251_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) struct ov7251 *ov7251 = to_ov7251(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) struct i2c_client *client = ov7251->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) mutex_lock(&ov7251->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (on == ov7251->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) ret = __ov7251_start_stream(ov7251);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) usleep_range(10 * 1000, 12 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) __ov7251_stop_stream(ov7251);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) ov7251->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) mutex_unlock(&ov7251->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) static int ov7251_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) struct ov7251 *ov7251 = to_ov7251(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) struct i2c_client *client = ov7251->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) mutex_lock(&ov7251->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (ov7251->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) ret = ov7251_write_array(ov7251->client, ov7251_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) ov7251->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ov7251->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) mutex_unlock(&ov7251->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static inline u32 ov7251_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) return DIV_ROUND_UP(cycles, OV7251_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) static int __ov7251_power_on(struct ov7251 *ov7251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) struct device *dev = &ov7251->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (!IS_ERR_OR_NULL(ov7251->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ret = pinctrl_select_state(ov7251->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) ov7251->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) ret = clk_set_rate(ov7251->xvclk, OV7251_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (clk_get_rate(ov7251->xvclk) != OV7251_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) ret = clk_prepare_enable(ov7251->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (!IS_ERR(ov7251->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) gpiod_set_value_cansleep(ov7251->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) ret = regulator_bulk_enable(OV7251_NUM_SUPPLIES, ov7251->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) usleep_range(5 * 1000, 10 * 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (!IS_ERR(ov7251->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) gpiod_set_value_cansleep(ov7251->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (!IS_ERR(ov7251->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) gpiod_set_value_cansleep(ov7251->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (!IS_ERR(ov7251->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) usleep_range(6000, 8000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) usleep_range(12000, 16000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) delay_us = ov7251_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) clk_disable_unprepare(ov7251->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) static void __ov7251_power_off(struct ov7251 *ov7251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) struct device *dev = &ov7251->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (!IS_ERR(ov7251->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) gpiod_set_value_cansleep(ov7251->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) clk_disable_unprepare(ov7251->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (!IS_ERR(ov7251->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) gpiod_set_value_cansleep(ov7251->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) if (!IS_ERR_OR_NULL(ov7251->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) ret = pinctrl_select_state(ov7251->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) ov7251->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) regulator_bulk_disable(OV7251_NUM_SUPPLIES, ov7251->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static int ov7251_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) struct ov7251 *ov7251 = to_ov7251(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return __ov7251_power_on(ov7251);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static int ov7251_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct ov7251 *ov7251 = to_ov7251(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) __ov7251_power_off(ov7251);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) static int ov7251_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) struct ov7251 *ov7251 = to_ov7251(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) const struct ov7251_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) mutex_lock(&ov7251->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) try_fmt->code = def_mode->bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) mutex_unlock(&ov7251->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) static int ov7251_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) fie->code = supported_modes[fie->index].bus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static const struct dev_pm_ops ov7251_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) SET_RUNTIME_PM_OPS(ov7251_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) ov7251_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static const struct v4l2_subdev_internal_ops ov7251_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) .open = ov7251_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) static const struct v4l2_subdev_core_ops ov7251_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) .s_power = ov7251_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) .ioctl = ov7251_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) .compat_ioctl32 = ov7251_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) static const struct v4l2_subdev_video_ops ov7251_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) .s_stream = ov7251_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) .g_frame_interval = ov7251_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) static const struct v4l2_subdev_pad_ops ov7251_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) .enum_mbus_code = ov7251_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) .enum_frame_size = ov7251_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) .enum_frame_interval = ov7251_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) .get_fmt = ov7251_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) .set_fmt = ov7251_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) .get_mbus_config = ov7251_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) static const struct v4l2_subdev_ops ov7251_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) .core = &ov7251_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) .video = &ov7251_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) .pad = &ov7251_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static int ov7251_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) struct ov7251 *ov7251 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) struct ov7251, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) struct i2c_client *client = ov7251->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) max = ov7251->cur_mode->height + ctrl->val - 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) __v4l2_ctrl_modify_range(ov7251->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) ov7251->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) ov7251->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) ov7251->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) ret = ov7251_write_reg(ov7251->client, OV7251_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) OV7251_REG_VALUE_24BIT, ctrl->val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) ret = ov7251_write_reg(ov7251->client, OV7251_REG_ANALOG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) OV7251_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) ctrl->val & ANALOG_GAIN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ret = ov7251_write_reg(ov7251->client, OV7251_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) OV7251_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) ctrl->val + ov7251->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) ret = ov7251_enable_test_pattern(ov7251, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) ret = ov7251_read_reg(ov7251->client, OV7251_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) OV7251_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) ret |= ov7251_write_reg(ov7251->client, OV7251_MIRROR_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) OV7251_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) OV7251_FETCH_MIRROR(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ret = ov7251_read_reg(ov7251->client, OV7251_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) OV7251_REG_VALUE_08BIT, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) ret |= ov7251_write_reg(ov7251->client, OV7251_FLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) OV7251_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) OV7251_FETCH_FLIP(val, ctrl->val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static const struct v4l2_ctrl_ops ov7251_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .s_ctrl = ov7251_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static int ov7251_initialize_controls(struct ov7251 *ov7251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) const struct ov7251_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) handler = &ov7251->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) mode = ov7251->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) handler->lock = &ov7251->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) 0, PIXEL_RATE_WITH_240M_10BIT, 1, PIXEL_RATE_WITH_240M_10BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) ov7251->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (ov7251->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) ov7251->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) ov7251->vblank = v4l2_ctrl_new_std(handler, &ov7251_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) OV7251_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) ov7251->cur_fps = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) exposure_max = mode->vts_def - 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) ov7251->exposure = v4l2_ctrl_new_std(handler, &ov7251_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) V4L2_CID_EXPOSURE, OV7251_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) exposure_max, OV7251_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) ov7251->anal_gain = v4l2_ctrl_new_std(handler, &ov7251_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) ANALOG_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) ov7251->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) &ov7251_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) ARRAY_SIZE(ov7251_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) 0, 0, ov7251_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) v4l2_ctrl_new_std(handler, &ov7251_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) v4l2_ctrl_new_std(handler, &ov7251_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) dev_err(&ov7251->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) ov7251->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static int ov7251_check_sensor_id(struct ov7251 *ov7251,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) struct device *dev = &ov7251->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) ret = ov7251_read_reg(client, OV7251_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) OV7251_REG_VALUE_08BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) static int ov7251_configure_regulators(struct ov7251 *ov7251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) for (i = 0; i < OV7251_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) ov7251->supplies[i].supply = ov7251_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) return devm_regulator_bulk_get(&ov7251->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) OV7251_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) ov7251->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) static int ov7251_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) struct ov7251 *ov7251;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) ov7251 = devm_kzalloc(dev, sizeof(*ov7251), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) if (!ov7251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) &ov7251->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) &ov7251->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) &ov7251->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) &ov7251->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) ov7251->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) ov7251->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) ov7251->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) if (IS_ERR(ov7251->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) ov7251->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) if (IS_ERR(ov7251->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) ov7251->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) if (IS_ERR(ov7251->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) ov7251->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (!IS_ERR(ov7251->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) ov7251->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) pinctrl_lookup_state(ov7251->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) if (IS_ERR(ov7251->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) ov7251->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) pinctrl_lookup_state(ov7251->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (IS_ERR(ov7251->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) ret = ov7251_configure_regulators(ov7251);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) mutex_init(&ov7251->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) sd = &ov7251->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) v4l2_i2c_subdev_init(sd, client, &ov7251_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) ret = ov7251_initialize_controls(ov7251);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) ret = __ov7251_power_on(ov7251);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) ret = ov7251_check_sensor_id(ov7251, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) sd->internal_ops = &ov7251_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) ov7251->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) ret = media_entity_pads_init(&sd->entity, 1, &ov7251->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) if (strcmp(ov7251->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) ov7251->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) OV7251_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) __ov7251_power_off(ov7251);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) v4l2_ctrl_handler_free(&ov7251->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) mutex_destroy(&ov7251->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) static int ov7251_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) struct ov7251 *ov7251 = to_ov7251(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) v4l2_ctrl_handler_free(&ov7251->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) mutex_destroy(&ov7251->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) __ov7251_power_off(ov7251);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) static const struct of_device_id ov7251_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) { .compatible = "ovti,ov7251" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) MODULE_DEVICE_TABLE(of, ov7251_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) static const struct i2c_device_id ov7251_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) { "ovti,ov7251", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static struct i2c_driver ov7251_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) .name = OV7251_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .pm = &ov7251_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .of_match_table = of_match_ptr(ov7251_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) .probe = &ov7251_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) .remove = &ov7251_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) .id_table = ov7251_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) return i2c_add_driver(&ov7251_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) i2c_del_driver(&ov7251_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) MODULE_DESCRIPTION("OmniVision ov7251 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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