^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * V4L2 subdevice driver for OmniVision OV6650 Camera Sensor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2010 Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Based on OmniVision OV96xx Camera Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2009 Marek Vasut <marek.vasut@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Based on ov772x camera driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Copyright (C) 2008 Renesas Solutions Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Kuninori Morimoto <morimoto.kuninori@renesas.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Based on ov7670 and soc_camera_platform driver,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Copyright (C) 2008 Magnus Damm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Hardware specific bits initially based on former work by Matt Callow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * drivers/media/video/omap/sensor_ov6650.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Copyright (C) 2006 Matt Callow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* Register definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define REG_GAIN 0x00 /* range 00 - 3F */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define REG_BLUE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define REG_RED 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define REG_SAT 0x03 /* [7:4] saturation [0:3] reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define REG_HUE 0x04 /* [7:6] rsrvd [5] hue en [4:0] hue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define REG_BRT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define REG_PIDH 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define REG_PIDL 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define REG_AECH 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define REG_CLKRC 0x11 /* Data Format and Internal Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* [7:6] Input system clock (MHz)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* 00=8, 01=12, 10=16, 11=24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* [5:0]: Internal Clock Pre-Scaler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define REG_COMA 0x12 /* [7] Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define REG_COMB 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define REG_COMC 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define REG_COMD 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define REG_COML 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define REG_HSTRT 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define REG_HSTOP 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define REG_VSTRT 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define REG_VSTOP 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define REG_PSHFT 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define REG_MIDH 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define REG_MIDL 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define REG_HSYNS 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define REG_HSYNE 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define REG_COME 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define REG_YOFF 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define REG_UOFF 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define REG_VOFF 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define REG_AEW 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define REG_AEB 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define REG_COMF 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define REG_COMG 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define REG_COMH 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define REG_COMI 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define REG_FRARL 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define REG_COMJ 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define REG_COMK 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define REG_AVGY 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define REG_REF0 0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define REG_REF1 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define REG_REF2 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define REG_FRAJH 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define REG_FRAJL 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define REG_FACT 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define REG_L1AEC 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define REG_AVGU 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define REG_AVGV 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define REG_SPCB 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define REG_SPCC 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define REG_GAM1 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define REG_GAM2 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define REG_GAM3 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define REG_SPCD 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define REG_SPCE 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define REG_ADCL 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define REG_RMCO 0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define REG_GMCO 0x6d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define REG_BMCO 0x6e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Register bits, values, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OV6650_PIDH 0x66 /* high byte of product ID number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OV6650_PIDL 0x50 /* low byte of product ID number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define OV6650_MIDH 0x7F /* high byte of mfg ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define OV6650_MIDL 0xA2 /* low byte of mfg ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DEF_GAIN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DEF_BLUE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DEF_RED 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SAT_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SAT_MASK (0xf << SAT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SET_SAT(x) (((x) << SAT_SHIFT) & SAT_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HUE_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HUE_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DEF_HUE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SET_HUE(x) (HUE_EN | ((x) & HUE_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DEF_AECH 0x4D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLKRC_8MHz 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLKRC_12MHz 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLKRC_16MHz 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLKRC_24MHz 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLKRC_DIV_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GET_CLKRC_DIV(x) (((x) & CLKRC_DIV_MASK) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DEF_CLKRC 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define COMA_RESET BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define COMA_QCIF BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define COMA_RAW_RGB BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define COMA_RGB BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define COMA_BW BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define COMA_WORD_SWAP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define COMA_BYTE_SWAP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define DEF_COMA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define COMB_FLIP_V BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define COMB_FLIP_H BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define COMB_BAND_FILTER BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define COMB_AWB BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define COMB_AGC BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define COMB_AEC BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define DEF_COMB 0x5f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define COML_ONE_CHANNEL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DEF_HSTRT 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DEF_HSTOP 0xd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DEF_VSTRT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DEF_VSTOP 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define COMF_HREF_LOW BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define COMJ_PCLK_RISING BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define COMJ_VSYNC_HIGH BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* supported resolutions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define W_QCIF (DEF_HSTOP - DEF_HSTRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define W_CIF (W_QCIF << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define H_QCIF (DEF_VSTOP - DEF_VSTRT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define H_CIF (H_QCIF << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define FRAME_RATE_MAX 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct ov6650_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u8 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct ov6650 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct v4l2_ctrl_handler hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* exposure/autoexposure cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct v4l2_ctrl *autoexposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* gain/autogain cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct v4l2_ctrl *autogain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct v4l2_ctrl *gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* blue/red/autowhitebalance cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct v4l2_ctrl *autowb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct v4l2_ctrl *blue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) struct v4l2_ctrl *red;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct v4l2_clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) bool half_scale; /* scale down output by 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct v4l2_rect rect; /* sensor cropping window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct v4l2_fract tpf; /* as requested with s_frame_interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct ov6650_xclk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u8 clkrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static const struct ov6650_xclk ov6650_xclk[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .rate = 8000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .clkrc = CLKRC_8MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .rate = 12000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .clkrc = CLKRC_12MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .rate = 16000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .clkrc = CLKRC_16MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .rate = 24000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .clkrc = CLKRC_24MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static u32 ov6650_codes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MEDIA_BUS_FMT_YUYV8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MEDIA_BUS_FMT_UYVY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MEDIA_BUS_FMT_YVYU8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) MEDIA_BUS_FMT_VYUY8_2X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) MEDIA_BUS_FMT_SBGGR8_1X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) MEDIA_BUS_FMT_Y8_1X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static const struct v4l2_mbus_framefmt ov6650_def_fmt = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .width = W_CIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .height = H_CIF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .code = MEDIA_BUS_FMT_SBGGR8_1X8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) .colorspace = V4L2_COLORSPACE_SRGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) .field = V4L2_FIELD_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .quantization = V4L2_QUANTIZATION_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .xfer_func = V4L2_XFER_FUNC_DEFAULT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* read a register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int ov6650_reg_read(struct i2c_client *client, u8 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u8 data = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) .len = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) .buf = &data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) msg.flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) *val = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) dev_err(&client->dev, "Failed reading register 0x%02x!\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* write a register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static int ov6650_reg_write(struct i2c_client *client, u8 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) unsigned char data[2] = { reg, val };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct i2c_msg msg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .addr = client->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .flags = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .len = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .buf = data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dev_err(&client->dev, "Failed writing register 0x%02x!\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* Read a register, alter its bits, write it back */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static int ov6650_reg_rmw(struct i2c_client *client, u8 reg, u8 set, u8 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ret = ov6650_reg_read(client, reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "[Read]-Modify-Write of register 0x%02x failed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) val |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ret = ov6650_reg_write(client, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "Read-Modify-[Write] of register 0x%02x failed!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static struct ov6650 *to_ov6650(const struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return container_of(i2c_get_clientdata(client), struct ov6650, subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) /* Start/Stop streaming from the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static int ov6650_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* Get status of additional camera capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static int ov6550_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct v4l2_subdev *sd = &priv->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) uint8_t reg, reg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) case V4L2_CID_AUTOGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ret = ov6650_reg_read(client, REG_GAIN, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) priv->gain->val = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case V4L2_CID_AUTO_WHITE_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) ret = ov6650_reg_read(client, REG_BLUE, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) ret = ov6650_reg_read(client, REG_RED, ®2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) priv->blue->val = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) priv->red->val = reg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) case V4L2_CID_EXPOSURE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) ret = ov6650_reg_read(client, REG_AECH, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) priv->exposure->val = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* Set status of additional camera capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int ov6550_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct ov6650 *priv = container_of(ctrl->handler, struct ov6650, hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct v4l2_subdev *sd = &priv->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) case V4L2_CID_AUTOGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) ret = ov6650_reg_rmw(client, REG_COMB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ctrl->val ? COMB_AGC : 0, COMB_AGC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (!ret && !ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ret = ov6650_reg_write(client, REG_GAIN, priv->gain->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) case V4L2_CID_AUTO_WHITE_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ret = ov6650_reg_rmw(client, REG_COMB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ctrl->val ? COMB_AWB : 0, COMB_AWB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!ret && !ctrl->val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ret = ov6650_reg_write(client, REG_BLUE, priv->blue->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ret = ov6650_reg_write(client, REG_RED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) priv->red->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return ov6650_reg_rmw(client, REG_SAT, SET_SAT(ctrl->val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) SAT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) case V4L2_CID_HUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return ov6650_reg_rmw(client, REG_HUE, SET_HUE(ctrl->val),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) HUE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) case V4L2_CID_BRIGHTNESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return ov6650_reg_write(client, REG_BRT, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) case V4L2_CID_EXPOSURE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) ret = ov6650_reg_rmw(client, REG_COMB, ctrl->val ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) V4L2_EXPOSURE_AUTO ? COMB_AEC : 0, COMB_AEC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (!ret && ctrl->val == V4L2_EXPOSURE_MANUAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) ret = ov6650_reg_write(client, REG_AECH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) priv->exposure->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) case V4L2_CID_GAMMA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ov6650_reg_write(client, REG_GAM1, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return ov6650_reg_rmw(client, REG_COMB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ctrl->val ? COMB_FLIP_V : 0, COMB_FLIP_V);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return ov6650_reg_rmw(client, REG_COMB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ctrl->val ? COMB_FLIP_H : 0, COMB_FLIP_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static int ov6650_get_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (reg->reg & ~0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) reg->size = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) ret = ov6650_reg_read(client, reg->reg, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) reg->val = (__u64)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static int ov6650_set_register(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) const struct v4l2_dbg_register *reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (reg->reg & ~0xff || reg->val & ~0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return ov6650_reg_write(client, reg->reg, reg->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int ov6650_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct ov6650 *priv = to_ov6650(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) ret = v4l2_clk_enable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) v4l2_clk_disable(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) static int ov6650_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct ov6650 *priv = to_ov6650(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) switch (sel->target) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) case V4L2_SEL_TGT_CROP_BOUNDS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) sel->r.left = DEF_HSTRT << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) sel->r.top = DEF_VSTRT << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) sel->r.width = W_CIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) sel->r.height = H_CIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) case V4L2_SEL_TGT_CROP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) sel->r = priv->rect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int ov6650_set_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct ov6650 *priv = to_ov6650(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (sel->which != V4L2_SUBDEV_FORMAT_ACTIVE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) sel->target != V4L2_SEL_TGT_CROP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) v4l_bound_align_image(&sel->r.width, 2, W_CIF, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) &sel->r.height, 2, H_CIF, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) v4l_bound_align_image(&sel->r.left, DEF_HSTRT << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) (DEF_HSTRT << 1) + W_CIF - (__s32)sel->r.width, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) &sel->r.top, DEF_VSTRT << 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) (DEF_VSTRT << 1) + H_CIF - (__s32)sel->r.height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ret = ov6650_reg_write(client, REG_HSTRT, sel->r.left >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) priv->rect.width += priv->rect.left - sel->r.left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) priv->rect.left = sel->r.left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) ret = ov6650_reg_write(client, REG_HSTOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) (sel->r.left + sel->r.width) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) priv->rect.width = sel->r.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ret = ov6650_reg_write(client, REG_VSTRT, sel->r.top >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) priv->rect.height += priv->rect.top - sel->r.top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) priv->rect.top = sel->r.top;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) ret = ov6650_reg_write(client, REG_VSTOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) (sel->r.top + sel->r.height) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) priv->rect.height = sel->r.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static int ov6650_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct v4l2_mbus_framefmt *mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct ov6650 *priv = to_ov6650(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) /* initialize response with default media bus frame format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) *mf = ov6650_def_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* update media bus format code and frame size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mf->width = cfg->try_fmt.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) mf->height = cfg->try_fmt.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) mf->code = cfg->try_fmt.code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) mf->width = priv->rect.width >> priv->half_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) mf->height = priv->rect.height >> priv->half_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) mf->code = priv->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static bool is_unscaled_ok(int width, int height, struct v4l2_rect *rect)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return width > rect->width >> 1 || height > rect->height >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define to_clkrc(div) ((div) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* set the format we will capture in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) static int ov6650_s_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *mf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct ov6650 *priv = to_ov6650(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) bool half_scale = !is_unscaled_ok(mf->width, mf->height, &priv->rect);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct v4l2_subdev_selection sel = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .which = V4L2_SUBDEV_FORMAT_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .target = V4L2_SEL_TGT_CROP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) .r.left = priv->rect.left + (priv->rect.width >> 1) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) (mf->width >> (1 - half_scale)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .r.top = priv->rect.top + (priv->rect.height >> 1) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) (mf->height >> (1 - half_scale)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .r.width = mf->width << half_scale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .r.height = mf->height << half_scale,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u32 code = mf->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u8 coma_set = 0, coma_mask = 0, coml_set, coml_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* select color matrix configuration for given color encoding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) switch (code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) case MEDIA_BUS_FMT_Y8_1X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dev_dbg(&client->dev, "pixel format GREY8_1X8\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) coma_mask |= COMA_RGB | COMA_WORD_SWAP | COMA_BYTE_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) coma_set |= COMA_BW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case MEDIA_BUS_FMT_YUYV8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dev_dbg(&client->dev, "pixel format YUYV8_2X8_LE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) coma_mask |= COMA_RGB | COMA_BW | COMA_BYTE_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) coma_set |= COMA_WORD_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) case MEDIA_BUS_FMT_YVYU8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dev_dbg(&client->dev, "pixel format YVYU8_2X8_LE (untested)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) COMA_BYTE_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) case MEDIA_BUS_FMT_UYVY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_dbg(&client->dev, "pixel format YUYV8_2X8_BE\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (half_scale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) coma_set |= COMA_BYTE_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) coma_mask |= COMA_RGB | COMA_BW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) case MEDIA_BUS_FMT_VYUY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev_dbg(&client->dev, "pixel format YVYU8_2X8_BE (untested)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (half_scale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) coma_mask |= COMA_RGB | COMA_BW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) coma_set |= COMA_BYTE_SWAP | COMA_WORD_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) coma_mask |= COMA_RGB | COMA_BW | COMA_WORD_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) coma_set |= COMA_BYTE_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) case MEDIA_BUS_FMT_SBGGR8_1X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_dbg(&client->dev, "pixel format SBGGR8_1X8 (untested)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) coma_mask |= COMA_BW | COMA_BYTE_SWAP | COMA_WORD_SWAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) coma_set |= COMA_RAW_RGB | COMA_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dev_err(&client->dev, "Pixel format not handled: 0x%x\n", code);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (code == MEDIA_BUS_FMT_Y8_1X8 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) code == MEDIA_BUS_FMT_SBGGR8_1X8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) coml_mask = COML_ONE_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) coml_set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) coml_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) coml_set = COML_ONE_CHANNEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (half_scale) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) dev_dbg(&client->dev, "max resolution: QCIF\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) coma_set |= COMA_QCIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) dev_dbg(&client->dev, "max resolution: CIF\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) coma_mask |= COMA_QCIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ret = ov6650_set_selection(sd, NULL, &sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ret = ov6650_reg_rmw(client, REG_COMA, coma_set, coma_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) priv->half_scale = half_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ret = ov6650_reg_rmw(client, REG_COML, coml_set, coml_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) priv->code = code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) static int ov6650_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct v4l2_mbus_framefmt *mf = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct ov6650 *priv = to_ov6650(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (format->pad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (is_unscaled_ok(mf->width, mf->height, &priv->rect))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) v4l_bound_align_image(&mf->width, 2, W_CIF, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) &mf->height, 2, H_CIF, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) switch (mf->code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) case MEDIA_BUS_FMT_Y10_1X10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) mf->code = MEDIA_BUS_FMT_Y8_1X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) case MEDIA_BUS_FMT_Y8_1X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) case MEDIA_BUS_FMT_YVYU8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) case MEDIA_BUS_FMT_YUYV8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) case MEDIA_BUS_FMT_VYUY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) case MEDIA_BUS_FMT_UYVY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) mf->code = MEDIA_BUS_FMT_SBGGR8_1X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) case MEDIA_BUS_FMT_SBGGR8_1X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* store media bus format code and frame size in pad config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) cfg->try_fmt.width = mf->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) cfg->try_fmt.height = mf->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) cfg->try_fmt.code = mf->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) /* return default mbus frame format updated with pad config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) *mf = ov6650_def_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) mf->width = cfg->try_fmt.width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) mf->height = cfg->try_fmt.height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) mf->code = cfg->try_fmt.code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* apply new media bus format code and frame size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int ret = ov6650_s_fmt(sd, mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* return default format updated with active size and code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) *mf = ov6650_def_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) mf->width = priv->rect.width >> priv->half_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) mf->height = priv->rect.height >> priv->half_scale;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) mf->code = priv->code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static int ov6650_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) if (code->pad || code->index >= ARRAY_SIZE(ov6650_codes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) code->code = ov6650_codes[code->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static int ov6650_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct v4l2_subdev_frame_interval *ival)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct ov6650 *priv = to_ov6650(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ival->interval = priv->tpf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) dev_dbg(&client->dev, "Frame interval: %u/%u s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) ival->interval.numerator, ival->interval.denominator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static int ov6650_s_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) struct v4l2_subdev_frame_interval *ival)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct ov6650 *priv = to_ov6650(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct v4l2_fract *tpf = &ival->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int div, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (tpf->numerator == 0 || tpf->denominator == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) div = 1; /* Reset to full rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) div = (tpf->numerator * FRAME_RATE_MAX) / tpf->denominator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (div == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) div = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) else if (div > GET_CLKRC_DIV(CLKRC_DIV_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) div = GET_CLKRC_DIV(CLKRC_DIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) ret = ov6650_reg_rmw(client, REG_CLKRC, to_clkrc(div), CLKRC_DIV_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) priv->tpf.numerator = div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) priv->tpf.denominator = FRAME_RATE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) *tpf = priv->tpf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* Soft reset the camera. This has nothing to do with the RESET pin! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static int ov6650_reset(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dev_dbg(&client->dev, "reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) ret = ov6650_reg_rmw(client, REG_COMA, COMA_RESET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) "An error occurred while entering soft reset!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* program default register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static int ov6650_prog_dflt(struct i2c_client *client, u8 clkrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) dev_dbg(&client->dev, "initializing\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ret = ov6650_reg_write(client, REG_COMA, 0); /* ~COMA_RESET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret = ov6650_reg_write(client, REG_CLKRC, clkrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) ret = ov6650_reg_rmw(client, REG_COMB, 0, COMB_BAND_FILTER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) static int ov6650_video_probe(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct ov6650 *priv = to_ov6650(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) const struct ov6650_xclk *xclk = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u8 pidh, pidl, midh, midl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) priv->clk = v4l2_clk_get(&client->dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) if (IS_ERR(priv->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ret = PTR_ERR(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dev_err(&client->dev, "v4l2_clk request err: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) rate = v4l2_clk_get_rate(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) for (i = 0; rate && i < ARRAY_SIZE(ov6650_xclk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (rate != ov6650_xclk[i].rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) xclk = &ov6650_xclk[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) dev_info(&client->dev, "using host default clock rate %lukHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) rate / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) for (i = 0; !xclk && i < ARRAY_SIZE(ov6650_xclk); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) ret = v4l2_clk_set_rate(priv->clk, ov6650_xclk[i].rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (ret || v4l2_clk_get_rate(priv->clk) != ov6650_xclk[i].rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) xclk = &ov6650_xclk[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) dev_info(&client->dev, "using negotiated clock rate %lukHz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) xclk->rate / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (!xclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dev_err(&client->dev, "unable to get supported clock rate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) goto eclkput;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ret = ov6650_s_power(sd, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) goto eclkput;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * check and show product ID and manufacturer ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ret = ov6650_reg_read(client, REG_PIDH, &pidh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ret = ov6650_reg_read(client, REG_PIDL, &pidl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) ret = ov6650_reg_read(client, REG_MIDH, &midh);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ret = ov6650_reg_read(client, REG_MIDL, &midl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if ((pidh != OV6650_PIDH) || (pidl != OV6650_PIDL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) dev_err(&client->dev, "Product ID error 0x%02x:0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) pidh, pidl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) goto done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) dev_info(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) "ov6650 Product ID 0x%02x:0x%02x Manufacturer ID 0x%02x:0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) pidh, pidl, midh, midl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ret = ov6650_reset(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) ret = ov6650_prog_dflt(client, xclk->clkrc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct v4l2_mbus_framefmt mf = ov6650_def_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ret = ov6650_s_fmt(sd, &mf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) ret = v4l2_ctrl_handler_setup(&priv->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ov6650_s_power(sd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) eclkput:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) v4l2_clk_put(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static const struct v4l2_ctrl_ops ov6550_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) .g_volatile_ctrl = ov6550_g_volatile_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) .s_ctrl = ov6550_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) static const struct v4l2_subdev_core_ops ov6650_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #ifdef CONFIG_VIDEO_ADV_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) .g_register = ov6650_get_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) .s_register = ov6650_set_register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) .s_power = ov6650_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) /* Request bus settings on camera side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static int ov6650_get_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct v4l2_mbus_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) u8 comj, comf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ret = ov6650_reg_read(client, REG_COMJ, &comj);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) ret = ov6650_reg_read(client, REG_COMF, &comf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_DATA_ACTIVE_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) | ((comj & COMJ_VSYNC_HIGH) ? V4L2_MBUS_VSYNC_ACTIVE_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) : V4L2_MBUS_VSYNC_ACTIVE_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) | ((comf & COMF_HREF_LOW) ? V4L2_MBUS_HSYNC_ACTIVE_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) : V4L2_MBUS_HSYNC_ACTIVE_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) | ((comj & COMJ_PCLK_RISING) ? V4L2_MBUS_PCLK_SAMPLE_RISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) : V4L2_MBUS_PCLK_SAMPLE_FALLING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) cfg->type = V4L2_MBUS_PARALLEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* Alter bus settings on camera side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static int ov6650_set_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) struct v4l2_mbus_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct i2c_client *client = v4l2_get_subdevdata(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if (cfg->flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_PCLK_RISING, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) else if (cfg->flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_PCLK_RISING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) if (cfg->flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ret = ov6650_reg_rmw(client, REG_COMF, COMF_HREF_LOW, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) else if (cfg->flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ret = ov6650_reg_rmw(client, REG_COMF, 0, COMF_HREF_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (cfg->flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ret = ov6650_reg_rmw(client, REG_COMJ, COMJ_VSYNC_HIGH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) else if (cfg->flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) ret = ov6650_reg_rmw(client, REG_COMJ, 0, COMJ_VSYNC_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) * Update the configuration to report what is actually applied to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * the hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) return ov6650_get_mbus_config(sd, pad, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) static const struct v4l2_subdev_video_ops ov6650_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .s_stream = ov6650_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) .g_frame_interval = ov6650_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) .s_frame_interval = ov6650_s_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static const struct v4l2_subdev_pad_ops ov6650_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) .enum_mbus_code = ov6650_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .get_selection = ov6650_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) .set_selection = ov6650_set_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) .get_fmt = ov6650_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) .set_fmt = ov6650_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) .get_mbus_config = ov6650_get_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) .set_mbus_config = ov6650_set_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) static const struct v4l2_subdev_ops ov6650_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) .core = &ov6650_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) .video = &ov6650_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) .pad = &ov6650_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) static const struct v4l2_subdev_internal_ops ov6650_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) .registered = ov6650_video_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * i2c_driver function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) static int ov6650_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) const struct i2c_device_id *did)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) struct ov6650 *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) priv = devm_kzalloc(&client->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) v4l2_i2c_subdev_init(&priv->subdev, client, &ov6650_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) v4l2_ctrl_handler_init(&priv->hdl, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) priv->autogain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) priv->gain = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) V4L2_CID_GAIN, 0, 0x3f, 1, DEF_GAIN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) priv->autowb = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) priv->blue = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) V4L2_CID_BLUE_BALANCE, 0, 0xff, 1, DEF_BLUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) priv->red = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) V4L2_CID_RED_BALANCE, 0, 0xff, 1, DEF_RED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) V4L2_CID_SATURATION, 0, 0xf, 1, 0x8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) V4L2_CID_HUE, 0, HUE_MASK, 1, DEF_HUE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) V4L2_CID_BRIGHTNESS, 0, 0xff, 1, 0x80);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) priv->autoexposure = v4l2_ctrl_new_std_menu(&priv->hdl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) &ov6550_ctrl_ops, V4L2_CID_EXPOSURE_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) V4L2_EXPOSURE_MANUAL, 0, V4L2_EXPOSURE_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) priv->exposure = v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) V4L2_CID_EXPOSURE, 0, 0xff, 1, DEF_AECH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) v4l2_ctrl_new_std(&priv->hdl, &ov6550_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) V4L2_CID_GAMMA, 0, 0xff, 1, 0x12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) priv->subdev.ctrl_handler = &priv->hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if (priv->hdl.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ret = priv->hdl.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) goto ectlhdlfree;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) v4l2_ctrl_auto_cluster(2, &priv->autogain, 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) v4l2_ctrl_auto_cluster(3, &priv->autowb, 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) v4l2_ctrl_auto_cluster(2, &priv->autoexposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) V4L2_EXPOSURE_MANUAL, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) priv->rect.left = DEF_HSTRT << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) priv->rect.top = DEF_VSTRT << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) priv->rect.width = W_CIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) priv->rect.height = H_CIF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) /* Hardware default frame interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) priv->tpf.numerator = GET_CLKRC_DIV(DEF_CLKRC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) priv->tpf.denominator = FRAME_RATE_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) priv->subdev.internal_ops = &ov6650_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) ret = v4l2_async_register_subdev(&priv->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) ectlhdlfree:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) v4l2_ctrl_handler_free(&priv->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static int ov6650_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) struct ov6650 *priv = to_ov6650(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) v4l2_clk_put(priv->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) v4l2_async_unregister_subdev(&priv->subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) v4l2_ctrl_handler_free(&priv->hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static const struct i2c_device_id ov6650_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) { "ov6650", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) MODULE_DEVICE_TABLE(i2c, ov6650_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) static struct i2c_driver ov6650_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) .name = "ov6650",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) .probe = ov6650_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) .remove = ov6650_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) .id_table = ov6650_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) module_i2c_driver(ov6650_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) MODULE_DESCRIPTION("V4L2 subdevice driver for OmniVision OV6650 camera sensor");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) MODULE_AUTHOR("Janusz Krzysztofik <jmkrzyszt@gmail.com");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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