^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ov5695 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X04 add function g_mbus_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* 45Mhz * 4 Binning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OV5695_PIXEL_RATE (45 * 1000 * 1000 * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OV5695_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CHIP_ID 0x005695
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OV5695_REG_CHIP_ID 0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OV5695_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OV5695_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OV5695_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OV5695_REG_EXPOSURE 0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OV5695_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OV5695_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OV5695_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OV5695_REG_ANALOG_GAIN 0x3509
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ANALOG_GAIN_MIN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ANALOG_GAIN_MAX 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ANALOG_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ANALOG_GAIN_DEFAULT 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OV5695_REG_DIGI_GAIN_H 0x350a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OV5695_REG_DIGI_GAIN_L 0x350b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OV5695_DIGI_GAIN_L_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OV5695_DIGI_GAIN_H_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OV5695_DIGI_GAIN_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OV5695_DIGI_GAIN_MAX (0x4000 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OV5695_DIGI_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OV5695_DIGI_GAIN_DEFAULT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OV5695_REG_TEST_PATTERN 0x4503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OV5695_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OV5695_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OV5695_REG_VTS 0x380e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OV5695_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OV5695_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OV5695_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OV5695_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OV5695_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define I2C_M_WR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define I2C_MSG_MAX 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define I2C_DATA_MAX (I2C_MSG_MAX * 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OV5695_NAME "ov5695"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static const char * const ov5695_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OV5695_NUM_SUPPLIES ARRAY_SIZE(ov5695_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct ov5695_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct ov5695 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct regulator_bulk_data supplies[OV5695_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) const struct ov5695_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define to_ov5695(sd) container_of(sd, struct ov5695, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * Pclk 45Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * linelength 672(0x2a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * framelength 2232(0x8b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * grabwindow_width 1296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * grabwindow_height 972
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * mipi_datarate per lane 840Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static const struct regval ov5695_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {0x0300, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {0x0301, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) {0x0302, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {0x0303, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {0x0304, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {0x0305, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {0x0307, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {0x030b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {0x030c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) {0x030d, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {0x030e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {0x030f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) {0x0312, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {0x3000, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {0x3002, 0xa1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) {0x3008, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {0x3010, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) {0x3022, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {0x3106, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x3107, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x3108, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x3500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x3501, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x3502, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x3503, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x3504, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x3505, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x3507, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x3508, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x3509, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x350c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x350d, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x3510, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x3511, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x3512, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x3601, 0x55},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x3602, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3614, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x3615, 0x77},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x3621, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x3624, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3633, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3634, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3635, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3636, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3638, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3639, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x363a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x363b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x363c, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x363d, 0xfa},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3650, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3651, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3652, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3653, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3654, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x3655, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x3656, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3657, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x3660, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3661, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3662, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x366a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x366e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3673, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3700, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3703, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3715, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3733, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3734, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x373f, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3765, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x37a1, 0x1d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x37a8, 0x26},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x37ab, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x37c2, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x37cb, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x37cc, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x37cd, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x37ce, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3803, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3804, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3805, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3806, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x3807, 0xaf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3808, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3809, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x380a, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x380b, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x380c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x380d, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x380e, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x380f, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x3810, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x3811, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3813, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3814, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3815, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3816, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3817, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3818, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x3819, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x381a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x381b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3820, 0x8b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3821, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3c80, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3c82, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3c83, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x3c88, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3d85, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3f02, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3f03, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x4008, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x4009, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x404e, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x4501, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x4502, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x4800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x481f, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x4837, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x5000, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x5780, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x5781, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x5782, 0x44},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x5783, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x5784, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x5785, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x5786, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x5787, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x5788, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x5789, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x578a, 0xfd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x578b, 0xf5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x578c, 0xf5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x578d, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x578e, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x578f, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x5790, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x5791, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x5792, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x5793, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x5794, 0xa3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x5b00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x5b01, 0x1c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x5b02, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x5b03, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x5b05, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x5e10, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x4010, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x3503, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x3505, 0x8c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x3507, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x3508, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3509, 0xf8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * Pclk 45Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * linelength 740(0x2e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * framelength 2024(0x7e8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * grabwindow_width 2592
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * grabwindow_height 1944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * mipi_datarate per lane 840Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) static const struct regval ov5695_2592x1944_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x3501, 0x7e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x366e, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x3803, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x3804, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x3805, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x3806, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x3807, 0xab},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x3808, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x3809, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x380a, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x380b, 0x98},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x380c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x380d, 0xe4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x380e, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x380f, 0xe8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x3811, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x3813, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x3814, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x3816, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x3817, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x3820, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x4501, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x4008, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x4009, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * Pclk 45Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * linelength 672(0x2a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * framelength 2232(0x8b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * grabwindow_width 1920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * grabwindow_height 1080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) * mipi_datarate per lane 840Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static const struct regval ov5695_1920x1080_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x3501, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x366e, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x3800, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x3801, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x3802, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x3803, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x3804, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x3805, 0xef},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x3806, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x3807, 0xf7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x3808, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x380a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x380b, 0x38},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x380c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x380d, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x380e, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x380f, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x3811, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x3813, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x3814, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x3816, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x3817, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x3820, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x3821, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x4501, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x4008, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x4009, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {REG_NULL, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * Pclk 45Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * linelength 740(0x02e4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * framelength 1012(0x03f4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * grabwindow_width 1296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * grabwindow_height 972
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * max_framerate 60fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * mipi_datarate per lane 840Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static const struct regval ov5695_1296x972_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x3501, 0x3e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x3611, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x3706, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x3714, 0x27},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x3716, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x3717, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x37c3, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x380d, 0xe4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x380e, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x380f, 0xf4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x3811, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x5000, 0x13},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {REG_NULL, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * Pclk 45Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * linelength 672(0x2a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * framelength 2232(0x8b8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * grabwindow_width 1280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * grabwindow_height 720
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * mipi_datarate per lane 840Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static const struct regval ov5695_1280x720_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x3501, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x366e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3802, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x3803, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x3804, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x3805, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x3806, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x3807, 0xaf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x3808, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x3809, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x380a, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x380b, 0xd0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x380c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x380d, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x380e, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x380f, 0xb8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x3811, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x3813, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) {0x3814, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {0x3816, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {0x3817, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x3820, 0x8b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x3821, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x4501, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x4008, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x4009, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {REG_NULL, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * Pclk 45Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * linelength 672(0x2a0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * framelength 558(0x22e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * grabwindow_width 640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * grabwindow_height 480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * max_framerate 120fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * mipi_datarate per lane 840Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const struct regval ov5695_640x480_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x3501, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x366e, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x3803, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x3804, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x3805, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x3806, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x3807, 0xa7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x3808, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x380a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x380b, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x380c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x380d, 0xa0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {0x380e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {0x380f, 0x2e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {0x3811, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x3813, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x3814, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x3816, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x3817, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x3820, 0x8d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x3821, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x4501, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x4008, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x4009, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {REG_NULL, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const struct ov5695_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .width = 2592,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .height = 1944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .exp_def = 0x0450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .hts_def = 0x02e4 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .vts_def = 0x07e8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .reg_list = ov5695_2592x1944_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .exp_def = 0x0450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .hts_def = 0x02a0 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .vts_def = 0x08b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .reg_list = ov5695_1920x1080_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .width = 1296,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .height = 972,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .denominator = 600000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .exp_def = 0x03e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .hts_def = 0x02e4 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) .vts_def = 0x03f4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) .reg_list = ov5695_1296x972_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .height = 720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .exp_def = 0x0450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .hts_def = 0x02a0 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .vts_def = 0x08b8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .reg_list = ov5695_1280x720_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .width = 640,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .height = 480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .denominator = 1200000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .exp_def = 0x0200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .hts_def = 0x02a0 * 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) .vts_def = 0x022e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) .reg_list = ov5695_640x480_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define OV5695_LINK_FREQ_420MHZ 420000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) OV5695_LINK_FREQ_420MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static const char * const ov5695_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static int ov5695_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) static int ov5695_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u8 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u32 i, j = 0, k = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct i2c_msg *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) msg = kmalloc((sizeof(struct i2c_msg) * I2C_MSG_MAX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) data = kmalloc((sizeof(unsigned char) * I2C_DATA_MAX),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) kfree(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) for (i = 0; regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) (msg + j)->addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) (msg + j)->flags = I2C_M_WR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) (msg + j)->buf = (data + k);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) data[k + 0] = (u8)(regs[i].addr >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) data[k + 1] = (u8)(regs[i].addr & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) data[k + 2] = (u8)(regs[i].val & 0xFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) k = k + 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) (msg + j)->len = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (j++ == (I2C_MSG_MAX - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ret = i2c_transfer(client->adapter, msg, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) kfree(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) j = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) k = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (j != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ret = i2c_transfer(client->adapter, msg, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) kfree(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) kfree(msg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) kfree(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int ov5695_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static int ov5695_get_reso_dist(const struct ov5695_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) static const struct ov5695_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ov5695_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dist = ov5695_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) static int ov5695_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct ov5695 *ov5695 = to_ov5695(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) const struct ov5695_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) mutex_lock(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) mode = ov5695_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) mutex_unlock(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ov5695->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) __v4l2_ctrl_modify_range(ov5695->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) __v4l2_ctrl_modify_range(ov5695->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) OV5695_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) mutex_unlock(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int ov5695_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct ov5695 *ov5695 = to_ov5695(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) const struct ov5695_mode *mode = ov5695->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) mutex_lock(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) mutex_unlock(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) mutex_unlock(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int ov5695_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) static int ov5695_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static int ov5695_enable_test_pattern(struct ov5695 *ov5695, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) val = (pattern - 1) | OV5695_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) val = OV5695_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return ov5695_write_reg(ov5695->client, OV5695_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) OV5695_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int ov5695_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct ov5695 *ov5695 = to_ov5695(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) const struct ov5695_mode *mode = ov5695->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) mutex_lock(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) mutex_unlock(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static void ov5695_get_module_inf(struct ov5695 *ov5695,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) strscpy(inf->base.sensor, OV5695_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) strscpy(inf->base.module, ov5695->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) strscpy(inf->base.lens, ov5695->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static long ov5695_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct ov5695 *ov5695 = to_ov5695(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) ov5695_get_module_inf(ov5695, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) ret = ov5695_write_reg(ov5695->client, OV5695_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) OV5695_REG_VALUE_08BIT, OV5695_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) ret = ov5695_write_reg(ov5695->client, OV5695_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) OV5695_REG_VALUE_08BIT, OV5695_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) static long ov5695_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ret = ov5695_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ret = ov5695_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ret = ov5695_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) ret = -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static int __ov5695_start_stream(struct ov5695 *ov5695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ret = ov5695_write_array(ov5695->client, ov5695->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) mutex_unlock(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ret = v4l2_ctrl_handler_setup(&ov5695->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) mutex_lock(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) return ov5695_write_reg(ov5695->client, OV5695_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) OV5695_REG_VALUE_08BIT, OV5695_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) static int __ov5695_stop_stream(struct ov5695 *ov5695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return ov5695_write_reg(ov5695->client, OV5695_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) OV5695_REG_VALUE_08BIT, OV5695_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) static int ov5695_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct ov5695 *ov5695 = to_ov5695(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct i2c_client *client = ov5695->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) mutex_lock(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (on == ov5695->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ret = __ov5695_start_stream(ov5695);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) __ov5695_stop_stream(ov5695);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ov5695->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) mutex_unlock(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) static int ov5695_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) struct ov5695 *ov5695 = to_ov5695(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct i2c_client *client = ov5695->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) mutex_lock(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (ov5695->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ret = ov5695_write_array(ov5695->client, ov5695_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) ov5695->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ov5695->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) mutex_unlock(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static inline u32 ov5695_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return DIV_ROUND_UP(cycles, OV5695_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static int __ov5695_power_on(struct ov5695 *ov5695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct device *dev = &ov5695->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) ret = clk_set_rate(ov5695->xvclk, OV5695_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dev_err(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (clk_get_rate(ov5695->xvclk) != OV5695_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ret = clk_prepare_enable(ov5695->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (!IS_ERR(ov5695->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) gpiod_set_value_cansleep(ov5695->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) ret = regulator_bulk_enable(OV5695_NUM_SUPPLIES, ov5695->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (!IS_ERR(ov5695->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) gpiod_set_value_cansleep(ov5695->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) if (!IS_ERR(ov5695->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) gpiod_set_value_cansleep(ov5695->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) delay_us = ov5695_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) clk_disable_unprepare(ov5695->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static void __ov5695_power_off(struct ov5695 *ov5695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) if (!IS_ERR(ov5695->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) gpiod_set_value_cansleep(ov5695->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) clk_disable_unprepare(ov5695->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (!IS_ERR(ov5695->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) gpiod_set_value_cansleep(ov5695->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) regulator_bulk_disable(OV5695_NUM_SUPPLIES, ov5695->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static int ov5695_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct ov5695 *ov5695 = to_ov5695(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return __ov5695_power_on(ov5695);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static int ov5695_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) struct ov5695 *ov5695 = to_ov5695(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) __ov5695_power_off(ov5695);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static int ov5695_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) struct ov5695 *ov5695 = to_ov5695(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) const struct ov5695_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) mutex_lock(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) mutex_unlock(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) static int ov5695_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) static int ov5695_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) val = 1 << (OV5695_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static const struct dev_pm_ops ov5695_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) SET_RUNTIME_PM_OPS(ov5695_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ov5695_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static const struct v4l2_subdev_internal_ops ov5695_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .open = ov5695_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) static const struct v4l2_subdev_core_ops ov5695_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .s_power = ov5695_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .ioctl = ov5695_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .compat_ioctl32 = ov5695_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static const struct v4l2_subdev_video_ops ov5695_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .s_stream = ov5695_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .g_frame_interval = ov5695_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) static const struct v4l2_subdev_pad_ops ov5695_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .enum_mbus_code = ov5695_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .enum_frame_size = ov5695_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .enum_frame_interval = ov5695_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .get_fmt = ov5695_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .set_fmt = ov5695_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .get_mbus_config = ov5695_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static const struct v4l2_subdev_ops ov5695_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .core = &ov5695_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .video = &ov5695_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .pad = &ov5695_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static int ov5695_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) struct ov5695 *ov5695 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) struct ov5695, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) struct i2c_client *client = ov5695->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) max = ov5695->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) __v4l2_ctrl_modify_range(ov5695->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) ov5695->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ov5695->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) ov5695->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) ret = ov5695_write_reg(ov5695->client, OV5695_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) OV5695_REG_VALUE_24BIT, ctrl->val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ret = ov5695_write_reg(ov5695->client, OV5695_REG_ANALOG_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) OV5695_REG_VALUE_08BIT, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) case V4L2_CID_DIGITAL_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ret = ov5695_write_reg(ov5695->client, OV5695_REG_DIGI_GAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) OV5695_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ctrl->val & OV5695_DIGI_GAIN_L_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) ret |= ov5695_write_reg(ov5695->client, OV5695_REG_DIGI_GAIN_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) OV5695_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) ctrl->val >> OV5695_DIGI_GAIN_H_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) ret = ov5695_write_reg(ov5695->client, OV5695_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) OV5695_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) ctrl->val + ov5695->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ret = ov5695_enable_test_pattern(ov5695, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) static const struct v4l2_ctrl_ops ov5695_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .s_ctrl = ov5695_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static int ov5695_initialize_controls(struct ov5695 *ov5695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) const struct ov5695_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) handler = &ov5695->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) mode = ov5695->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) handler->lock = &ov5695->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) 0, OV5695_PIXEL_RATE, 1, OV5695_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) ov5695->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (ov5695->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) ov5695->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) ov5695->vblank = v4l2_ctrl_new_std(handler, &ov5695_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) OV5695_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) ov5695->exposure = v4l2_ctrl_new_std(handler, &ov5695_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) V4L2_CID_EXPOSURE, OV5695_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) exposure_max, OV5695_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) ov5695->anal_gain = v4l2_ctrl_new_std(handler, &ov5695_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ANALOG_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) /* Digital gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) ov5695->digi_gain = v4l2_ctrl_new_std(handler, &ov5695_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) V4L2_CID_DIGITAL_GAIN, OV5695_DIGI_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) OV5695_DIGI_GAIN_MAX, OV5695_DIGI_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) OV5695_DIGI_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ov5695->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) &ov5695_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) ARRAY_SIZE(ov5695_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) 0, 0, ov5695_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) dev_err(&ov5695->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) ov5695->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static int ov5695_check_sensor_id(struct ov5695 *ov5695,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) struct device *dev = &ov5695->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ret = ov5695_read_reg(client, OV5695_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) OV5695_REG_VALUE_24BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) static int ov5695_configure_regulators(struct ov5695 *ov5695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) for (i = 0; i < OV5695_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) ov5695->supplies[i].supply = ov5695_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return devm_regulator_bulk_get(&ov5695->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) OV5695_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) ov5695->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static int ov5695_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) struct ov5695 *ov5695;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) ov5695 = devm_kzalloc(dev, sizeof(*ov5695), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (!ov5695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) &ov5695->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) &ov5695->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) &ov5695->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) &ov5695->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) ov5695->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) ov5695->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) ov5695->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (IS_ERR(ov5695->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) ov5695->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (IS_ERR(ov5695->reset_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) ov5695->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (IS_ERR(ov5695->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ret = ov5695_configure_regulators(ov5695);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) mutex_init(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) sd = &ov5695->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) v4l2_i2c_subdev_init(sd, client, &ov5695_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) ret = ov5695_initialize_controls(ov5695);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) ret = __ov5695_power_on(ov5695);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) ret = ov5695_check_sensor_id(ov5695, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) sd->internal_ops = &ov5695_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ov5695->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) ret = media_entity_pads_init(&sd->entity, 1, &ov5695->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (strcmp(ov5695->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) ov5695->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) OV5695_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) __ov5695_power_off(ov5695);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) v4l2_ctrl_handler_free(&ov5695->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) mutex_destroy(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) static int ov5695_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) struct ov5695 *ov5695 = to_ov5695(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) v4l2_ctrl_handler_free(&ov5695->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) mutex_destroy(&ov5695->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) __ov5695_power_off(ov5695);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) static const struct of_device_id ov5695_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) { .compatible = "ovti,ov5695" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) MODULE_DEVICE_TABLE(of, ov5695_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) static const struct i2c_device_id ov5695_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) { "ovti,ov5695", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static struct i2c_driver ov5695_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .name = OV5695_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .pm = &ov5695_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .of_match_table = of_match_ptr(ov5695_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .probe = &ov5695_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .remove = &ov5695_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .id_table = ov5695_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) return i2c_add_driver(&ov5695_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) i2c_del_driver(&ov5695_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) MODULE_DESCRIPTION("OmniVision ov5695 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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