^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ov5648 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X04 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X05 add function g_mbus_config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <media/v4l2-common.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-image-sizes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <media/v4l2-mediabus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* verify default register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) //#define CHECK_REG_VALUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MIPI_FREQ 210000000U
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OV5648_PIXEL_RATE (210000000LL * 2LL * 2LL / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OV5648_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CHIP_ID 0x5648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OV5648_REG_CHIP_ID 0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OV5648_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OV5648_MODE_SW_STANDBY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OV5648_MODE_STREAMING 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OV5648_REG_EXPOSURE 0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OV5648_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OV5648_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OV5648_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OV5648_REG_ANALOG_GAIN 0x3509
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ANALOG_GAIN_MIN 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ANALOG_GAIN_MAX 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ANALOG_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ANALOG_GAIN_DEFAULT 0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OV5648_REG_GAIN_H 0x350a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OV5648_REG_GAIN_L 0x350b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OV5648_GAIN_L_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OV5648_GAIN_H_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OV5648_DIGI_GAIN_H_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OV5648_DIGI_GAIN_MIN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OV5648_DIGI_GAIN_MAX (0x4000 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OV5648_DIGI_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OV5648_DIGI_GAIN_DEFAULT 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OV5648_REG_TEST_PATTERN 0x503d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OV5648_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OV5648_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OV5648_REG_VTS 0x380e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OV5648_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OV5648_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OV5648_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OV5648_LANES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OV5648_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define OV5648_NAME "ov5648"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static const char * const ov5648_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define OV5648_NUM_SUPPLIES ARRAY_SIZE(ov5648_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct ov5648_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct ov5648 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct gpio_desc *power_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct regulator_bulk_data supplies[OV5648_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const struct ov5648_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned int lane_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned int cfg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned int pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define to_ov5648(sd) container_of(sd, struct ov5648, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * Pclk 84Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * linelength 2816(0xb00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * framelength 1984(0x7c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * grabwindow_width 2592
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * grabwindow_height 1944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * max_framerate 15fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * mipi_datarate per lane 420Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct regval ov5648_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x3001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x3011, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x3017, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x3018, 0x4c}, //bit[7:5] 001: 1lane;010: 2lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x301c, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x3022, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x3034, 0x1a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x3035, 0x21},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x3036, 0x69},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x3037, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x3038, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x3039, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x303a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x303b, 0x19},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x303c, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x303d, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x3105, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x3106, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x3304, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3305, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3306, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3308, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3309, 0xc8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x330a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x330b, 0x90},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x330c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x330d, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x330e, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x330f, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3300, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3501, 0x3d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3502, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x3503, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x350a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x350b, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3601, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x3602, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3611, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3612, 0x2b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3614, 0x50},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3620, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3622, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3630, 0xad},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3631, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3632, 0x94},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3633, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3634, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x3704, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x3705, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x3708, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3709, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x370b, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x370c, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x370d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x370e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x371c, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3739, 0xd2},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x373c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3801, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3803, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3804, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x3805, 0x3f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3806, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3807, 0xa3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3808, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3809, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x380a, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x380b, 0xcc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x380c, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x380d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x380e, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x380f, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3810, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x3811, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3813, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3814, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3815, 0x31},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3817, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x3820, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x3821, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3826, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3829, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x382b, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3830, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3836, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3837, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x3838, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3839, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x383a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x383b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x3b00, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3b02, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3b03, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3b04, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3b05, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3b06, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x3b07, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x3b08, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x3b09, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3b0a, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x3b0b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3b0c, 0x3d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3f01, 0x0d},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3f0f, 0xf5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x4000, 0x89},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x4001, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x4002, 0x45},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x4004, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x4005, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x4006, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x4007, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x4008, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x4050, 0x6e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x4051, 0x8f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x4300, 0xf8},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x4303, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x4304, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x4307, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x4520, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x4521, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x4511, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x4801, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x4814, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x481f, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x4823, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x4826, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x481b, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x4827, 0x32},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x4837, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x4b00, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x4b01, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x4b04, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x5000, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x5001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x5002, 0x41},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x5003, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x5004, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x5043, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x5013, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x501f, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x503d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x5780, 0xfc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x5781, 0x1f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x5782, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x5786, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x5787, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x5788, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x5789, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x578a, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x578b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x578c, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x578d, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x578e, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x578f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x5790, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x5a00, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x5b00, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x5b01, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x5b02, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x5b03, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) //{0x0100, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * Pclk 84Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * linelength 2816(0xb00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * framelength 1984(0x7c0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * grabwindow_width 2592
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * grabwindow_height 1944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * max_framerate 15fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * mipi_datarate per lane 420Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static const struct regval ov5648_2592x1944_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) // 2592x1944 15fps 2 lane MIPI 420Mbps/lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x3501, 0x7b}, // exposure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x2502, 0x00}, // exposure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x3708, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x3709, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x370c, 0xcc}, // changed by AM05d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x3800, 0x00}, // xstart = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x3801, 0x00}, // xstart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x3802, 0x00}, // ystart = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x3803, 0x00}, // ystart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x3804, 0x0a}, // xend = 2623
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x3805, 0x3f}, // xend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x3806, 0x07}, // yend = 1955
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x3807, 0xa3}, // yend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x3808, 0x0a}, // x output size = 2592
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x3809, 0x20}, // x output size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x380a, 0x07}, // y output size = 1944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x380b, 0x98}, // y output size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x380c, 0x0b}, // hts = 2816
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x380d, 0x00}, // hts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x380e, 0x07}, // vts = 1984
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x380f, 0xc0}, // vts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x3810, 0x00}, // isp x win = 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x3811, 0x10}, // isp x win
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x3812, 0x00}, // isp y win = 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x3813, 0x06}, // isp y win
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x3814, 0x11}, // x inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x3815, 0x11}, // y inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x3817, 0x00}, // hsync start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x3820, 0x40}, // flip off, v bin off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x3821, 0x06}, // mirror on, v bin off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x4004, 0x04}, // black line number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x4005, 0x1a}, // blc always update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x350b, 0x40}, // gain = 4x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x4837, 0x17}, // MIPI global timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) //{0x0100, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * Pclk 84Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * linelength 2816(0xb00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * framelength 992(0x3e0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * grabwindow_width 1296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * grabwindow_height 972
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * max_framerate 30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * mipi_datarate per lane 420Mbps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) static const struct regval ov5648_1296x972_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) // 1296x972 30fps 2 lane MIPI 420Mbps/lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x0100, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x3501, 0x3d}, // exposure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x3502, 0x00}, // exposure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x3708, 0x66},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x3709, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x370c, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x3800, 0x00}, // xstart = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x3801, 0x00}, // x start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x3802, 0x00}, // y start = 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x3803, 0x00}, // y start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x3804, 0x0a}, // xend = 2623
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x3805, 0x3f}, // xend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x3806, 0x07}, // yend = 1955
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x3807, 0xa3}, // yend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x3808, 0x05}, // x output size = 1296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x3809, 0x10}, // x output size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x380a, 0x03}, // y output size = 972
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x380b, 0xcc}, // y output size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x380c, 0x0b}, // hts = 2816
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x380d, 0x00}, // hts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x380e, 0x03}, // vts = 992
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x380f, 0xe0}, // vts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x3810, 0x00}, // isp x win = 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x3811, 0x08}, // isp x win
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x3812, 0x00}, // isp y win = 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x3813, 0x04}, // isp y win
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {0x3814, 0x31}, // x inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3815, 0x31}, // y inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x3817, 0x00}, // hsync start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x3820, 0x08}, // flip off, v bin off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x3821, 0x07}, // mirror on, h bin on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x4004, 0x02}, // black line number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x4005, 0x18}, // blc level trigger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x350b, 0x80}, // gain = 8x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x4837, 0x17}, // MIPI global timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) //{0x0100, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {REG_NULL, 0x00}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) static const struct ov5648_mode supported_modes_2lane[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .width = 2592,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .height = 1944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .denominator = 150000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .exp_def = 0x0450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .hts_def = 0x0b00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .vts_def = 0x07c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .reg_list = ov5648_2592x1944_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .width = 1296,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .height = 972,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .exp_def = 0x03d0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .hts_def = 0x0b00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .vts_def = 0x03e0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .reg_list = ov5648_1296x972_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) static const struct ov5648_mode *supported_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) MIPI_FREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static const char * const ov5648_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) static int ov5648_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) //dev_info(&client->dev, "%s(%d) enter!\n", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) //dev_info(&client->dev, "write reg(0x%x val:0x%x)!\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) if (i2c_master_send(client, buf, len + 2) != len + 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) "write reg(0x%x val:0x%x)failed !\n", reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int ov5648_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) ret = ov5648_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) OV5648_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int ov5648_read_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) unsigned int len, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /* Check Register value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #ifdef CHECK_REG_VALUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int ov5648_reg_verify(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ret = ov5648_read_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) OV5648_REG_VALUE_08BIT, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (value != regs[i].val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) dev_info(&client->dev, "%s:0x%04x is 0x%08x \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) instead of 0x%08x\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) regs[i].addr, value, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static int ov5648_get_reso_dist(const struct ov5648_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static const struct ov5648_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ov5648_find_best_fit(struct ov5648 *ov5648,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) for (i = 0; i < ov5648->cfg_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) dist = ov5648_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) static int ov5648_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct ov5648 *ov5648 = to_ov5648(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) const struct ov5648_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) mutex_lock(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) mode = ov5648_find_best_fit(ov5648, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) mutex_unlock(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ov5648->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) __v4l2_ctrl_modify_range(ov5648->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) __v4l2_ctrl_modify_range(ov5648->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) OV5648_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) mutex_unlock(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int ov5648_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct ov5648 *ov5648 = to_ov5648(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) const struct ov5648_mode *mode = ov5648->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) mutex_lock(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) mutex_unlock(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) mutex_unlock(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static int ov5648_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) static int ov5648_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct ov5648 *ov5648 = to_ov5648(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (fse->index >= ov5648->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int ov5648_enable_test_pattern(struct ov5648 *ov5648, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) val = (pattern - 1) | OV5648_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) val = OV5648_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return ov5648_write_reg(ov5648->client, OV5648_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) OV5648_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static int ov5648_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct ov5648 *ov5648 = to_ov5648(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) const struct ov5648_mode *mode = ov5648->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) mutex_lock(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) mutex_unlock(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static void ov5648_get_module_inf(struct ov5648 *ov5648,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) strlcpy(inf->base.sensor, OV5648_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) strlcpy(inf->base.module, ov5648->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) strlcpy(inf->base.lens, ov5648->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static long ov5648_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct ov5648 *ov5648 = to_ov5648(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ov5648_get_module_inf(ov5648, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ret = ov5648_write_reg(ov5648->client, OV5648_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) OV5648_REG_VALUE_08BIT, OV5648_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) ret = ov5648_write_reg(ov5648->client, OV5648_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) OV5648_REG_VALUE_08BIT, OV5648_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static long ov5648_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ret = ov5648_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ret = ov5648_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ret = ov5648_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) static int __ov5648_start_stream(struct ov5648 *ov5648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) ret = ov5648_write_array(ov5648->client, ov5648->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #ifdef CHECK_REG_VALUE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) usleep_range(10000, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) /* verify default values to make sure everything has */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) /* been written correctly as expected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) dev_info(&ov5648->client->dev, "%s:Check register value!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ret = ov5648_reg_verify(ov5648->client, ov5648_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) ret = ov5648_reg_verify(ov5648->client, ov5648->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) mutex_unlock(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ret = v4l2_ctrl_handler_setup(&ov5648->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) mutex_lock(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ret = ov5648_write_reg(ov5648->client, OV5648_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) OV5648_REG_VALUE_08BIT, OV5648_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) static int __ov5648_stop_stream(struct ov5648 *ov5648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return ov5648_write_reg(ov5648->client, OV5648_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) OV5648_REG_VALUE_08BIT, OV5648_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static int ov5648_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct ov5648 *ov5648 = to_ov5648(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) struct i2c_client *client = ov5648->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) dev_info(&client->dev, "%s(%d) enter!\n", __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) mutex_lock(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) if (on == ov5648->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dev_info(&client->dev, "stream on!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ret = __ov5648_start_stream(ov5648);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dev_info(&client->dev, "stream off!!!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) __ov5648_stop_stream(ov5648);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) ov5648->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) mutex_unlock(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) static int ov5648_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct ov5648 *ov5648 = to_ov5648(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) struct i2c_client *client = ov5648->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) mutex_lock(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) if (ov5648->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ret = ov5648_write_array(ov5648->client, ov5648_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) ov5648->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ov5648->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) mutex_unlock(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) static inline u32 ov5648_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return DIV_ROUND_UP(cycles, OV5648_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static int __ov5648_power_on(struct ov5648 *ov5648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct device *dev = &ov5648->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (!IS_ERR(ov5648->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) gpiod_set_value_cansleep(ov5648->power_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (!IS_ERR_OR_NULL(ov5648->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ret = pinctrl_select_state(ov5648->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ov5648->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ret = clk_set_rate(ov5648->xvclk, OV5648_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (clk_get_rate(ov5648->xvclk) != OV5648_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ret = clk_prepare_enable(ov5648->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (!IS_ERR(ov5648->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) gpiod_set_value_cansleep(ov5648->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ret = regulator_bulk_enable(OV5648_NUM_SUPPLIES, ov5648->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (!IS_ERR(ov5648->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) gpiod_set_value_cansleep(ov5648->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (!IS_ERR(ov5648->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) gpiod_set_value_cansleep(ov5648->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) delay_us = ov5648_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) clk_disable_unprepare(ov5648->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) static void __ov5648_power_off(struct ov5648 *ov5648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct device *dev = &ov5648->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (!IS_ERR(ov5648->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) gpiod_set_value_cansleep(ov5648->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) clk_disable_unprepare(ov5648->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (!IS_ERR(ov5648->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) gpiod_set_value_cansleep(ov5648->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (!IS_ERR_OR_NULL(ov5648->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) ret = pinctrl_select_state(ov5648->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ov5648->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (!IS_ERR(ov5648->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) gpiod_set_value_cansleep(ov5648->power_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) regulator_bulk_disable(OV5648_NUM_SUPPLIES, ov5648->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static int ov5648_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) struct ov5648 *ov5648 = to_ov5648(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) return __ov5648_power_on(ov5648);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) static int ov5648_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) struct ov5648 *ov5648 = to_ov5648(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) __ov5648_power_off(ov5648);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) static int ov5648_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct ov5648 *ov5648 = to_ov5648(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) const struct ov5648_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) mutex_lock(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) mutex_unlock(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) static int ov5648_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct ov5648 *ov5648 = to_ov5648(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (fie->index >= ov5648->cfg_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (fie->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static int ov5648_g_mbus_config(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) val = 1 << (OV5648_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) config->type = V4L2_MBUS_CSI2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) static const struct dev_pm_ops ov5648_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) SET_RUNTIME_PM_OPS(ov5648_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ov5648_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) static const struct v4l2_subdev_internal_ops ov5648_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .open = ov5648_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) static const struct v4l2_subdev_core_ops ov5648_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) .s_power = ov5648_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) .ioctl = ov5648_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) .compat_ioctl32 = ov5648_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) static const struct v4l2_subdev_video_ops ov5648_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .s_stream = ov5648_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) .g_frame_interval = ov5648_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) .g_mbus_config = ov5648_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) static const struct v4l2_subdev_pad_ops ov5648_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) .enum_mbus_code = ov5648_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) .enum_frame_size = ov5648_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) .enum_frame_interval = ov5648_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) .get_fmt = ov5648_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) .set_fmt = ov5648_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) static const struct v4l2_subdev_ops ov5648_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .core = &ov5648_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .video = &ov5648_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .pad = &ov5648_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) static int ov5648_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct ov5648 *ov5648 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct ov5648, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct i2c_client *client = ov5648->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) max = ov5648->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) __v4l2_ctrl_modify_range(ov5648->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ov5648->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) ov5648->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ov5648->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) ret = ov5648_write_reg(ov5648->client, OV5648_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) OV5648_REG_VALUE_24BIT, ctrl->val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) ret = ov5648_write_reg(ov5648->client, OV5648_REG_GAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) OV5648_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ctrl->val & OV5648_GAIN_L_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) ret |= ov5648_write_reg(ov5648->client, OV5648_REG_GAIN_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) OV5648_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) (ctrl->val >> OV5648_DIGI_GAIN_H_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) OV5648_GAIN_H_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ret = ov5648_write_reg(ov5648->client, OV5648_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) OV5648_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) ctrl->val + ov5648->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ret = ov5648_enable_test_pattern(ov5648, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static const struct v4l2_ctrl_ops ov5648_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .s_ctrl = ov5648_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) static int ov5648_initialize_controls(struct ov5648 *ov5648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) const struct ov5648_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) handler = &ov5648->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) mode = ov5648->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) handler->lock = &ov5648->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) 0, ov5648->pixel_rate, 1, ov5648->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) ov5648->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (ov5648->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) ov5648->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ov5648->vblank = v4l2_ctrl_new_std(handler, &ov5648_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) OV5648_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) ov5648->exposure = v4l2_ctrl_new_std(handler, &ov5648_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) V4L2_CID_EXPOSURE, OV5648_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) exposure_max, OV5648_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ov5648->anal_gain = v4l2_ctrl_new_std(handler, &ov5648_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) V4L2_CID_ANALOGUE_GAIN, ANALOG_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) ANALOG_GAIN_MAX, ANALOG_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) ANALOG_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* Digital gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) ov5648->digi_gain = v4l2_ctrl_new_std(handler, &ov5648_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) V4L2_CID_DIGITAL_GAIN, OV5648_DIGI_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) OV5648_DIGI_GAIN_MAX, OV5648_DIGI_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) OV5648_DIGI_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) ov5648->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) &ov5648_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ARRAY_SIZE(ov5648_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) 0, 0, ov5648_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) dev_err(&ov5648->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ov5648->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static int ov5648_check_sensor_id(struct ov5648 *ov5648,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) struct device *dev = &ov5648->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) ret = ov5648_read_reg(client, OV5648_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) OV5648_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) static int ov5648_configure_regulators(struct ov5648 *ov5648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) for (i = 0; i < OV5648_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) ov5648->supplies[i].supply = ov5648_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) return devm_regulator_bulk_get(&ov5648->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) OV5648_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) ov5648->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) static int ov5648_parse_of(struct ov5648 *ov5648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) struct device *dev = &ov5648->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) struct fwnode_handle *fwnode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) int rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) dev_err(dev, "Failed to get endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) fwnode = of_fwnode_handle(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) rval = fwnode_property_read_u32_array(fwnode, "data-lanes", NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (rval <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) dev_warn(dev, " Get mipi lane num failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ov5648->lane_num = rval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (2 == ov5648->lane_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) ov5648->cur_mode = &supported_modes_2lane[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) supported_modes = supported_modes_2lane;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) ov5648->cfg_num = ARRAY_SIZE(supported_modes_2lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) ov5648->pixel_rate = MIPI_FREQ * 2U * ov5648->lane_num / 10U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) dev_info(dev, "lane_num(%d) pixel_rate(%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ov5648->lane_num, ov5648->pixel_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) dev_err(dev, "unsupported lane_num(%d)\n", ov5648->lane_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) static int ov5648_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct ov5648 *ov5648;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) char facing[2] = "b";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) ov5648 = devm_kzalloc(dev, sizeof(*ov5648), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (!ov5648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) &ov5648->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) dev_warn(dev, "could not get module index!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) ov5648->module_index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) &ov5648->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) &ov5648->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) &ov5648->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) ov5648->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) ov5648->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (IS_ERR(ov5648->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) ov5648->power_gpio = devm_gpiod_get(dev, "power", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (IS_ERR(ov5648->power_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) dev_warn(dev, "Failed to get power-gpios, maybe no use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) ov5648->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (IS_ERR(ov5648->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) dev_warn(dev, "Failed to get reset-gpios, maybe no use\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) ov5648->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (IS_ERR(ov5648->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) ret = ov5648_configure_regulators(ov5648);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) ret = ov5648_parse_of(ov5648);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) ov5648->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (!IS_ERR(ov5648->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) ov5648->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) pinctrl_lookup_state(ov5648->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (IS_ERR(ov5648->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) ov5648->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) pinctrl_lookup_state(ov5648->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if (IS_ERR(ov5648->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) mutex_init(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) sd = &ov5648->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) v4l2_i2c_subdev_init(sd, client, &ov5648_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ret = ov5648_initialize_controls(ov5648);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) ret = __ov5648_power_on(ov5648);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) ret = ov5648_check_sensor_id(ov5648, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) dev_info(&client->dev, "%s(%d) Check id failed\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) "check following information:\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) "Power/PowerDown/Reset/Mclk/I2cBus !!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) __func__, __LINE__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) sd->internal_ops = &ov5648_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) ov5648->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) ret = media_entity_pads_init(&sd->entity, 1, &ov5648->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) if (strcmp(ov5648->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) ov5648->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) OV5648_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) __ov5648_power_off(ov5648);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) v4l2_ctrl_handler_free(&ov5648->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) mutex_destroy(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) static int ov5648_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) struct ov5648 *ov5648 = to_ov5648(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) v4l2_ctrl_handler_free(&ov5648->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) mutex_destroy(&ov5648->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) __ov5648_power_off(ov5648);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static const struct of_device_id ov5648_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) { .compatible = "ovti,ov5648" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) MODULE_DEVICE_TABLE(of, ov5648_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) static const struct i2c_device_id ov5648_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) { "ovti,ov5648", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) static struct i2c_driver ov5648_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .name = OV5648_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .pm = &ov5648_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .of_match_table = of_match_ptr(ov5648_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .probe = &ov5648_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .remove = &ov5648_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .id_table = ov5648_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) return i2c_add_driver(&ov5648_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) i2c_del_driver(&ov5648_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) MODULE_DESCRIPTION("OmniVision ov5648 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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