^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the OV5645 camera sensor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2011-2015, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2015 By Tech Design S.L. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2012-2013 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Based on:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * - the OV5645 driver from QC msm-3.10 kernel on codeaurora.org:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * https://us.codeaurora.org/cgit/quic/la/kernel/msm-3.10/tree/drivers/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * media/platform/msm/camera_v2/sensor/ov5645.c?h=LA.BR.1.2.4_rb1.41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * - the OV5640 driver posted on linux-media:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * https://www.mail-archive.com/linux-media%40vger.kernel.org/msg92671.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of_graph.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OV5645_SYSTEM_CTRL0 0x3008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OV5645_SYSTEM_CTRL0_START 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OV5645_SYSTEM_CTRL0_STOP 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OV5645_CHIP_ID_HIGH 0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OV5645_CHIP_ID_HIGH_BYTE 0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OV5645_CHIP_ID_LOW 0x300b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OV5645_CHIP_ID_LOW_BYTE 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OV5645_IO_MIPI_CTRL00 0x300e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OV5645_PAD_OUTPUT00 0x3019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OV5645_AWB_MANUAL_CONTROL 0x3406
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OV5645_AWB_MANUAL_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OV5645_AEC_PK_MANUAL 0x3503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OV5645_AEC_MANUAL_ENABLE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OV5645_AGC_MANUAL_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OV5645_TIMING_TC_REG20 0x3820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OV5645_SENSOR_VFLIP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OV5645_ISP_VFLIP BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OV5645_TIMING_TC_REG21 0x3821
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OV5645_SENSOR_MIRROR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OV5645_MIPI_CTRL00 0x4800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OV5645_PRE_ISP_TEST_SETTING_1 0x503d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OV5645_TEST_PATTERN_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OV5645_SET_TEST_PATTERN(x) ((x) & OV5645_TEST_PATTERN_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OV5645_TEST_PATTERN_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OV5645_SDE_SAT_U 0x5583
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OV5645_SDE_SAT_V 0x5584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* regulator supplies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) static const char * const ov5645_supply_name[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "vdddo", /* Digital I/O (1.8V) supply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "vdda", /* Analog (2.8V) supply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "vddd", /* Digital Core (1.5V) supply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OV5645_NUM_SUPPLIES ARRAY_SIZE(ov5645_supply_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct reg_value {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct ov5645_mode_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) const struct reg_value *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 pixel_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct ov5645 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct i2c_client *i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct v4l2_fwnode_endpoint ep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct v4l2_mbus_framefmt fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct v4l2_rect crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct clk *xclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) struct regulator_bulk_data supplies[OV5645_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) const struct ov5645_mode_info *current_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct v4l2_ctrl_handler ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct v4l2_ctrl *pixel_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct v4l2_ctrl *link_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Cached register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u8 aec_pk_manual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u8 timing_tc_reg20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 timing_tc_reg21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct mutex power_lock; /* lock to protect power state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) int power_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct gpio_desc *enable_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct gpio_desc *rst_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) static inline struct ov5645 *to_ov5645(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return container_of(sd, struct ov5645, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static const struct reg_value ov5645_global_init_setting[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) { 0x3103, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) { 0x3008, 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) { 0x3008, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) { 0x3103, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) { 0x3503, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) { 0x3002, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) { 0x3006, 0xc3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) { 0x3017, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) { 0x3018, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) { 0x302e, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) { 0x3037, 0x13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) { 0x3108, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { 0x3611, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { 0x3500, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { 0x3501, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { 0x3502, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { 0x350a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { 0x350b, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { 0x3620, 0x33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { 0x3621, 0xe0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { 0x3622, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) { 0x3630, 0x2e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) { 0x3631, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { 0x3632, 0x32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { 0x3633, 0x52 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) { 0x3634, 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) { 0x3635, 0x13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) { 0x3636, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) { 0x3703, 0x5a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) { 0x3704, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) { 0x3705, 0x1a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) { 0x3709, 0x12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) { 0x370b, 0x61 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) { 0x370f, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) { 0x3715, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) { 0x3717, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) { 0x371b, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) { 0x3731, 0x12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) { 0x3901, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) { 0x3905, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) { 0x3906, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) { 0x3719, 0x86 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) { 0x3810, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) { 0x3811, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) { 0x3812, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) { 0x3821, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) { 0x3824, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) { 0x3826, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) { 0x3828, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) { 0x3a19, 0xf8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) { 0x3c01, 0x34 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) { 0x3c04, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) { 0x3c05, 0x98 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) { 0x3c07, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) { 0x3c09, 0xc2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) { 0x3c0a, 0x9c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) { 0x3c0b, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) { 0x3c01, 0x34 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) { 0x4001, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) { 0x4514, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) { 0x4520, 0xb0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { 0x460b, 0x37 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { 0x460c, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 0x4818, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { 0x481d, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { 0x481f, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { 0x4823, 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { 0x4831, 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) { 0x5000, 0xa7 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) { 0x5001, 0x83 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) { 0x501d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) { 0x501f, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) { 0x503d, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) { 0x505c, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) { 0x5181, 0x59 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) { 0x5183, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) { 0x5191, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) { 0x5192, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) { 0x5684, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) { 0x5685, 0xa0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) { 0x5686, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) { 0x5687, 0x78 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { 0x5a00, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) { 0x5a21, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) { 0x5a24, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) { 0x3008, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) { 0x3503, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) { 0x5180, 0xff },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) { 0x5181, 0xf2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { 0x5182, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { 0x5183, 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) { 0x5184, 0x25 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) { 0x5185, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) { 0x5186, 0x09 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) { 0x5187, 0x09 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) { 0x5188, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) { 0x5189, 0x75 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) { 0x518a, 0x52 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) { 0x518b, 0xea },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) { 0x518c, 0xa8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { 0x518d, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { 0x518e, 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) { 0x518f, 0x56 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) { 0x5190, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) { 0x5191, 0xf8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) { 0x5192, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) { 0x5193, 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) { 0x5194, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) { 0x5195, 0xf0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) { 0x5196, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) { 0x5197, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) { 0x5198, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) { 0x5199, 0x12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) { 0x519a, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) { 0x519b, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) { 0x519c, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) { 0x519d, 0x82 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) { 0x519e, 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) { 0x5381, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) { 0x5382, 0x5b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { 0x5383, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { 0x5384, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { 0x5385, 0x7e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { 0x5386, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { 0x5387, 0x7c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { 0x5388, 0x6c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { 0x5389, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { 0x538a, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { 0x538b, 0x98 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { 0x5300, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { 0x5301, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { 0x5302, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { 0x5303, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { 0x5304, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { 0x5305, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { 0x5306, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { 0x5307, 0x16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { 0x5309, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { 0x530a, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { 0x530b, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { 0x530c, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { 0x5480, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { 0x5481, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { 0x5482, 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { 0x5483, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { 0x5484, 0x51 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { 0x5485, 0x65 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { 0x5486, 0x71 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { 0x5487, 0x7d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { 0x5488, 0x87 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { 0x5489, 0x91 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { 0x548a, 0x9a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { 0x548b, 0xaa },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { 0x548c, 0xb8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { 0x548d, 0xcd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { 0x548e, 0xdd },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { 0x548f, 0xea },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { 0x5490, 0x1d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { 0x5580, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { 0x5583, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { 0x5584, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { 0x5589, 0x10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { 0x558a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { 0x558b, 0xf8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) { 0x5800, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) { 0x5801, 0x16 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) { 0x5802, 0x0e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) { 0x5803, 0x0d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) { 0x5804, 0x17 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) { 0x5805, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) { 0x5806, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { 0x5807, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) { 0x5808, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) { 0x5809, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) { 0x580a, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) { 0x580b, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) { 0x580c, 0x09 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { 0x580d, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) { 0x580e, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) { 0x580f, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) { 0x5810, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) { 0x5811, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) { 0x5812, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) { 0x5813, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) { 0x5814, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) { 0x5815, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) { 0x5816, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) { 0x5817, 0x09 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) { 0x5818, 0x0f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) { 0x5819, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) { 0x581a, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) { 0x581b, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) { 0x581c, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) { 0x581d, 0x0c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) { 0x581e, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) { 0x581f, 0x1e },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) { 0x5820, 0x12 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) { 0x5821, 0x13 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) { 0x5822, 0x21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) { 0x5823, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) { 0x5824, 0x68 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) { 0x5825, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) { 0x5826, 0x2c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) { 0x5827, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) { 0x5828, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) { 0x5829, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) { 0x582a, 0x64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) { 0x582b, 0x62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) { 0x582c, 0x64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) { 0x582d, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) { 0x582e, 0x46 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) { 0x582f, 0x62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) { 0x5830, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { 0x5831, 0x62 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { 0x5832, 0x26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { 0x5833, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { 0x5834, 0x66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { 0x5835, 0x44 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { 0x5836, 0x64 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { 0x5837, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { 0x5838, 0x66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { 0x5839, 0x48 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) { 0x583a, 0x2c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) { 0x583b, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) { 0x583c, 0x26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) { 0x583d, 0xae },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { 0x5025, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) { 0x3a0f, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) { 0x3a10, 0x28 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { 0x3a1b, 0x30 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) { 0x3a1e, 0x26 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) { 0x3a11, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) { 0x3a1f, 0x14 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) { 0x0601, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) { 0x3008, 0x42 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { 0x3008, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { OV5645_IO_MIPI_CTRL00, 0x40 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { OV5645_MIPI_CTRL00, 0x24 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { OV5645_PAD_OUTPUT00, 0x70 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const struct reg_value ov5645_setting_sxga[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { 0x3612, 0xa9 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { 0x3614, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { 0x3618, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { 0x3034, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { 0x3035, 0x21 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { 0x3036, 0x70 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { 0x3600, 0x09 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) { 0x3601, 0x43 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) { 0x3708, 0x66 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) { 0x370c, 0xc3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) { 0x3800, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) { 0x3801, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) { 0x3802, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) { 0x3803, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { 0x3804, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { 0x3805, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { 0x3806, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { 0x3807, 0x9d },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { 0x3808, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) { 0x3809, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { 0x380a, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { 0x380b, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { 0x380c, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { 0x380d, 0x68 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { 0x380e, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) { 0x380f, 0xd8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { 0x3813, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { 0x3814, 0x31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { 0x3815, 0x31 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { 0x3820, 0x47 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { 0x3a02, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { 0x3a03, 0xd8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) { 0x3a08, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { 0x3a09, 0xf8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { 0x3a0a, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { 0x3a0b, 0xa4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { 0x3a0e, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { 0x3a0d, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { 0x3a14, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) { 0x3a15, 0xd8 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { 0x3a18, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { 0x4004, 0x02 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { 0x4005, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) { 0x4300, 0x32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { 0x4202, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static const struct reg_value ov5645_setting_1080p[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { 0x3612, 0xab },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { 0x3614, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { 0x3618, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) { 0x3034, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { 0x3035, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { 0x3036, 0x54 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { 0x3600, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { 0x3601, 0x33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { 0x3708, 0x63 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) { 0x370c, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { 0x3800, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { 0x3801, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) { 0x3802, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) { 0x3803, 0xb2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) { 0x3804, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) { 0x3805, 0xef },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) { 0x3806, 0x05 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) { 0x3807, 0xf1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) { 0x3808, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) { 0x3809, 0x80 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { 0x380a, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) { 0x380b, 0x38 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) { 0x380c, 0x09 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) { 0x380d, 0xc4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) { 0x380e, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) { 0x380f, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) { 0x3813, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) { 0x3814, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) { 0x3815, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) { 0x3820, 0x47 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) { 0x4514, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) { 0x3a02, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { 0x3a03, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { 0x3a08, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) { 0x3a09, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { 0x3a0a, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) { 0x3a0b, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) { 0x3a0e, 0x03 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { 0x3a0d, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) { 0x3a14, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) { 0x3a15, 0x60 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) { 0x3a18, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) { 0x4004, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) { 0x4005, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) { 0x4300, 0x32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) { 0x4202, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) { 0x4837, 0x0b }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static const struct reg_value ov5645_setting_full[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) { 0x3612, 0xab },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) { 0x3614, 0x50 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) { 0x3618, 0x04 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { 0x3034, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) { 0x3035, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) { 0x3036, 0x54 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) { 0x3600, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) { 0x3601, 0x33 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) { 0x3708, 0x63 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) { 0x370c, 0xc0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) { 0x3800, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) { 0x3801, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) { 0x3802, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) { 0x3803, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) { 0x3804, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) { 0x3805, 0x3f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) { 0x3806, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) { 0x3807, 0x9f },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) { 0x3808, 0x0a },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) { 0x3809, 0x20 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) { 0x380a, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) { 0x380b, 0x98 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) { 0x380c, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) { 0x380d, 0x1c },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) { 0x380e, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) { 0x380f, 0xb0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) { 0x3813, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) { 0x3814, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) { 0x3815, 0x11 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) { 0x3820, 0x47 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) { 0x4514, 0x88 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) { 0x3a02, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) { 0x3a03, 0xb0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) { 0x3a08, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) { 0x3a09, 0x27 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) { 0x3a0a, 0x00 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) { 0x3a0b, 0xf6 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) { 0x3a0e, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) { 0x3a0d, 0x08 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) { 0x3a14, 0x07 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) { 0x3a15, 0xb0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) { 0x3a18, 0x01 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) { 0x4004, 0x06 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) { 0x4005, 0x18 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) { 0x4300, 0x32 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) { 0x4837, 0x0b },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) { 0x4202, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static const s64 link_freq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 224000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 336000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static const struct ov5645_mode_info ov5645_mode_info_data[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .width = 1280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .height = 960,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .data = ov5645_setting_sxga,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) .data_size = ARRAY_SIZE(ov5645_setting_sxga),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) .pixel_clock = 112000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) .link_freq = 0 /* an index in link_freq[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .width = 1920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .height = 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .data = ov5645_setting_1080p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .data_size = ARRAY_SIZE(ov5645_setting_1080p),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .pixel_clock = 168000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .link_freq = 1 /* an index in link_freq[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .width = 2592,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .height = 1944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .data = ov5645_setting_full,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .data_size = ARRAY_SIZE(ov5645_setting_full),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .pixel_clock = 168000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .link_freq = 1 /* an index in link_freq[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int ov5645_write_reg(struct ov5645 *ov5645, u16 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u8 regbuf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) regbuf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) regbuf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) regbuf[2] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret = i2c_master_send(ov5645->i2c_client, regbuf, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) dev_err(ov5645->dev, "%s: write reg error %d: reg=%x, val=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) __func__, ret, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int ov5645_read_reg(struct ov5645 *ov5645, u16 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u8 regbuf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) regbuf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) regbuf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ret = i2c_master_send(ov5645->i2c_client, regbuf, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev_err(ov5645->dev, "%s: write reg error %d: reg=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) __func__, ret, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ret = i2c_master_recv(ov5645->i2c_client, val, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) dev_err(ov5645->dev, "%s: read reg error %d: reg=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) __func__, ret, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static int ov5645_set_aec_mode(struct ov5645 *ov5645, u32 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u8 val = ov5645->aec_pk_manual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (mode == V4L2_EXPOSURE_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) val &= ~OV5645_AEC_MANUAL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) else /* V4L2_EXPOSURE_MANUAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) val |= OV5645_AEC_MANUAL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ret = ov5645_write_reg(ov5645, OV5645_AEC_PK_MANUAL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ov5645->aec_pk_manual = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) static int ov5645_set_agc_mode(struct ov5645 *ov5645, u32 enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) u8 val = ov5645->aec_pk_manual;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) val &= ~OV5645_AGC_MANUAL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) val |= OV5645_AGC_MANUAL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ret = ov5645_write_reg(ov5645, OV5645_AEC_PK_MANUAL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ov5645->aec_pk_manual = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int ov5645_set_register_array(struct ov5645 *ov5645,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) const struct reg_value *settings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) unsigned int num_settings)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) for (i = 0; i < num_settings; ++i, ++settings) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ret = ov5645_write_reg(ov5645, settings->reg, settings->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static int ov5645_set_power_on(struct ov5645 *ov5645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ret = regulator_bulk_enable(OV5645_NUM_SUPPLIES, ov5645->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ret = clk_prepare_enable(ov5645->xclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dev_err(ov5645->dev, "clk prepare enable failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) regulator_bulk_disable(OV5645_NUM_SUPPLIES, ov5645->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) usleep_range(5000, 15000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) gpiod_set_value_cansleep(ov5645->enable_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) gpiod_set_value_cansleep(ov5645->rst_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static void ov5645_set_power_off(struct ov5645 *ov5645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) gpiod_set_value_cansleep(ov5645->rst_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) gpiod_set_value_cansleep(ov5645->enable_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) clk_disable_unprepare(ov5645->xclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) regulator_bulk_disable(OV5645_NUM_SUPPLIES, ov5645->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static int ov5645_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct ov5645 *ov5645 = to_ov5645(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) mutex_lock(&ov5645->power_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* If the power count is modified from 0 to != 0 or from != 0 to 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * update the power state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (ov5645->power_count == !on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) ret = ov5645_set_power_on(ov5645);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ret = ov5645_set_register_array(ov5645,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) ov5645_global_init_setting,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) ARRAY_SIZE(ov5645_global_init_setting));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) dev_err(ov5645->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ov5645_set_power_off(ov5645);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) goto exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ov5645_write_reg(ov5645, OV5645_IO_MIPI_CTRL00, 0x58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ov5645_set_power_off(ov5645);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* Update the power count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) ov5645->power_count += on ? 1 : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) WARN_ON(ov5645->power_count < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) mutex_unlock(&ov5645->power_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static int ov5645_set_saturation(struct ov5645 *ov5645, s32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u32 reg_value = (value * 0x10) + 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ret = ov5645_write_reg(ov5645, OV5645_SDE_SAT_U, reg_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return ov5645_write_reg(ov5645, OV5645_SDE_SAT_V, reg_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static int ov5645_set_hflip(struct ov5645 *ov5645, s32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) u8 val = ov5645->timing_tc_reg21;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) if (value == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) val &= ~(OV5645_SENSOR_MIRROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) val |= (OV5645_SENSOR_MIRROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) ret = ov5645_write_reg(ov5645, OV5645_TIMING_TC_REG21, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ov5645->timing_tc_reg21 = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static int ov5645_set_vflip(struct ov5645 *ov5645, s32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) u8 val = ov5645->timing_tc_reg20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (value == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) val |= (OV5645_SENSOR_VFLIP | OV5645_ISP_VFLIP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) val &= ~(OV5645_SENSOR_VFLIP | OV5645_ISP_VFLIP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) ret = ov5645_write_reg(ov5645, OV5645_TIMING_TC_REG20, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) ov5645->timing_tc_reg20 = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static int ov5645_set_test_pattern(struct ov5645 *ov5645, s32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) val = OV5645_SET_TEST_PATTERN(value - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) val |= OV5645_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return ov5645_write_reg(ov5645, OV5645_PRE_ISP_TEST_SETTING_1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static const char * const ov5645_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) "Vertical Color Bars",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) "Pseudo-Random Data",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) "Color Square",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) "Black Image",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int ov5645_set_awb(struct ov5645 *ov5645, s32 enable_auto)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) u8 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!enable_auto)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) val = OV5645_AWB_MANUAL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return ov5645_write_reg(ov5645, OV5645_AWB_MANUAL_CONTROL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int ov5645_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct ov5645 *ov5645 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) struct ov5645, ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) mutex_lock(&ov5645->power_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (!ov5645->power_count) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) mutex_unlock(&ov5645->power_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) ret = ov5645_set_saturation(ov5645, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) case V4L2_CID_AUTO_WHITE_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret = ov5645_set_awb(ov5645, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) case V4L2_CID_AUTOGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ret = ov5645_set_agc_mode(ov5645, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) case V4L2_CID_EXPOSURE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) ret = ov5645_set_aec_mode(ov5645, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ret = ov5645_set_test_pattern(ov5645, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = ov5645_set_hflip(ov5645, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ret = ov5645_set_vflip(ov5645, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) mutex_unlock(&ov5645->power_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) static const struct v4l2_ctrl_ops ov5645_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .s_ctrl = ov5645_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int ov5645_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (code->index > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) code->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) static int ov5645_enum_frame_size(struct v4l2_subdev *subdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if (fse->code != MEDIA_BUS_FMT_UYVY8_2X8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (fse->index >= ARRAY_SIZE(ov5645_mode_info_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) fse->min_width = ov5645_mode_info_data[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) fse->max_width = ov5645_mode_info_data[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) fse->min_height = ov5645_mode_info_data[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) fse->max_height = ov5645_mode_info_data[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) static struct v4l2_mbus_framefmt *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) __ov5645_get_pad_format(struct ov5645 *ov5645,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) unsigned int pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) enum v4l2_subdev_format_whence which)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) switch (which) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) case V4L2_SUBDEV_FORMAT_TRY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return v4l2_subdev_get_try_format(&ov5645->sd, cfg, pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) case V4L2_SUBDEV_FORMAT_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return &ov5645->fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) static int ov5645_get_format(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct ov5645 *ov5645 = to_ov5645(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) format->format = *__ov5645_get_pad_format(ov5645, cfg, format->pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) format->which);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static struct v4l2_rect *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) __ov5645_get_pad_crop(struct ov5645 *ov5645, struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) unsigned int pad, enum v4l2_subdev_format_whence which)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) switch (which) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) case V4L2_SUBDEV_FORMAT_TRY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) return v4l2_subdev_get_try_crop(&ov5645->sd, cfg, pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) case V4L2_SUBDEV_FORMAT_ACTIVE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return &ov5645->crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static int ov5645_set_format(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct ov5645 *ov5645 = to_ov5645(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) struct v4l2_mbus_framefmt *__format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct v4l2_rect *__crop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) const struct ov5645_mode_info *new_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) __crop = __ov5645_get_pad_crop(ov5645, cfg, format->pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) format->which);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) new_mode = v4l2_find_nearest_size(ov5645_mode_info_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) ARRAY_SIZE(ov5645_mode_info_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) width, height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) format->format.width, format->format.height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) __crop->width = new_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) __crop->height = new_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ret = v4l2_ctrl_s_ctrl_int64(ov5645->pixel_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) new_mode->pixel_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ret = v4l2_ctrl_s_ctrl(ov5645->link_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) new_mode->link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ov5645->current_mode = new_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) __format = __ov5645_get_pad_format(ov5645, cfg, format->pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) format->which);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) __format->width = __crop->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) __format->height = __crop->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) __format->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) __format->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) __format->colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) format->format = *__format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static int ov5645_entity_init_cfg(struct v4l2_subdev *subdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct v4l2_subdev_pad_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct v4l2_subdev_format fmt = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) fmt.which = cfg ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) fmt.format.width = 1920;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) fmt.format.height = 1080;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ov5645_set_format(subdev, cfg, &fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static int ov5645_get_selection(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct v4l2_subdev_selection *sel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) struct ov5645 *ov5645 = to_ov5645(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (sel->target != V4L2_SEL_TGT_CROP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) sel->r = *__ov5645_get_pad_crop(ov5645, cfg, sel->pad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) sel->which);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static int ov5645_s_stream(struct v4l2_subdev *subdev, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct ov5645 *ov5645 = to_ov5645(subdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ret = ov5645_set_register_array(ov5645,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ov5645->current_mode->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ov5645->current_mode->data_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) dev_err(ov5645->dev, "could not set mode %dx%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) ov5645->current_mode->width,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ov5645->current_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ret = v4l2_ctrl_handler_setup(&ov5645->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) dev_err(ov5645->dev, "could not sync v4l2 controls\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ret = ov5645_write_reg(ov5645, OV5645_IO_MIPI_CTRL00, 0x45);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ret = ov5645_write_reg(ov5645, OV5645_SYSTEM_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) OV5645_SYSTEM_CTRL0_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) ret = ov5645_write_reg(ov5645, OV5645_IO_MIPI_CTRL00, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) ret = ov5645_write_reg(ov5645, OV5645_SYSTEM_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) OV5645_SYSTEM_CTRL0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) static const struct v4l2_subdev_core_ops ov5645_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) .s_power = ov5645_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static const struct v4l2_subdev_video_ops ov5645_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) .s_stream = ov5645_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static const struct v4l2_subdev_pad_ops ov5645_subdev_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .init_cfg = ov5645_entity_init_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .enum_mbus_code = ov5645_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) .enum_frame_size = ov5645_enum_frame_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) .get_fmt = ov5645_get_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) .set_fmt = ov5645_set_format,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) .get_selection = ov5645_get_selection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static const struct v4l2_subdev_ops ov5645_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .core = &ov5645_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) .video = &ov5645_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .pad = &ov5645_subdev_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) static int ov5645_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct device_node *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct ov5645 *ov5645;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) u8 chip_id_high, chip_id_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) u32 xclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) ov5645 = devm_kzalloc(dev, sizeof(struct ov5645), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (!ov5645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ov5645->i2c_client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) ov5645->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) endpoint = of_graph_get_next_endpoint(dev->of_node, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) dev_err(dev, "endpoint node not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ret = v4l2_fwnode_endpoint_parse(of_fwnode_handle(endpoint),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) &ov5645->ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) of_node_put(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) dev_err(dev, "parsing endpoint node failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) if (ov5645->ep.bus_type != V4L2_MBUS_CSI2_DPHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) dev_err(dev, "invalid bus type, must be CSI2\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) /* get system clock (xclk) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) ov5645->xclk = devm_clk_get(dev, "xclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (IS_ERR(ov5645->xclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) dev_err(dev, "could not get xclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) return PTR_ERR(ov5645->xclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) ret = of_property_read_u32(dev->of_node, "clock-frequency", &xclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) dev_err(dev, "could not get xclk frequency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* external clock must be 24MHz, allow 1% tolerance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (xclk_freq < 23760000 || xclk_freq > 24240000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) dev_err(dev, "external clock frequency %u is not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) xclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) ret = clk_set_rate(ov5645->xclk, xclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) dev_err(dev, "could not set xclk frequency\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) for (i = 0; i < OV5645_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ov5645->supplies[i].supply = ov5645_supply_name[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) ret = devm_regulator_bulk_get(dev, OV5645_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) ov5645->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ov5645->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) if (IS_ERR(ov5645->enable_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) dev_err(dev, "cannot get enable gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return PTR_ERR(ov5645->enable_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) ov5645->rst_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (IS_ERR(ov5645->rst_gpio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) dev_err(dev, "cannot get reset gpio\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return PTR_ERR(ov5645->rst_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) mutex_init(&ov5645->power_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) v4l2_ctrl_handler_init(&ov5645->ctrls, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) V4L2_CID_SATURATION, -4, 4, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) v4l2_ctrl_new_std(&ov5645->ctrls, &ov5645_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) V4L2_CID_AUTO_WHITE_BALANCE, 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) v4l2_ctrl_new_std_menu(&ov5645->ctrls, &ov5645_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) 0, V4L2_EXPOSURE_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) v4l2_ctrl_new_std_menu_items(&ov5645->ctrls, &ov5645_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ARRAY_SIZE(ov5645_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) 0, 0, ov5645_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ov5645->pixel_clock = v4l2_ctrl_new_std(&ov5645->ctrls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) &ov5645_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) 1, INT_MAX, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ov5645->link_freq = v4l2_ctrl_new_int_menu(&ov5645->ctrls,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) &ov5645_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) ARRAY_SIZE(link_freq) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) 0, link_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (ov5645->link_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) ov5645->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ov5645->sd.ctrl_handler = &ov5645->ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (ov5645->ctrls.error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) dev_err(dev, "%s: control initialization error %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) __func__, ov5645->ctrls.error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) ret = ov5645->ctrls.error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) goto free_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) v4l2_i2c_subdev_init(&ov5645->sd, client, &ov5645_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) ov5645->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) ov5645->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ov5645->sd.dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) ov5645->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) ret = media_entity_pads_init(&ov5645->sd.entity, 1, &ov5645->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) dev_err(dev, "could not register media entity\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) goto free_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ret = ov5645_s_power(&ov5645->sd, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) dev_err(dev, "could not power up OV5645\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) goto free_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) ret = ov5645_read_reg(ov5645, OV5645_CHIP_ID_HIGH, &chip_id_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (ret < 0 || chip_id_high != OV5645_CHIP_ID_HIGH_BYTE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) dev_err(dev, "could not read ID high\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) goto power_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ret = ov5645_read_reg(ov5645, OV5645_CHIP_ID_LOW, &chip_id_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (ret < 0 || chip_id_low != OV5645_CHIP_ID_LOW_BYTE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) dev_err(dev, "could not read ID low\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) goto power_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) dev_info(dev, "OV5645 detected at address 0x%02x\n", client->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) ret = ov5645_read_reg(ov5645, OV5645_AEC_PK_MANUAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) &ov5645->aec_pk_manual);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) dev_err(dev, "could not read AEC/AGC mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) goto power_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) ret = ov5645_read_reg(ov5645, OV5645_TIMING_TC_REG20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) &ov5645->timing_tc_reg20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dev_err(dev, "could not read vflip value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) goto power_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) ret = ov5645_read_reg(ov5645, OV5645_TIMING_TC_REG21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) &ov5645->timing_tc_reg21);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) dev_err(dev, "could not read hflip value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) goto power_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) ov5645_s_power(&ov5645->sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) ret = v4l2_async_register_subdev(&ov5645->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) dev_err(dev, "could not register v4l2 device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) goto free_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ov5645_entity_init_cfg(&ov5645->sd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) power_down:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ov5645_s_power(&ov5645->sd, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) free_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) media_entity_cleanup(&ov5645->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) free_ctrl:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) v4l2_ctrl_handler_free(&ov5645->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) mutex_destroy(&ov5645->power_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static int ov5645_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct ov5645 *ov5645 = to_ov5645(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) v4l2_async_unregister_subdev(&ov5645->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) media_entity_cleanup(&ov5645->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) v4l2_ctrl_handler_free(&ov5645->ctrls);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) mutex_destroy(&ov5645->power_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static const struct i2c_device_id ov5645_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) { "ov5645", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) MODULE_DEVICE_TABLE(i2c, ov5645_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) static const struct of_device_id ov5645_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) { .compatible = "ovti,ov5645" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) MODULE_DEVICE_TABLE(of, ov5645_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) static struct i2c_driver ov5645_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) .of_match_table = of_match_ptr(ov5645_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .name = "ov5645",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) .probe_new = ov5645_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) .remove = ov5645_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) .id_table = ov5645_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) module_i2c_driver(ov5645_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) MODULE_DESCRIPTION("Omnivision OV5645 Camera Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) MODULE_AUTHOR("Todor Tomov <todor.tomov@linaro.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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