^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014-2017 Mentor Graphics Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk-provider.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clkdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/v4l2-device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-event.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-fwnode.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* min/typical/max system clock (xclk) frequencies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define OV5640_XCLK_MIN 6000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define OV5640_XCLK_MAX 54000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define OV5640_DEFAULT_SLAVE_ID 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define OV5640_REG_SYS_RESET02 0x3002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OV5640_REG_SYS_CLOCK_ENABLE02 0x3006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OV5640_REG_SYS_CTRL0 0x3008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OV5640_REG_SYS_CTRL0_SW_PWDN 0x42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OV5640_REG_SYS_CTRL0_SW_PWUP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OV5640_REG_CHIP_ID 0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define OV5640_REG_IO_MIPI_CTRL00 0x300e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OV5640_REG_PAD_OUTPUT_ENABLE01 0x3017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OV5640_REG_PAD_OUTPUT_ENABLE02 0x3018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OV5640_REG_PAD_OUTPUT00 0x3019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OV5640_REG_SYSTEM_CONTROL1 0x302e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define OV5640_REG_SC_PLL_CTRL0 0x3034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OV5640_REG_SC_PLL_CTRL1 0x3035
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OV5640_REG_SC_PLL_CTRL2 0x3036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OV5640_REG_SC_PLL_CTRL3 0x3037
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define OV5640_REG_SLAVE_ID 0x3100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OV5640_REG_SCCB_SYS_CTRL1 0x3103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OV5640_REG_SYS_ROOT_DIVIDER 0x3108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OV5640_REG_AWB_R_GAIN 0x3400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OV5640_REG_AWB_G_GAIN 0x3402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OV5640_REG_AWB_B_GAIN 0x3404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OV5640_REG_AWB_MANUAL_CTRL 0x3406
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OV5640_REG_AEC_PK_EXPOSURE_HI 0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OV5640_REG_AEC_PK_EXPOSURE_MED 0x3501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OV5640_REG_AEC_PK_EXPOSURE_LO 0x3502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OV5640_REG_AEC_PK_MANUAL 0x3503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OV5640_REG_AEC_PK_REAL_GAIN 0x350a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OV5640_REG_AEC_PK_VTS 0x350c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OV5640_REG_TIMING_DVPHO 0x3808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OV5640_REG_TIMING_DVPVO 0x380a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OV5640_REG_TIMING_HTS 0x380c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OV5640_REG_TIMING_VTS 0x380e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OV5640_REG_TIMING_TC_REG20 0x3820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OV5640_REG_TIMING_TC_REG21 0x3821
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OV5640_REG_AEC_CTRL00 0x3a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OV5640_REG_AEC_B50_STEP 0x3a08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OV5640_REG_AEC_B60_STEP 0x3a0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define OV5640_REG_AEC_CTRL0D 0x3a0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OV5640_REG_AEC_CTRL0E 0x3a0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OV5640_REG_AEC_CTRL0F 0x3a0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OV5640_REG_AEC_CTRL10 0x3a10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OV5640_REG_AEC_CTRL11 0x3a11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OV5640_REG_AEC_CTRL1B 0x3a1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OV5640_REG_AEC_CTRL1E 0x3a1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OV5640_REG_AEC_CTRL1F 0x3a1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OV5640_REG_HZ5060_CTRL00 0x3c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OV5640_REG_HZ5060_CTRL01 0x3c01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OV5640_REG_SIGMADELTA_CTRL0C 0x3c0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OV5640_REG_FRAME_CTRL01 0x4202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OV5640_REG_FORMAT_CONTROL00 0x4300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OV5640_REG_VFIFO_HSIZE 0x4602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OV5640_REG_VFIFO_VSIZE 0x4604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OV5640_REG_JPG_MODE_SELECT 0x4713
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define OV5640_REG_CCIR656_CTRL00 0x4730
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OV5640_REG_POLARITY_CTRL00 0x4740
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define OV5640_REG_MIPI_CTRL00 0x4800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OV5640_REG_DEBUG_MODE 0x4814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OV5640_REG_ISP_FORMAT_MUX_CTRL 0x501f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OV5640_REG_PRE_ISP_TEST_SET1 0x503d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OV5640_REG_SDE_CTRL0 0x5580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OV5640_REG_SDE_CTRL1 0x5581
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OV5640_REG_SDE_CTRL3 0x5583
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OV5640_REG_SDE_CTRL4 0x5584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OV5640_REG_SDE_CTRL5 0x5585
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OV5640_REG_AVG_READOUT 0x56a1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) enum ov5640_mode_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) OV5640_MODE_QCIF_176_144 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) OV5640_MODE_QVGA_320_240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) OV5640_MODE_VGA_640_480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) OV5640_MODE_NTSC_720_480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) OV5640_MODE_PAL_720_576,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) OV5640_MODE_XGA_1024_768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) OV5640_MODE_720P_1280_720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) OV5640_MODE_1080P_1920_1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) OV5640_MODE_QSXGA_2592_1944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) OV5640_NUM_MODES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) enum ov5640_frame_rate {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) OV5640_15_FPS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) OV5640_30_FPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) OV5640_60_FPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) OV5640_NUM_FRAMERATES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) enum ov5640_format_mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) OV5640_FMT_MUX_YUV422 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) OV5640_FMT_MUX_RGB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) OV5640_FMT_MUX_DITHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) OV5640_FMT_MUX_RAW_DPC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) OV5640_FMT_MUX_SNR_RAW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) OV5640_FMT_MUX_RAW_CIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct ov5640_pixfmt {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) static const struct ov5640_pixfmt ov5640_formats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) { MEDIA_BUS_FMT_JPEG_1X8, V4L2_COLORSPACE_JPEG, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) { MEDIA_BUS_FMT_UYVY8_2X8, V4L2_COLORSPACE_SRGB, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) { MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_SRGB, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) { MEDIA_BUS_FMT_RGB565_2X8_LE, V4L2_COLORSPACE_SRGB, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) { MEDIA_BUS_FMT_RGB565_2X8_BE, V4L2_COLORSPACE_SRGB, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) { MEDIA_BUS_FMT_SBGGR8_1X8, V4L2_COLORSPACE_SRGB, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { MEDIA_BUS_FMT_SGBRG8_1X8, V4L2_COLORSPACE_SRGB, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { MEDIA_BUS_FMT_SGRBG8_1X8, V4L2_COLORSPACE_SRGB, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) { MEDIA_BUS_FMT_SRGGB8_1X8, V4L2_COLORSPACE_SRGB, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * FIXME: remove this when a subdev API becomes available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * to set the MIPI CSI-2 virtual channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static unsigned int virtual_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) module_param(virtual_channel, uint, 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) MODULE_PARM_DESC(virtual_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) "MIPI CSI-2 virtual channel (0..3), default 0");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static const int ov5640_framerates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) [OV5640_15_FPS] = 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) [OV5640_30_FPS] = 30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) [OV5640_60_FPS] = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* regulator supplies */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static const char * const ov5640_supply_name[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "DOVDD", /* Digital I/O (1.8V) supply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "AVDD", /* Analog (2.8V) supply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "DVDD", /* Digital Core (1.5V) supply */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define OV5640_NUM_SUPPLIES ARRAY_SIZE(ov5640_supply_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * Image size under 1280 * 960 are SUBSAMPLING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * Image size upper 1280 * 960 are SCALING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) enum ov5640_downsize_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) SUBSAMPLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) SCALING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct reg_value {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u16 reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u8 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 delay_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct ov5640_mode_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) enum ov5640_mode_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) enum ov5640_downsize_mode dn_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 hact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 htot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 vact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 vtot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) const struct reg_value *reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 reg_data_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct ov5640_ctrls {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct v4l2_ctrl_handler handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct v4l2_ctrl *pixel_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct v4l2_ctrl *auto_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct v4l2_ctrl *auto_wb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct v4l2_ctrl *blue_balance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct v4l2_ctrl *red_balance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct v4l2_ctrl *auto_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct v4l2_ctrl *gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct v4l2_ctrl *brightness;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct v4l2_ctrl *light_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct v4l2_ctrl *saturation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct v4l2_ctrl *contrast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct v4l2_ctrl *hue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct v4l2_ctrl *hflip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct v4l2_ctrl *vflip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct ov5640_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct i2c_client *i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct v4l2_subdev sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct v4l2_fwnode_endpoint ep; /* the parsed DT endpoint info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct clk *xclk; /* system clock to OV5640 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 xclk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct regulator_bulk_data supplies[OV5640_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) bool upside_down;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* lock to protect all members below */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) int power_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct v4l2_mbus_framefmt fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) bool pending_fmt_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) const struct ov5640_mode_info *current_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) const struct ov5640_mode_info *last_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) enum ov5640_frame_rate current_fr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct v4l2_fract frame_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct ov5640_ctrls ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 prev_sysclk, prev_hts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u32 ae_low, ae_high, ae_target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) bool pending_mode_change;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static inline struct ov5640_dev *to_ov5640_dev(struct v4l2_subdev *sd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return container_of(sd, struct ov5640_dev, sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return &container_of(ctrl->handler, struct ov5640_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) ctrls.handler)->sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * FIXME: all of these register tables are likely filled with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * entries that set the register to their power-on default values,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * and which are otherwise not touched by this driver. Those entries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * should be identified and removed to speed register load time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * over i2c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* YUV422 UYVY VGA@30fps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) static const struct reg_value ov5640_init_setting_30fps_VGA[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3103, 0x11, 0, 0}, {0x3008, 0x82, 0, 5}, {0x3008, 0x42, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x3103, 0x03, 0, 0}, {0x3630, 0x36, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3631, 0x0e, 0, 0}, {0x3632, 0xe2, 0, 0}, {0x3633, 0x12, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3621, 0xe0, 0, 0}, {0x3704, 0xa0, 0, 0}, {0x3703, 0x5a, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3715, 0x78, 0, 0}, {0x3717, 0x01, 0, 0}, {0x370b, 0x60, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x3705, 0x1a, 0, 0}, {0x3905, 0x02, 0, 0}, {0x3906, 0x10, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x3901, 0x0a, 0, 0}, {0x3731, 0x12, 0, 0}, {0x3600, 0x08, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x3601, 0x33, 0, 0}, {0x302d, 0x60, 0, 0}, {0x3620, 0x52, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x371b, 0x20, 0, 0}, {0x471c, 0x50, 0, 0}, {0x3a13, 0x43, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x3a18, 0x00, 0, 0}, {0x3a19, 0xf8, 0, 0}, {0x3635, 0x13, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x3636, 0x03, 0, 0}, {0x3634, 0x40, 0, 0}, {0x3622, 0x01, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x3c01, 0xa4, 0, 0}, {0x3c04, 0x28, 0, 0}, {0x3c05, 0x98, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x3c06, 0x00, 0, 0}, {0x3c07, 0x08, 0, 0}, {0x3c08, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x3820, 0x41, 0, 0}, {0x3821, 0x07, 0, 0}, {0x3814, 0x31, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3810, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0}, {0x3000, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x3002, 0x1c, 0, 0}, {0x3004, 0xff, 0, 0}, {0x3006, 0xc3, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x302e, 0x08, 0, 0}, {0x4300, 0x3f, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x501f, 0x00, 0, 0}, {0x4407, 0x04, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x440e, 0x00, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x4837, 0x0a, 0, 0}, {0x3824, 0x02, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x5000, 0xa7, 0, 0}, {0x5001, 0xa3, 0, 0}, {0x5180, 0xff, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x5181, 0xf2, 0, 0}, {0x5182, 0x00, 0, 0}, {0x5183, 0x14, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x5184, 0x25, 0, 0}, {0x5185, 0x24, 0, 0}, {0x5186, 0x09, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x5187, 0x09, 0, 0}, {0x5188, 0x09, 0, 0}, {0x5189, 0x88, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x518a, 0x54, 0, 0}, {0x518b, 0xee, 0, 0}, {0x518c, 0xb2, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x518d, 0x50, 0, 0}, {0x518e, 0x34, 0, 0}, {0x518f, 0x6b, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x5190, 0x46, 0, 0}, {0x5191, 0xf8, 0, 0}, {0x5192, 0x04, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x5193, 0x70, 0, 0}, {0x5194, 0xf0, 0, 0}, {0x5195, 0xf0, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x5196, 0x03, 0, 0}, {0x5197, 0x01, 0, 0}, {0x5198, 0x04, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x5199, 0x6c, 0, 0}, {0x519a, 0x04, 0, 0}, {0x519b, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x519c, 0x09, 0, 0}, {0x519d, 0x2b, 0, 0}, {0x519e, 0x38, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x5381, 0x1e, 0, 0}, {0x5382, 0x5b, 0, 0}, {0x5383, 0x08, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x5384, 0x0a, 0, 0}, {0x5385, 0x7e, 0, 0}, {0x5386, 0x88, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x5387, 0x7c, 0, 0}, {0x5388, 0x6c, 0, 0}, {0x5389, 0x10, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x538a, 0x01, 0, 0}, {0x538b, 0x98, 0, 0}, {0x5300, 0x08, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x5301, 0x30, 0, 0}, {0x5302, 0x10, 0, 0}, {0x5303, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x5304, 0x08, 0, 0}, {0x5305, 0x30, 0, 0}, {0x5306, 0x08, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x5307, 0x16, 0, 0}, {0x5309, 0x08, 0, 0}, {0x530a, 0x30, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x530b, 0x04, 0, 0}, {0x530c, 0x06, 0, 0}, {0x5480, 0x01, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x5481, 0x08, 0, 0}, {0x5482, 0x14, 0, 0}, {0x5483, 0x28, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x5484, 0x51, 0, 0}, {0x5485, 0x65, 0, 0}, {0x5486, 0x71, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x5487, 0x7d, 0, 0}, {0x5488, 0x87, 0, 0}, {0x5489, 0x91, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x548a, 0x9a, 0, 0}, {0x548b, 0xaa, 0, 0}, {0x548c, 0xb8, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x548d, 0xcd, 0, 0}, {0x548e, 0xdd, 0, 0}, {0x548f, 0xea, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x5490, 0x1d, 0, 0}, {0x5580, 0x02, 0, 0}, {0x5583, 0x40, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x5584, 0x10, 0, 0}, {0x5589, 0x10, 0, 0}, {0x558a, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x558b, 0xf8, 0, 0}, {0x5800, 0x23, 0, 0}, {0x5801, 0x14, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x5802, 0x0f, 0, 0}, {0x5803, 0x0f, 0, 0}, {0x5804, 0x12, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x5805, 0x26, 0, 0}, {0x5806, 0x0c, 0, 0}, {0x5807, 0x08, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x5808, 0x05, 0, 0}, {0x5809, 0x05, 0, 0}, {0x580a, 0x08, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x580b, 0x0d, 0, 0}, {0x580c, 0x08, 0, 0}, {0x580d, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x580e, 0x00, 0, 0}, {0x580f, 0x00, 0, 0}, {0x5810, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x5811, 0x09, 0, 0}, {0x5812, 0x07, 0, 0}, {0x5813, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x5814, 0x00, 0, 0}, {0x5815, 0x01, 0, 0}, {0x5816, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x5817, 0x08, 0, 0}, {0x5818, 0x0d, 0, 0}, {0x5819, 0x08, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x581a, 0x05, 0, 0}, {0x581b, 0x06, 0, 0}, {0x581c, 0x08, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x581d, 0x0e, 0, 0}, {0x581e, 0x29, 0, 0}, {0x581f, 0x17, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x5820, 0x11, 0, 0}, {0x5821, 0x11, 0, 0}, {0x5822, 0x15, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x5823, 0x28, 0, 0}, {0x5824, 0x46, 0, 0}, {0x5825, 0x26, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x5826, 0x08, 0, 0}, {0x5827, 0x26, 0, 0}, {0x5828, 0x64, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x5829, 0x26, 0, 0}, {0x582a, 0x24, 0, 0}, {0x582b, 0x22, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x582c, 0x24, 0, 0}, {0x582d, 0x24, 0, 0}, {0x582e, 0x06, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x582f, 0x22, 0, 0}, {0x5830, 0x40, 0, 0}, {0x5831, 0x42, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x5832, 0x24, 0, 0}, {0x5833, 0x26, 0, 0}, {0x5834, 0x24, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x5835, 0x22, 0, 0}, {0x5836, 0x22, 0, 0}, {0x5837, 0x26, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x5838, 0x44, 0, 0}, {0x5839, 0x24, 0, 0}, {0x583a, 0x26, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x583b, 0x28, 0, 0}, {0x583c, 0x42, 0, 0}, {0x583d, 0xce, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x5025, 0x00, 0, 0}, {0x3a0f, 0x30, 0, 0}, {0x3a10, 0x28, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x3a1b, 0x30, 0, 0}, {0x3a1e, 0x26, 0, 0}, {0x3a11, 0x60, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x3a1f, 0x14, 0, 0}, {0x3008, 0x02, 0, 0}, {0x3c00, 0x04, 0, 300},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) static const struct reg_value ov5640_setting_VGA_640_480[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x3c07, 0x08, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x3814, 0x31, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x3810, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static const struct reg_value ov5640_setting_XGA_1024_768[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x3c07, 0x08, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x3814, 0x31, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x3810, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static const struct reg_value ov5640_setting_QVGA_320_240[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x3c07, 0x08, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x3814, 0x31, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x3810, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) static const struct reg_value ov5640_setting_QCIF_176_144[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x3c07, 0x08, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x3814, 0x31, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0x3810, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const struct reg_value ov5640_setting_NTSC_720_480[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3c07, 0x08, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x3814, 0x31, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x3810, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x3c, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static const struct reg_value ov5640_setting_PAL_720_576[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x3c07, 0x08, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {0x3814, 0x31, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x3802, 0x00, 0, 0}, {0x3803, 0x04, 0, 0}, {0x3804, 0x0a, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9b, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x3810, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x3811, 0x38, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x06, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {0x3824, 0x02, 0, 0}, {0x5001, 0xa3, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const struct reg_value ov5640_setting_720P_1280_720[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {0x3c07, 0x07, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {0x3814, 0x31, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {0x3815, 0x31, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {0x3802, 0x00, 0, 0}, {0x3803, 0xfa, 0, 0}, {0x3804, 0x0a, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {0x3805, 0x3f, 0, 0}, {0x3806, 0x06, 0, 0}, {0x3807, 0xa9, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {0x3810, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {0x3618, 0x00, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x64, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {0x3709, 0x52, 0, 0}, {0x370c, 0x03, 0, 0}, {0x3a02, 0x02, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) {0x3a03, 0xe4, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0xbc, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x72, 0, 0}, {0x3a0e, 0x01, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) {0x3a0d, 0x02, 0, 0}, {0x3a14, 0x02, 0, 0}, {0x3a15, 0xe4, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {0x4001, 0x02, 0, 0}, {0x4004, 0x02, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {0x4407, 0x04, 0, 0}, {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) {0x3824, 0x04, 0, 0}, {0x5001, 0x83, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) static const struct reg_value ov5640_setting_1080P_1920_1080[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) {0x3c07, 0x08, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {0x3814, 0x11, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) {0x3810, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) {0x3c07, 0x07, 0, 0}, {0x3c08, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {0x3800, 0x01, 0, 0}, {0x3801, 0x50, 0, 0}, {0x3802, 0x01, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {0x3803, 0xb2, 0, 0}, {0x3804, 0x08, 0, 0}, {0x3805, 0xef, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) {0x3806, 0x05, 0, 0}, {0x3807, 0xf1, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) {0x3612, 0x2b, 0, 0}, {0x3708, 0x64, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {0x3a02, 0x04, 0, 0}, {0x3a03, 0x60, 0, 0}, {0x3a08, 0x01, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {0x3a09, 0x50, 0, 0}, {0x3a0a, 0x01, 0, 0}, {0x3a0b, 0x18, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {0x3a0e, 0x03, 0, 0}, {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x04, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {0x3a15, 0x60, 0, 0}, {0x4407, 0x04, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {0x460b, 0x37, 0, 0}, {0x460c, 0x20, 0, 0}, {0x3824, 0x04, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {0x4005, 0x1a, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static const struct reg_value ov5640_setting_QSXGA_2592_1944[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {0x3c07, 0x08, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {0x3c09, 0x1c, 0, 0}, {0x3c0a, 0x9c, 0, 0}, {0x3c0b, 0x40, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {0x3814, 0x11, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {0x3815, 0x11, 0, 0}, {0x3800, 0x00, 0, 0}, {0x3801, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {0x3802, 0x00, 0, 0}, {0x3803, 0x00, 0, 0}, {0x3804, 0x0a, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) {0x3805, 0x3f, 0, 0}, {0x3806, 0x07, 0, 0}, {0x3807, 0x9f, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {0x3810, 0x00, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {0x3811, 0x10, 0, 0}, {0x3812, 0x00, 0, 0}, {0x3813, 0x04, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {0x3618, 0x04, 0, 0}, {0x3612, 0x29, 0, 0}, {0x3708, 0x21, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {0x3709, 0x12, 0, 0}, {0x370c, 0x00, 0, 0}, {0x3a02, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {0x3a03, 0xd8, 0, 0}, {0x3a08, 0x01, 0, 0}, {0x3a09, 0x27, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) {0x3a0a, 0x00, 0, 0}, {0x3a0b, 0xf6, 0, 0}, {0x3a0e, 0x03, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {0x3a0d, 0x04, 0, 0}, {0x3a14, 0x03, 0, 0}, {0x3a15, 0xd8, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {0x4001, 0x02, 0, 0}, {0x4004, 0x06, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) {0x4407, 0x04, 0, 0}, {0x460b, 0x35, 0, 0}, {0x460c, 0x22, 0, 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {0x3824, 0x02, 0, 0}, {0x5001, 0x83, 0, 70},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* power-on sensor init reg table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) static const struct ov5640_mode_info ov5640_mode_init_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 0, SUBSAMPLING, 640, 1896, 480, 984,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ov5640_init_setting_30fps_VGA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) ARRAY_SIZE(ov5640_init_setting_30fps_VGA),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) OV5640_30_FPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static const struct ov5640_mode_info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ov5640_mode_data[OV5640_NUM_MODES] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {OV5640_MODE_QCIF_176_144, SUBSAMPLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 176, 1896, 144, 984,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) ov5640_setting_QCIF_176_144,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ARRAY_SIZE(ov5640_setting_QCIF_176_144),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) OV5640_30_FPS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {OV5640_MODE_QVGA_320_240, SUBSAMPLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 320, 1896, 240, 984,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ov5640_setting_QVGA_320_240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ARRAY_SIZE(ov5640_setting_QVGA_320_240),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) OV5640_30_FPS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {OV5640_MODE_VGA_640_480, SUBSAMPLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 640, 1896, 480, 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ov5640_setting_VGA_640_480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ARRAY_SIZE(ov5640_setting_VGA_640_480),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) OV5640_60_FPS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {OV5640_MODE_NTSC_720_480, SUBSAMPLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 720, 1896, 480, 984,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ov5640_setting_NTSC_720_480,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ARRAY_SIZE(ov5640_setting_NTSC_720_480),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) OV5640_30_FPS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {OV5640_MODE_PAL_720_576, SUBSAMPLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 720, 1896, 576, 984,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) ov5640_setting_PAL_720_576,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ARRAY_SIZE(ov5640_setting_PAL_720_576),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) OV5640_30_FPS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {OV5640_MODE_XGA_1024_768, SUBSAMPLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 1024, 1896, 768, 1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ov5640_setting_XGA_1024_768,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ARRAY_SIZE(ov5640_setting_XGA_1024_768),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) OV5640_30_FPS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {OV5640_MODE_720P_1280_720, SUBSAMPLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 1280, 1892, 720, 740,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) ov5640_setting_720P_1280_720,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) ARRAY_SIZE(ov5640_setting_720P_1280_720),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) OV5640_30_FPS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {OV5640_MODE_1080P_1920_1080, SCALING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 1920, 2500, 1080, 1120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) ov5640_setting_1080P_1920_1080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) ARRAY_SIZE(ov5640_setting_1080P_1920_1080),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) OV5640_30_FPS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {OV5640_MODE_QSXGA_2592_1944, SCALING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 2592, 2844, 1944, 1968,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) ov5640_setting_QSXGA_2592_1944,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ARRAY_SIZE(ov5640_setting_QSXGA_2592_1944),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) OV5640_15_FPS},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int ov5640_init_slave_id(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct i2c_client *client = sensor->i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) u8 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (client->addr == OV5640_DEFAULT_SLAVE_ID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) buf[0] = OV5640_REG_SLAVE_ID >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) buf[1] = OV5640_REG_SLAVE_ID & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) buf[2] = client->addr << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) msg.addr = OV5640_DEFAULT_SLAVE_ID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) msg.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_err(&client->dev, "%s: failed with %d\n", __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) static int ov5640_write_reg(struct ov5640_dev *sensor, u16 reg, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct i2c_client *client = sensor->i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct i2c_msg msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) u8 buf[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) buf[2] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) msg.addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) msg.flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) msg.buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) msg.len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ret = i2c_transfer(client->adapter, &msg, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dev_err(&client->dev, "%s: error: reg=%x, val=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) __func__, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static int ov5640_read_reg(struct ov5640_dev *sensor, u16 reg, u8 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct i2c_client *client = sensor->i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct i2c_msg msg[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) u8 buf[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) msg[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) msg[0].flags = client->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) msg[0].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) msg[0].len = sizeof(buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) msg[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) msg[1].flags = client->flags | I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) msg[1].buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) msg[1].len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ret = i2c_transfer(client->adapter, msg, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dev_err(&client->dev, "%s: error: reg=%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) __func__, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) *val = buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) static int ov5640_read_reg16(struct ov5640_dev *sensor, u16 reg, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) u8 hi, lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ret = ov5640_read_reg(sensor, reg, &hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret = ov5640_read_reg(sensor, reg + 1, &lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) *val = ((u16)hi << 8) | (u16)lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static int ov5640_write_reg16(struct ov5640_dev *sensor, u16 reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) ret = ov5640_write_reg(sensor, reg, val >> 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return ov5640_write_reg(sensor, reg + 1, val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int ov5640_mod_reg(struct ov5640_dev *sensor, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) u8 mask, u8 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) u8 readval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) ret = ov5640_read_reg(sensor, reg, &readval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) readval &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) val &= mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) val |= readval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) return ov5640_write_reg(sensor, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) * After trying the various combinations, reading various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * documentations spread around the net, and from the various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) * feedback, the clock tree is probably as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * +--------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * | Ext. Clock |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * +-+------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * | +----------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * +->| PLL1 | - reg 0x3036, for the multiplier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) * +-+--------+ - reg 0x3037, bits 0-3 for the pre-divider
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * | +--------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * +->| System Clock | - reg 0x3035, bits 4-7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * +-+------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * | +--------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) * +->| MIPI Divider | - reg 0x3035, bits 0-3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * | +-+------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * | +----------------> MIPI SCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * | + +-----+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * | +->| / 2 |-------> MIPI BIT CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) * | +-----+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) * | +--------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) * +->| PLL Root Div | - reg 0x3037, bit 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * +-+------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * | +---------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * +->| Bit Div | - reg 0x3034, bits 0-3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * +-+-------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * | +-------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * +->| SCLK Div | - reg 0x3108, bits 0-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) * | +-+-----------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * | +---------------> SCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * | +-------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * +->| SCLK 2X Div | - reg 0x3108, bits 2-3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) * | +-+-----------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * | +---------------> SCLK 2X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * | +-------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * +->| PCLK Div | - reg 0x3108, bits 4-5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * ++------------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * + +-----------+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * +->| P_DIV | - reg 0x3035, bits 0-3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * +-----+-----+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * +------------> PCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * This is deviating from the datasheet at least for the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * 0x3108, since it's said here that the PCLK would be clocked from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * the PLL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * There seems to be also (unverified) constraints:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * - the PLL pre-divider output rate should be in the 4-27MHz range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * - the PLL multiplier output rate should be in the 500-1000MHz range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * - PCLK >= SCLK * 2 in YUV, >= SCLK in Raw or JPEG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * In the two latter cases, these constraints are met since our
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * factors are hardcoded. If we were to change that, we would need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * take this into account. The only varying parts are the PLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * multiplier and the system clock divider, which are shared between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * all these clocks so won't cause any issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * This is supposed to be ranging from 1 to 8, but the value is always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * set to 3 in the vendor kernels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define OV5640_PLL_PREDIV 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define OV5640_PLL_MULT_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define OV5640_PLL_MULT_MAX 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) * This is supposed to be ranging from 1 to 16, but the value is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * always set to either 1 or 2 in the vendor kernels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define OV5640_SYSDIV_MIN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define OV5640_SYSDIV_MAX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * Hardcode these values for scaler and non-scaler modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * FIXME: to be re-calcualted for 1 data lanes setups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define OV5640_MIPI_DIV_PCLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define OV5640_MIPI_DIV_SCLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * This is supposed to be ranging from 1 to 2, but the value is always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * set to 2 in the vendor kernels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define OV5640_PLL_ROOT_DIV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define OV5640_PLL_CTRL3_PLL_ROOT_DIV_2 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * We only supports 8-bit formats at the moment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define OV5640_BIT_DIV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define OV5640_PLL_CTRL0_MIPI_MODE_8BIT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) * This is supposed to be ranging from 1 to 8, but the value is always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) * set to 2 in the vendor kernels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define OV5640_SCLK_ROOT_DIV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) * This is hardcoded so that the consistency is maintained between SCLK and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * SCLK 2x.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define OV5640_SCLK2X_ROOT_DIV (OV5640_SCLK_ROOT_DIV / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * This is supposed to be ranging from 1 to 8, but the value is always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * set to 1 in the vendor kernels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define OV5640_PCLK_ROOT_DIV 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define OV5640_PLL_SYS_ROOT_DIVIDER_BYPASS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) static unsigned long ov5640_compute_sys_clk(struct ov5640_dev *sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) u8 pll_prediv, u8 pll_mult,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) u8 sysdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) unsigned long sysclk = sensor->xclk_freq / pll_prediv * pll_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* PLL1 output cannot exceed 1GHz. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (sysclk / 1000000 > 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return sysclk / sysdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static unsigned long ov5640_calc_sys_clk(struct ov5640_dev *sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) u8 *pll_prediv, u8 *pll_mult,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u8 *sysdiv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) unsigned long best = ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) u8 best_sysdiv = 1, best_mult = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u8 _sysdiv, _pll_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) for (_sysdiv = OV5640_SYSDIV_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) _sysdiv <= OV5640_SYSDIV_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) _sysdiv++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) for (_pll_mult = OV5640_PLL_MULT_MIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) _pll_mult <= OV5640_PLL_MULT_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) _pll_mult++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) unsigned long _rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * The PLL multiplier cannot be odd if above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * 127.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (_pll_mult > 127 && (_pll_mult % 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) _rate = ov5640_compute_sys_clk(sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) OV5640_PLL_PREDIV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) _pll_mult, _sysdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) * We have reached the maximum allowed PLL1 output,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) * increase sysdiv.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (!_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) * Prefer rates above the expected clock rate than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) * below, even if that means being less precise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (_rate < rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (abs(rate - _rate) < abs(rate - best)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) best = _rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) best_sysdiv = _sysdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) best_mult = _pll_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (_rate == rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) *sysdiv = best_sysdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) *pll_prediv = OV5640_PLL_PREDIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) *pll_mult = best_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return best;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * ov5640_set_mipi_pclk() - Calculate the clock tree configuration values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * for the MIPI CSI-2 output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * @rate: The requested bandwidth per lane in bytes per second.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * 'Bandwidth Per Lane' is calculated as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) * bpl = HTOT * VTOT * FPS * bpp / num_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) * This function use the requested bandwidth to calculate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * - sample_rate = bpl / (bpp / num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * = bpl / (PLL_RDIV * BIT_DIV * PCLK_DIV * MIPI_DIV / num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * - mipi_sclk = bpl / MIPI_DIV / 2; ( / 2 is for CSI-2 DDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * with these fixed parameters:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * PLL_RDIV = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * BIT_DIVIDER = 2; (MIPI_BIT_MODE == 8 ? 2 : 2,5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * PCLK_DIV = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * The MIPI clock generation differs for modes that use the scaler and modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * that do not. In case the scaler is in use, the MIPI_SCLK generates the MIPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * BIT CLk, and thus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) * - mipi_sclk = bpl / MIPI_DIV / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) * MIPI_DIV = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * For modes that do not go through the scaler, the MIPI BIT CLOCK is generated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * from the pixel clock, and thus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) * - sample_rate = bpl / (bpp / num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * = bpl / (2 * 2 * 1 * MIPI_DIV / num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * = bpl / (4 * MIPI_DIV / num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * - MIPI_DIV = bpp / (4 * num_lanes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * FIXME: this have been tested with 16bpp and 2 lanes setup only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * MIPI_DIV is fixed to value 2, but it -might- be changed according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * above formula for setups with 1 lane or image formats with different bpp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * FIXME: this deviates from the sensor manual documentation which is quite
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) * thin on the MIPI clock tree generation part.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) static int ov5640_set_mipi_pclk(struct ov5640_dev *sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) const struct ov5640_mode_info *mode = sensor->current_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) u8 prediv, mult, sysdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u8 mipi_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) * 1280x720 is reported to use 'SUBSAMPLING' only,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * but according to the sensor manual it goes through the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) * scaler before subsampling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (mode->dn_mode == SCALING ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) (mode->id == OV5640_MODE_720P_1280_720))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) mipi_div = OV5640_MIPI_DIV_SCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) mipi_div = OV5640_MIPI_DIV_PCLK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ov5640_calc_sys_clk(sensor, rate, &prediv, &mult, &sysdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) 0x0f, OV5640_PLL_CTRL0_MIPI_MODE_8BIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) 0xff, sysdiv << 4 | mipi_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL2, 0xff, mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) 0x1f, OV5640_PLL_CTRL3_PLL_ROOT_DIV_2 | prediv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return ov5640_mod_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) 0x30, OV5640_PLL_SYS_ROOT_DIVIDER_BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) static unsigned long ov5640_calc_pclk(struct ov5640_dev *sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) unsigned long rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) u8 *pll_prediv, u8 *pll_mult, u8 *sysdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) u8 *pll_rdiv, u8 *bit_div, u8 *pclk_div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) unsigned long _rate = rate * OV5640_PLL_ROOT_DIV * OV5640_BIT_DIV *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) OV5640_PCLK_ROOT_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) _rate = ov5640_calc_sys_clk(sensor, _rate, pll_prediv, pll_mult,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) sysdiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) *pll_rdiv = OV5640_PLL_ROOT_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) *bit_div = OV5640_BIT_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) *pclk_div = OV5640_PCLK_ROOT_DIV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return _rate / *pll_rdiv / *bit_div / *pclk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static int ov5640_set_dvp_pclk(struct ov5640_dev *sensor, unsigned long rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) u8 prediv, mult, sysdiv, pll_rdiv, bit_div, pclk_div;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ov5640_calc_pclk(sensor, rate, &prediv, &mult, &sysdiv, &pll_rdiv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) &bit_div, &pclk_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (bit_div == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) bit_div = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) 0x0f, bit_div);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) * We need to set sysdiv according to the clock, and to clear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * the MIPI divider.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) 0xff, sysdiv << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) 0xff, mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) ret = ov5640_mod_reg(sensor, OV5640_REG_SC_PLL_CTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) 0x1f, prediv | ((pll_rdiv - 1) << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return ov5640_mod_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER, 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) (ilog2(pclk_div) << 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* set JPEG framing sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) static int ov5640_set_jpeg_timings(struct ov5640_dev *sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) const struct ov5640_mode_info *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * compression mode 3 timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) * Data is transmitted with programmable width (VFIFO_HSIZE).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) * No padding done. Last line may have less data. Varying
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) * number of lines per frame, depending on amount of data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) ret = ov5640_mod_reg(sensor, OV5640_REG_JPG_MODE_SELECT, 0x7, 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ret = ov5640_write_reg16(sensor, OV5640_REG_VFIFO_HSIZE, mode->hact);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return ov5640_write_reg16(sensor, OV5640_REG_VFIFO_VSIZE, mode->vact);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /* download ov5640 settings to sensor through i2c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static int ov5640_set_timings(struct ov5640_dev *sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) const struct ov5640_mode_info *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) if (sensor->fmt.code == MEDIA_BUS_FMT_JPEG_1X8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) ret = ov5640_set_jpeg_timings(sensor, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) ret = ov5640_write_reg16(sensor, OV5640_REG_TIMING_DVPHO, mode->hact);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) ret = ov5640_write_reg16(sensor, OV5640_REG_TIMING_DVPVO, mode->vact);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) ret = ov5640_write_reg16(sensor, OV5640_REG_TIMING_HTS, mode->htot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return ov5640_write_reg16(sensor, OV5640_REG_TIMING_VTS, mode->vtot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) static int ov5640_load_regs(struct ov5640_dev *sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) const struct ov5640_mode_info *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) const struct reg_value *regs = mode->reg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) u32 delay_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) u16 reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) u8 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) for (i = 0; i < mode->reg_data_size; ++i, ++regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) delay_ms = regs->delay_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) reg_addr = regs->reg_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) val = regs->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) mask = regs->mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) /* remain in power down mode for DVP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (regs->reg_addr == OV5640_REG_SYS_CTRL0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) val == OV5640_REG_SYS_CTRL0_SW_PWUP &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) sensor->ep.bus_type != V4L2_MBUS_CSI2_DPHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) ret = ov5640_mod_reg(sensor, reg_addr, mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) ret = ov5640_write_reg(sensor, reg_addr, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if (delay_ms)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) usleep_range(1000 * delay_ms, 1000 * delay_ms + 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return ov5640_set_timings(sensor, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static int ov5640_set_autoexposure(struct ov5640_dev *sensor, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) return ov5640_mod_reg(sensor, OV5640_REG_AEC_PK_MANUAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) BIT(0), on ? 0 : BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) /* read exposure, in number of line periods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static int ov5640_get_exposure(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) int exp, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) u8 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) ret = ov5640_read_reg(sensor, OV5640_REG_AEC_PK_EXPOSURE_HI, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) exp = ((int)temp & 0x0f) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ret = ov5640_read_reg(sensor, OV5640_REG_AEC_PK_EXPOSURE_MED, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) exp |= ((int)temp << 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) ret = ov5640_read_reg(sensor, OV5640_REG_AEC_PK_EXPOSURE_LO, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) exp |= (int)temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return exp >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* write exposure, given number of line periods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static int ov5640_set_exposure(struct ov5640_dev *sensor, u32 exposure)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) exposure <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) ret = ov5640_write_reg(sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) OV5640_REG_AEC_PK_EXPOSURE_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) exposure & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) ret = ov5640_write_reg(sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) OV5640_REG_AEC_PK_EXPOSURE_MED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) (exposure >> 8) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) return ov5640_write_reg(sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) OV5640_REG_AEC_PK_EXPOSURE_HI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) (exposure >> 16) & 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static int ov5640_get_gain(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) u16 gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ret = ov5640_read_reg16(sensor, OV5640_REG_AEC_PK_REAL_GAIN, &gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) return gain & 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) static int ov5640_set_gain(struct ov5640_dev *sensor, int gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return ov5640_write_reg16(sensor, OV5640_REG_AEC_PK_REAL_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) (u16)gain & 0x3ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) static int ov5640_set_autogain(struct ov5640_dev *sensor, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) return ov5640_mod_reg(sensor, OV5640_REG_AEC_PK_MANUAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) BIT(1), on ? 0 : BIT(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) static int ov5640_set_stream_dvp(struct ov5640_dev *sensor, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) return ov5640_write_reg(sensor, OV5640_REG_SYS_CTRL0, on ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) OV5640_REG_SYS_CTRL0_SW_PWUP :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) OV5640_REG_SYS_CTRL0_SW_PWDN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) static int ov5640_set_stream_mipi(struct ov5640_dev *sensor, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) * Enable/disable the MIPI interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) * 0x300e = on ? 0x45 : 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) * FIXME: the sensor manual (version 2.03) reports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) * [7:5] = 000 : 1 data lane mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) * [7:5] = 001 : 2 data lanes mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * But this settings do not work, while the following ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * have been validated for 2 data lanes mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) * [7:5] = 010 : 2 data lanes mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) * [4] = 0 : Power up MIPI HS Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * [3] = 0 : Power up MIPI LS Rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) * [2] = 1/0 : MIPI interface enable/disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * [1:0] = 01/00: FIXME: 'debug'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ret = ov5640_write_reg(sensor, OV5640_REG_IO_MIPI_CTRL00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) on ? 0x45 : 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) return ov5640_write_reg(sensor, OV5640_REG_FRAME_CTRL01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) on ? 0x00 : 0x0f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) static int ov5640_get_sysclk(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* calculate sysclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) u32 xvclk = sensor->xclk_freq / 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) u32 multiplier, prediv, VCO, sysdiv, pll_rdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) u32 sclk_rdiv_map[] = {1, 2, 4, 8};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) u32 bit_div2x = 1, sclk_rdiv, sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) u8 temp1, temp2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) ret = ov5640_read_reg(sensor, OV5640_REG_SC_PLL_CTRL0, &temp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) temp2 = temp1 & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (temp2 == 8 || temp2 == 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) bit_div2x = temp2 / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ret = ov5640_read_reg(sensor, OV5640_REG_SC_PLL_CTRL1, &temp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) sysdiv = temp1 >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (sysdiv == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) sysdiv = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) ret = ov5640_read_reg(sensor, OV5640_REG_SC_PLL_CTRL2, &temp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) multiplier = temp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) ret = ov5640_read_reg(sensor, OV5640_REG_SC_PLL_CTRL3, &temp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) prediv = temp1 & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) pll_rdiv = ((temp1 >> 4) & 0x01) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ret = ov5640_read_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER, &temp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) temp2 = temp1 & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) sclk_rdiv = sclk_rdiv_map[temp2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (!prediv || !sysdiv || !pll_rdiv || !bit_div2x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) VCO = xvclk * multiplier / prediv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) sysclk = VCO / sysdiv / pll_rdiv * 2 / bit_div2x / sclk_rdiv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) return sysclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) static int ov5640_set_night_mode(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /* read HTS from register settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) u8 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) ret = ov5640_read_reg(sensor, OV5640_REG_AEC_CTRL00, &mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) mode &= 0xfb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) return ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL00, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static int ov5640_get_hts(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /* read HTS from register settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) u16 hts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) ret = ov5640_read_reg16(sensor, OV5640_REG_TIMING_HTS, &hts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) return hts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) static int ov5640_get_vts(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) u16 vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) ret = ov5640_read_reg16(sensor, OV5640_REG_TIMING_VTS, &vts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) return vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) static int ov5640_set_vts(struct ov5640_dev *sensor, int vts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) return ov5640_write_reg16(sensor, OV5640_REG_TIMING_VTS, vts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) static int ov5640_get_light_freq(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /* get banding filter value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) int ret, light_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) u8 temp, temp1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ret = ov5640_read_reg(sensor, OV5640_REG_HZ5060_CTRL01, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (temp & 0x80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /* manual */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) ret = ov5640_read_reg(sensor, OV5640_REG_HZ5060_CTRL00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) &temp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (temp1 & 0x04) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) /* 50Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) light_freq = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) /* 60Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) light_freq = 60;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) /* auto */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) ret = ov5640_read_reg(sensor, OV5640_REG_SIGMADELTA_CTRL0C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) &temp1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (temp1 & 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /* 50Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) light_freq = 50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) /* 60Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return light_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static int ov5640_set_bandingfilter(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) u32 band_step60, max_band60, band_step50, max_band50, prev_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /* read preview PCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) ret = ov5640_get_sysclk(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) sensor->prev_sysclk = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) /* read preview HTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) ret = ov5640_get_hts(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) sensor->prev_hts = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) /* read preview VTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) ret = ov5640_get_vts(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) prev_vts = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /* calculate banding filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) /* 60Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) band_step60 = sensor->prev_sysclk * 100 / sensor->prev_hts * 100 / 120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) ret = ov5640_write_reg16(sensor, OV5640_REG_AEC_B60_STEP, band_step60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (!band_step60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) max_band60 = (int)((prev_vts - 4) / band_step60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL0D, max_band60);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) /* 50Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) band_step50 = sensor->prev_sysclk * 100 / sensor->prev_hts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) ret = ov5640_write_reg16(sensor, OV5640_REG_AEC_B50_STEP, band_step50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (!band_step50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) max_band50 = (int)((prev_vts - 4) / band_step50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL0E, max_band50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static int ov5640_set_ae_target(struct ov5640_dev *sensor, int target)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* stable in high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) u32 fast_high, fast_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) sensor->ae_low = target * 23 / 25; /* 0.92 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) sensor->ae_high = target * 27 / 25; /* 1.08 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) fast_high = sensor->ae_high << 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (fast_high > 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) fast_high = 255;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) fast_low = sensor->ae_low >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL0F, sensor->ae_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL10, sensor->ae_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL1B, sensor->ae_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL1E, sensor->ae_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ret = ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL11, fast_high);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) return ov5640_write_reg(sensor, OV5640_REG_AEC_CTRL1F, fast_low);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) static int ov5640_get_binning(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) u8 temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) ret = ov5640_read_reg(sensor, OV5640_REG_TIMING_TC_REG21, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) return temp & BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) static int ov5640_set_binning(struct ov5640_dev *sensor, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) * TIMING TC REG21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) * - [0]: Horizontal binning enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) ret = ov5640_mod_reg(sensor, OV5640_REG_TIMING_TC_REG21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) BIT(0), enable ? BIT(0) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) * TIMING TC REG20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) * - [0]: Undocumented, but hardcoded init sequences
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) * are always setting REG21/REG20 bit 0 to same value...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) return ov5640_mod_reg(sensor, OV5640_REG_TIMING_TC_REG20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) BIT(0), enable ? BIT(0) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) static int ov5640_set_virtual_channel(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) struct i2c_client *client = sensor->i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) u8 temp, channel = virtual_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) if (channel > 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) dev_err(&client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) "%s: wrong virtual_channel parameter, expected (0..3), got %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) __func__, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) ret = ov5640_read_reg(sensor, OV5640_REG_DEBUG_MODE, &temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) temp &= ~(3 << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) temp |= (channel << 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) return ov5640_write_reg(sensor, OV5640_REG_DEBUG_MODE, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) static const struct ov5640_mode_info *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) ov5640_find_mode(struct ov5640_dev *sensor, enum ov5640_frame_rate fr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) int width, int height, bool nearest)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) const struct ov5640_mode_info *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) mode = v4l2_find_nearest_size(ov5640_mode_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) ARRAY_SIZE(ov5640_mode_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) hact, vact,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) width, height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (!mode ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) (!nearest && (mode->hact != width || mode->vact != height)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) /* Check to see if the current mode exceeds the max frame rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) if (ov5640_framerates[fr] > ov5640_framerates[mode->max_fps])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) static u64 ov5640_calc_pixel_rate(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) u64 rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) rate = sensor->current_mode->vtot * sensor->current_mode->htot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) rate *= ov5640_framerates[sensor->current_fr];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) return rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) * sensor changes between scaling and subsampling, go through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) * exposure calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) static int ov5640_set_mode_exposure_calc(struct ov5640_dev *sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) const struct ov5640_mode_info *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) u32 prev_shutter, prev_gain16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) u32 cap_shutter, cap_gain16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) u32 cap_sysclk, cap_hts, cap_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) u32 light_freq, cap_bandfilt, cap_maxband;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) u32 cap_gain16_shutter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) u8 average;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) if (!mode->reg_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /* read preview shutter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) ret = ov5640_get_exposure(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) prev_shutter = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) ret = ov5640_get_binning(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) if (ret && mode->id != OV5640_MODE_720P_1280_720 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) mode->id != OV5640_MODE_1080P_1920_1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) prev_shutter *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) /* read preview gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) ret = ov5640_get_gain(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) prev_gain16 = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) /* get average */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) ret = ov5640_read_reg(sensor, OV5640_REG_AVG_READOUT, &average);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) /* turn off night mode for capture */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) ret = ov5640_set_night_mode(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) /* Write capture setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) ret = ov5640_load_regs(sensor, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) /* read capture VTS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) ret = ov5640_get_vts(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) cap_vts = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) ret = ov5640_get_hts(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) cap_hts = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) ret = ov5640_get_sysclk(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) cap_sysclk = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) /* calculate capture banding filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) ret = ov5640_get_light_freq(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) light_freq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) if (light_freq == 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) /* 60Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) cap_bandfilt = cap_sysclk * 100 / cap_hts * 100 / 120;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /* 50Hz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) cap_bandfilt = cap_sysclk * 100 / cap_hts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (!sensor->prev_sysclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) ret = ov5640_get_sysclk(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) if (ret == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) sensor->prev_sysclk = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) if (!cap_bandfilt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) cap_maxband = (int)((cap_vts - 4) / cap_bandfilt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) /* calculate capture shutter/gain16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (average > sensor->ae_low && average < sensor->ae_high) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* in stable range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) cap_gain16_shutter =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) prev_gain16 * prev_shutter *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) cap_sysclk / sensor->prev_sysclk *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) sensor->prev_hts / cap_hts *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) sensor->ae_target / average;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) cap_gain16_shutter =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) prev_gain16 * prev_shutter *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) cap_sysclk / sensor->prev_sysclk *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) sensor->prev_hts / cap_hts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) /* gain to shutter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) if (cap_gain16_shutter < (cap_bandfilt * 16)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) /* shutter < 1/100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) cap_shutter = cap_gain16_shutter / 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) if (cap_shutter < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) cap_shutter = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) cap_gain16 = cap_gain16_shutter / cap_shutter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) if (cap_gain16 < 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) cap_gain16 = 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (cap_gain16_shutter > (cap_bandfilt * cap_maxband * 16)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) /* exposure reach max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) cap_shutter = cap_bandfilt * cap_maxband;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) if (!cap_shutter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) cap_gain16 = cap_gain16_shutter / cap_shutter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) /* 1/100 < (cap_shutter = n/100) =< max */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) cap_shutter =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) ((int)(cap_gain16_shutter / 16 / cap_bandfilt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) * cap_bandfilt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) if (!cap_shutter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) cap_gain16 = cap_gain16_shutter / cap_shutter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /* set capture gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) ret = ov5640_set_gain(sensor, cap_gain16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) /* write capture shutter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) if (cap_shutter > (cap_vts - 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) cap_vts = cap_shutter + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) ret = ov5640_set_vts(sensor, cap_vts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) /* set exposure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) return ov5640_set_exposure(sensor, cap_shutter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) * if sensor changes inside scaling or subsampling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) * change mode directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static int ov5640_set_mode_direct(struct ov5640_dev *sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) const struct ov5640_mode_info *mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if (!mode->reg_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) /* Write capture setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) return ov5640_load_regs(sensor, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) static int ov5640_set_mode(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) const struct ov5640_mode_info *mode = sensor->current_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) const struct ov5640_mode_info *orig_mode = sensor->last_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) enum ov5640_downsize_mode dn_mode, orig_dn_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) bool auto_gain = sensor->ctrls.auto_gain->val == 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) bool auto_exp = sensor->ctrls.auto_exp->val == V4L2_EXPOSURE_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) dn_mode = mode->dn_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) orig_dn_mode = orig_mode->dn_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) /* auto gain and exposure must be turned off when changing modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) if (auto_gain) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) ret = ov5640_set_autogain(sensor, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (auto_exp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) ret = ov5640_set_autoexposure(sensor, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) goto restore_auto_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) * All the formats we support have 16 bits per pixel, seems to require
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) * the same rate than YUV, so we can just use 16 bpp all the time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) rate = ov5640_calc_pixel_rate(sensor) * 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (sensor->ep.bus_type == V4L2_MBUS_CSI2_DPHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) rate = rate / sensor->ep.bus.mipi_csi2.num_data_lanes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) ret = ov5640_set_mipi_pclk(sensor, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) rate = rate / sensor->ep.bus.parallel.bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) ret = ov5640_set_dvp_pclk(sensor, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) if ((dn_mode == SUBSAMPLING && orig_dn_mode == SCALING) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) (dn_mode == SCALING && orig_dn_mode == SUBSAMPLING)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) * change between subsampling and scaling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) * go through exposure calculation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) ret = ov5640_set_mode_exposure_calc(sensor, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) * change inside subsampling or scaling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) * download firmware directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) ret = ov5640_set_mode_direct(sensor, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) goto restore_auto_exp_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) /* restore auto gain and exposure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (auto_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) ov5640_set_autogain(sensor, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) if (auto_exp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) ov5640_set_autoexposure(sensor, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) ret = ov5640_set_binning(sensor, dn_mode != SCALING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) ret = ov5640_set_ae_target(sensor, sensor->ae_target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) ret = ov5640_get_light_freq(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) ret = ov5640_set_bandingfilter(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) ret = ov5640_set_virtual_channel(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) sensor->pending_mode_change = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) sensor->last_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) restore_auto_exp_gain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) if (auto_exp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) ov5640_set_autoexposure(sensor, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) restore_auto_gain:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (auto_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) ov5640_set_autogain(sensor, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) static int ov5640_set_framefmt(struct ov5640_dev *sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) struct v4l2_mbus_framefmt *format);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) /* restore the last set video mode after chip power-on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) static int ov5640_restore_mode(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) /* first load the initial register values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) ret = ov5640_load_regs(sensor, &ov5640_mode_init_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) sensor->last_mode = &ov5640_mode_init_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) ret = ov5640_mod_reg(sensor, OV5640_REG_SYS_ROOT_DIVIDER, 0x3f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) (ilog2(OV5640_SCLK2X_ROOT_DIV) << 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) ilog2(OV5640_SCLK_ROOT_DIV));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) /* now restore the last capture mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) ret = ov5640_set_mode(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) return ov5640_set_framefmt(sensor, &sensor->fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) static void ov5640_power(struct ov5640_dev *sensor, bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) gpiod_set_value_cansleep(sensor->pwdn_gpio, enable ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) static void ov5640_reset(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if (!sensor->reset_gpio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) gpiod_set_value_cansleep(sensor->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) /* camera power cycle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) ov5640_power(sensor, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) ov5640_power(sensor, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) usleep_range(5000, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) gpiod_set_value_cansleep(sensor->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) gpiod_set_value_cansleep(sensor->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) usleep_range(20000, 25000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) static int ov5640_set_power_on(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) struct i2c_client *client = sensor->i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) ret = clk_prepare_enable(sensor->xclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) dev_err(&client->dev, "%s: failed to enable clock\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) ret = regulator_bulk_enable(OV5640_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) sensor->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) dev_err(&client->dev, "%s: failed to enable regulators\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) goto xclk_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) ov5640_reset(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) ov5640_power(sensor, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) ret = ov5640_init_slave_id(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) goto power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) ov5640_power(sensor, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) regulator_bulk_disable(OV5640_NUM_SUPPLIES, sensor->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) xclk_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) clk_disable_unprepare(sensor->xclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) static void ov5640_set_power_off(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) ov5640_power(sensor, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) regulator_bulk_disable(OV5640_NUM_SUPPLIES, sensor->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) clk_disable_unprepare(sensor->xclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) static int ov5640_set_power_mipi(struct ov5640_dev *sensor, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) if (!on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) /* Reset MIPI bus settings to their default values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) ov5640_write_reg(sensor, OV5640_REG_IO_MIPI_CTRL00, 0x58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) ov5640_write_reg(sensor, OV5640_REG_MIPI_CTRL00, 0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) * Power up MIPI HS Tx and LS Rx; 2 data lanes mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) * 0x300e = 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) * [7:5] = 010 : 2 data lanes mode (see FIXME note in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) * "ov5640_set_stream_mipi()")
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) * [4] = 0 : Power up MIPI HS Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) * [3] = 0 : Power up MIPI LS Rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) * [2] = 0 : MIPI interface disabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) ret = ov5640_write_reg(sensor, OV5640_REG_IO_MIPI_CTRL00, 0x40);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) * Gate clock and set LP11 in 'no packets mode' (idle)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) * 0x4800 = 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) * [5] = 1 : Gate clock when 'no packets'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) * [2] = 1 : MIPI bus in LP11 when 'no packets'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) ret = ov5640_write_reg(sensor, OV5640_REG_MIPI_CTRL00, 0x24);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) * Set data lanes and clock in LP11 when 'sleeping'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) * 0x3019 = 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) * [6] = 1 : MIPI data lane 2 in LP11 when 'sleeping'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) * [5] = 1 : MIPI data lane 1 in LP11 when 'sleeping'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) * [4] = 1 : MIPI clock lane in LP11 when 'sleeping'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) ret = ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT00, 0x70);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) /* Give lanes some time to coax into LP11 state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) static int ov5640_set_power_dvp(struct ov5640_dev *sensor, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) unsigned int flags = sensor->ep.bus.parallel.flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) bool bt656 = sensor->ep.bus_type == V4L2_MBUS_BT656;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) u8 polarities = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) if (!on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) /* Reset settings to their default values. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) ov5640_write_reg(sensor, OV5640_REG_CCIR656_CTRL00, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) ov5640_write_reg(sensor, OV5640_REG_IO_MIPI_CTRL00, 0x58);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) ov5640_write_reg(sensor, OV5640_REG_POLARITY_CTRL00, 0x20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT_ENABLE01, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT_ENABLE02, 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) * Note about parallel port configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) * When configured in parallel mode, the OV5640 will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) * output 10 bits data on DVP data lines [9:0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) * If only 8 bits data are wanted, the 8 bits data lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) * of the camera interface must be physically connected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) * on the DVP data lines [9:2].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) * Control lines polarity can be configured through
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) * devicetree endpoint control lines properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) * If no endpoint control lines properties are set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) * polarity will be as below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) * - VSYNC: active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) * - HREF: active low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) * - PCLK: active low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) * VSYNC & HREF are not configured if BT656 bus mode is selected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) * BT656 embedded synchronization configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) * CCIR656 CTRL00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) * - [7]: SYNC code selection (0: auto generate sync code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) * 1: sync code from regs 0x4732-0x4735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) * - [6]: f value in CCIR656 SYNC code when fixed f value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) * - [5]: Fixed f value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) * - [4:3]: Blank toggle data options (00: data=1'h040/1'h200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) * 01: data from regs 0x4736-0x4738, 10: always keep 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) * - [1]: Clip data disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) * - [0]: CCIR656 mode enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) * Default CCIR656 SAV/EAV mode with default codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) * SAV=0xff000080 & EAV=0xff00009d is enabled here with settings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) * - CCIR656 mode enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) * - auto generation of sync codes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) * - blank toggle data 1'h040/1'h200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) * - clip reserved data (0x00 & 0xff changed to 0x01 & 0xfe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) ret = ov5640_write_reg(sensor, OV5640_REG_CCIR656_CTRL00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) bt656 ? 0x01 : 0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) * configure parallel port control lines polarity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) * POLARITY CTRL0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) * - [5]: PCLK polarity (0: active low, 1: active high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) * - [1]: HREF polarity (0: active low, 1: active high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) * - [0]: VSYNC polarity (mismatch here between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) * datasheet and hardware, 0 is active high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) * and 1 is active low...)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) if (!bt656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) if (flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) polarities |= BIT(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) polarities |= BIT(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) if (flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) polarities |= BIT(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) ret = ov5640_write_reg(sensor, OV5640_REG_POLARITY_CTRL00, polarities);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) * powerdown MIPI TX/RX PHY & enable DVP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) * MIPI CONTROL 00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) * [4] = 1 : Power down MIPI HS Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) * [3] = 1 : Power down MIPI LS Rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) * [2] = 0 : DVP enable (MIPI disable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) ret = ov5640_write_reg(sensor, OV5640_REG_IO_MIPI_CTRL00, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) * enable VSYNC/HREF/PCLK DVP control lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) * & D[9:6] DVP data lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) * PAD OUTPUT ENABLE 01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) * - 6: VSYNC output enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) * - 5: HREF output enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) * - 4: PCLK output enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) * - [3:0]: D[9:6] output enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) ret = ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT_ENABLE01,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) bt656 ? 0x1f : 0x7f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) * enable D[5:0] DVP data lines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) * PAD OUTPUT ENABLE 02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) * - [7:2]: D[5:0] output enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) return ov5640_write_reg(sensor, OV5640_REG_PAD_OUTPUT_ENABLE02, 0xfc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) static int ov5640_set_power(struct ov5640_dev *sensor, bool on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) ret = ov5640_set_power_on(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) ret = ov5640_restore_mode(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) goto power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) if (sensor->ep.bus_type == V4L2_MBUS_CSI2_DPHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) ret = ov5640_set_power_mipi(sensor, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) ret = ov5640_set_power_dvp(sensor, on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) goto power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) if (!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) ov5640_set_power_off(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) ov5640_set_power_off(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) /* --------------- Subdev Operations --------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) static int ov5640_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) struct ov5640_dev *sensor = to_ov5640_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) mutex_lock(&sensor->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) * If the power count is modified from 0 to != 0 or from != 0 to 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) * update the power state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) if (sensor->power_count == !on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) ret = ov5640_set_power(sensor, !!on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) /* Update the power count. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) sensor->power_count += on ? 1 : -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) WARN_ON(sensor->power_count < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) mutex_unlock(&sensor->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) if (on && !ret && sensor->power_count == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) /* restore controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) ret = v4l2_ctrl_handler_setup(&sensor->ctrls.handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) static int ov5640_try_frame_interval(struct ov5640_dev *sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) struct v4l2_fract *fi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) u32 width, u32 height)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) const struct ov5640_mode_info *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) enum ov5640_frame_rate rate = OV5640_15_FPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) int minfps, maxfps, best_fps, fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) minfps = ov5640_framerates[OV5640_15_FPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) maxfps = ov5640_framerates[OV5640_60_FPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) if (fi->numerator == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) fi->denominator = maxfps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) fi->numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) rate = OV5640_60_FPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) goto find_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) fps = clamp_val(DIV_ROUND_CLOSEST(fi->denominator, fi->numerator),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) minfps, maxfps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) best_fps = minfps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) for (i = 0; i < ARRAY_SIZE(ov5640_framerates); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) int curr_fps = ov5640_framerates[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) if (abs(curr_fps - fps) < abs(best_fps - fps)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) best_fps = curr_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) rate = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) fi->numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) fi->denominator = best_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) find_mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) mode = ov5640_find_mode(sensor, rate, width, height, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) return mode ? rate : -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) static int ov5640_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) struct ov5640_dev *sensor = to_ov5640_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) struct v4l2_mbus_framefmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) if (format->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) mutex_lock(&sensor->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) if (format->which == V4L2_SUBDEV_FORMAT_TRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) fmt = v4l2_subdev_get_try_format(&sensor->sd, cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) format->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) fmt = &sensor->fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) format->format = *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) mutex_unlock(&sensor->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) static int ov5640_try_fmt_internal(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) struct v4l2_mbus_framefmt *fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) enum ov5640_frame_rate fr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) const struct ov5640_mode_info **new_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) struct ov5640_dev *sensor = to_ov5640_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) const struct ov5640_mode_info *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) mode = ov5640_find_mode(sensor, fr, fmt->width, fmt->height, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) if (!mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) fmt->width = mode->hact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) fmt->height = mode->vact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) if (new_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) *new_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) for (i = 0; i < ARRAY_SIZE(ov5640_formats); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) if (ov5640_formats[i].code == fmt->code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) if (i >= ARRAY_SIZE(ov5640_formats))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) fmt->code = ov5640_formats[i].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) fmt->colorspace = ov5640_formats[i].colorspace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) static int ov5640_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) struct v4l2_subdev_format *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) struct ov5640_dev *sensor = to_ov5640_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) const struct ov5640_mode_info *new_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) struct v4l2_mbus_framefmt *mbus_fmt = &format->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) struct v4l2_mbus_framefmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) if (format->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) mutex_lock(&sensor->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) if (sensor->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) ret = ov5640_try_fmt_internal(sd, mbus_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) sensor->current_fr, &new_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) if (format->which == V4L2_SUBDEV_FORMAT_TRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) fmt = v4l2_subdev_get_try_format(sd, cfg, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) fmt = &sensor->fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) *fmt = *mbus_fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) if (new_mode != sensor->current_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) sensor->current_mode = new_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) sensor->pending_mode_change = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) if (mbus_fmt->code != sensor->fmt.code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) sensor->pending_fmt_change = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) __v4l2_ctrl_s_ctrl_int64(sensor->ctrls.pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) ov5640_calc_pixel_rate(sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) mutex_unlock(&sensor->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) static int ov5640_set_framefmt(struct ov5640_dev *sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) struct v4l2_mbus_framefmt *format)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) bool is_jpeg = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) u8 fmt, mux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) switch (format->code) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) case MEDIA_BUS_FMT_UYVY8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) /* YUV422, UYVY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) fmt = 0x3f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) mux = OV5640_FMT_MUX_YUV422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) case MEDIA_BUS_FMT_YUYV8_2X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) /* YUV422, YUYV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) fmt = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) mux = OV5640_FMT_MUX_YUV422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) case MEDIA_BUS_FMT_RGB565_2X8_LE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) /* RGB565 {g[2:0],b[4:0]},{r[4:0],g[5:3]} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) fmt = 0x6F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) mux = OV5640_FMT_MUX_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) case MEDIA_BUS_FMT_RGB565_2X8_BE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) /* RGB565 {r[4:0],g[5:3]},{g[2:0],b[4:0]} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) fmt = 0x61;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) mux = OV5640_FMT_MUX_RGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) case MEDIA_BUS_FMT_JPEG_1X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) /* YUV422, YUYV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) fmt = 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) mux = OV5640_FMT_MUX_YUV422;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) is_jpeg = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) case MEDIA_BUS_FMT_SBGGR8_1X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) /* Raw, BGBG... / GRGR... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) fmt = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) mux = OV5640_FMT_MUX_RAW_DPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) case MEDIA_BUS_FMT_SGBRG8_1X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) /* Raw bayer, GBGB... / RGRG... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) fmt = 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) mux = OV5640_FMT_MUX_RAW_DPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) case MEDIA_BUS_FMT_SGRBG8_1X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) /* Raw bayer, GRGR... / BGBG... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) fmt = 0x02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) mux = OV5640_FMT_MUX_RAW_DPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) case MEDIA_BUS_FMT_SRGGB8_1X8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) /* Raw bayer, RGRG... / GBGB... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) fmt = 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) mux = OV5640_FMT_MUX_RAW_DPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) /* FORMAT CONTROL00: YUV and RGB formatting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) ret = ov5640_write_reg(sensor, OV5640_REG_FORMAT_CONTROL00, fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) /* FORMAT MUX CONTROL: ISP YUV or RGB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) ret = ov5640_write_reg(sensor, OV5640_REG_ISP_FORMAT_MUX_CTRL, mux);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) * TIMING TC REG21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) * - [5]: JPEG enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) ret = ov5640_mod_reg(sensor, OV5640_REG_TIMING_TC_REG21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) BIT(5), is_jpeg ? BIT(5) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) * SYSTEM RESET02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) * - [4]: Reset JFIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) * - [3]: Reset SFIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) * - [2]: Reset JPEG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) ret = ov5640_mod_reg(sensor, OV5640_REG_SYS_RESET02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) BIT(4) | BIT(3) | BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) is_jpeg ? 0 : (BIT(4) | BIT(3) | BIT(2)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) * CLOCK ENABLE02:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) * - [5]: Enable JPEG 2x clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) * - [3]: Enable JPEG clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) return ov5640_mod_reg(sensor, OV5640_REG_SYS_CLOCK_ENABLE02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) BIT(5) | BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) is_jpeg ? (BIT(5) | BIT(3)) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) * Sensor Controls.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) static int ov5640_set_ctrl_hue(struct ov5640_dev *sensor, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) BIT(0), BIT(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) ret = ov5640_write_reg16(sensor, OV5640_REG_SDE_CTRL1, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0, BIT(0), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) static int ov5640_set_ctrl_contrast(struct ov5640_dev *sensor, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) BIT(2), BIT(2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) ret = ov5640_write_reg(sensor, OV5640_REG_SDE_CTRL5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) value & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0, BIT(2), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) static int ov5640_set_ctrl_saturation(struct ov5640_dev *sensor, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) BIT(1), BIT(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) ret = ov5640_write_reg(sensor, OV5640_REG_SDE_CTRL3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) value & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) ret = ov5640_write_reg(sensor, OV5640_REG_SDE_CTRL4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) value & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) ret = ov5640_mod_reg(sensor, OV5640_REG_SDE_CTRL0, BIT(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) static int ov5640_set_ctrl_white_balance(struct ov5640_dev *sensor, int awb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) ret = ov5640_mod_reg(sensor, OV5640_REG_AWB_MANUAL_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) BIT(0), awb ? 0 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) if (!awb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) u16 red = (u16)sensor->ctrls.red_balance->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) u16 blue = (u16)sensor->ctrls.blue_balance->val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) ret = ov5640_write_reg16(sensor, OV5640_REG_AWB_R_GAIN, red);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) ret = ov5640_write_reg16(sensor, OV5640_REG_AWB_B_GAIN, blue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) static int ov5640_set_ctrl_exposure(struct ov5640_dev *sensor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) enum v4l2_exposure_auto_type auto_exposure)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) struct ov5640_ctrls *ctrls = &sensor->ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) bool auto_exp = (auto_exposure == V4L2_EXPOSURE_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) if (ctrls->auto_exp->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) ret = ov5640_set_autoexposure(sensor, auto_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) if (!auto_exp && ctrls->exposure->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) u16 max_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) ret = ov5640_read_reg16(sensor, OV5640_REG_AEC_PK_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) &max_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) ret = ov5640_get_vts(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) max_exp += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) if (ctrls->exposure->val < max_exp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) ret = ov5640_set_exposure(sensor, ctrls->exposure->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) static int ov5640_set_ctrl_gain(struct ov5640_dev *sensor, bool auto_gain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) struct ov5640_ctrls *ctrls = &sensor->ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) if (ctrls->auto_gain->is_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) ret = ov5640_set_autogain(sensor, auto_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) if (!auto_gain && ctrls->gain->is_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) ret = ov5640_set_gain(sensor, ctrls->gain->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) static const char * const test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) "Color bars",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) "Color bars w/ rolling bar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) "Color squares",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) "Color squares w/ rolling bar",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) #define OV5640_TEST_ENABLE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) #define OV5640_TEST_ROLLING BIT(6) /* rolling horizontal bar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) #define OV5640_TEST_TRANSPARENT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) #define OV5640_TEST_SQUARE_BW BIT(4) /* black & white squares */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) #define OV5640_TEST_BAR_STANDARD (0 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) #define OV5640_TEST_BAR_VERT_CHANGE_1 (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) #define OV5640_TEST_BAR_HOR_CHANGE (2 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) #define OV5640_TEST_BAR_VERT_CHANGE_2 (3 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) #define OV5640_TEST_BAR (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) #define OV5640_TEST_RANDOM (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) #define OV5640_TEST_SQUARE (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) #define OV5640_TEST_BLACK (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) static const u8 test_pattern_val[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) OV5640_TEST_ENABLE | OV5640_TEST_BAR_VERT_CHANGE_1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) OV5640_TEST_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) OV5640_TEST_ENABLE | OV5640_TEST_ROLLING |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) OV5640_TEST_BAR_VERT_CHANGE_1 | OV5640_TEST_BAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) OV5640_TEST_ENABLE | OV5640_TEST_SQUARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) OV5640_TEST_ENABLE | OV5640_TEST_ROLLING | OV5640_TEST_SQUARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) static int ov5640_set_ctrl_test_pattern(struct ov5640_dev *sensor, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) return ov5640_write_reg(sensor, OV5640_REG_PRE_ISP_TEST_SET1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) test_pattern_val[value]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) static int ov5640_set_ctrl_light_freq(struct ov5640_dev *sensor, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) ret = ov5640_mod_reg(sensor, OV5640_REG_HZ5060_CTRL01, BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) (value == V4L2_CID_POWER_LINE_FREQUENCY_AUTO) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) 0 : BIT(7));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) return ov5640_mod_reg(sensor, OV5640_REG_HZ5060_CTRL00, BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) (value == V4L2_CID_POWER_LINE_FREQUENCY_50HZ) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) BIT(2) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) static int ov5640_set_ctrl_hflip(struct ov5640_dev *sensor, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) * If sensor is mounted upside down, mirror logic is inversed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) * Sensor is a BSI (Back Side Illuminated) one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) * so image captured is physically mirrored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) * This is why mirror logic is inversed in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) * order to cancel this mirror effect.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) * TIMING TC REG21:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) * - [2]: ISP mirror
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) * - [1]: Sensor mirror
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) return ov5640_mod_reg(sensor, OV5640_REG_TIMING_TC_REG21,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) BIT(2) | BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) (!(value ^ sensor->upside_down)) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) (BIT(2) | BIT(1)) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) static int ov5640_set_ctrl_vflip(struct ov5640_dev *sensor, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) /* If sensor is mounted upside down, flip logic is inversed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) * TIMING TC REG20:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) * - [2]: ISP vflip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) * - [1]: Sensor vflip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) return ov5640_mod_reg(sensor, OV5640_REG_TIMING_TC_REG20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) BIT(2) | BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) (value ^ sensor->upside_down) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) (BIT(2) | BIT(1)) : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) static int ov5640_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) struct ov5640_dev *sensor = to_ov5640_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) /* v4l2_ctrl_lock() locks our own mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) case V4L2_CID_AUTOGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) val = ov5640_get_gain(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) sensor->ctrls.gain->val = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) case V4L2_CID_EXPOSURE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) val = ov5640_get_exposure(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) if (val < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) sensor->ctrls.exposure->val = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) static int ov5640_s_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) struct v4l2_subdev *sd = ctrl_to_sd(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) struct ov5640_dev *sensor = to_ov5640_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) /* v4l2_ctrl_lock() locks our own mutex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) * If the device is not powered up by the host driver do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) * not apply any controls to H/W at this time. Instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) * the controls will be restored right after power-up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) if (sensor->power_count == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) case V4L2_CID_AUTOGAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) ret = ov5640_set_ctrl_gain(sensor, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) case V4L2_CID_EXPOSURE_AUTO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) ret = ov5640_set_ctrl_exposure(sensor, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) case V4L2_CID_AUTO_WHITE_BALANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) ret = ov5640_set_ctrl_white_balance(sensor, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) case V4L2_CID_HUE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) ret = ov5640_set_ctrl_hue(sensor, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) case V4L2_CID_CONTRAST:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) ret = ov5640_set_ctrl_contrast(sensor, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) case V4L2_CID_SATURATION:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) ret = ov5640_set_ctrl_saturation(sensor, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) ret = ov5640_set_ctrl_test_pattern(sensor, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) case V4L2_CID_POWER_LINE_FREQUENCY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) ret = ov5640_set_ctrl_light_freq(sensor, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) ret = ov5640_set_ctrl_hflip(sensor, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) ret = ov5640_set_ctrl_vflip(sensor, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) static const struct v4l2_ctrl_ops ov5640_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) .g_volatile_ctrl = ov5640_g_volatile_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) .s_ctrl = ov5640_s_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) static int ov5640_init_controls(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) const struct v4l2_ctrl_ops *ops = &ov5640_ctrl_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) struct ov5640_ctrls *ctrls = &sensor->ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) struct v4l2_ctrl_handler *hdl = &ctrls->handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) v4l2_ctrl_handler_init(hdl, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) /* we can use our own mutex for the ctrl lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) hdl->lock = &sensor->lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) /* Clock related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) ctrls->pixel_rate = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) 0, INT_MAX, 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) ov5640_calc_pixel_rate(sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) /* Auto/manual white balance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) ctrls->auto_wb = v4l2_ctrl_new_std(hdl, ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) V4L2_CID_AUTO_WHITE_BALANCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) ctrls->blue_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_BLUE_BALANCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) 0, 4095, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) ctrls->red_balance = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_RED_BALANCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) 0, 4095, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) /* Auto/manual exposure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) ctrls->auto_exp = v4l2_ctrl_new_std_menu(hdl, ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) V4L2_CID_EXPOSURE_AUTO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) V4L2_EXPOSURE_MANUAL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) V4L2_EXPOSURE_AUTO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) ctrls->exposure = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) 0, 65535, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) /* Auto/manual gain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) ctrls->auto_gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_AUTOGAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) 0, 1, 1, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) ctrls->gain = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) 0, 1023, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) ctrls->saturation = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_SATURATION,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) 0, 255, 1, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) ctrls->hue = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) 0, 359, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) ctrls->contrast = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_CONTRAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) 0, 255, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) ctrls->test_pattern =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) ARRAY_SIZE(test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) 0, 0, test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) ctrls->hflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HFLIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) ctrls->vflip = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VFLIP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) ctrls->light_freq =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) v4l2_ctrl_new_std_menu(hdl, ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) V4L2_CID_POWER_LINE_FREQUENCY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) V4L2_CID_POWER_LINE_FREQUENCY_AUTO, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) V4L2_CID_POWER_LINE_FREQUENCY_50HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) if (hdl->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) ret = hdl->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) goto free_ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) ctrls->pixel_rate->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) ctrls->gain->flags |= V4L2_CTRL_FLAG_VOLATILE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) ctrls->exposure->flags |= V4L2_CTRL_FLAG_VOLATILE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) v4l2_ctrl_auto_cluster(3, &ctrls->auto_wb, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) v4l2_ctrl_auto_cluster(2, &ctrls->auto_gain, 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) v4l2_ctrl_auto_cluster(2, &ctrls->auto_exp, 1, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) sensor->sd.ctrl_handler = hdl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) free_ctrls:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) v4l2_ctrl_handler_free(hdl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) static int ov5640_enum_frame_size(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) if (fse->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) if (fse->index >= OV5640_NUM_MODES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) fse->min_width =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) ov5640_mode_data[fse->index].hact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) fse->max_width = fse->min_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) fse->min_height =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) ov5640_mode_data[fse->index].vact;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) fse->max_height = fse->min_height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) static int ov5640_enum_frame_interval(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) struct ov5640_dev *sensor = to_ov5640_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) struct v4l2_fract tpf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) if (fie->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) if (fie->index >= OV5640_NUM_FRAMERATES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) tpf.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) tpf.denominator = ov5640_framerates[fie->index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) ret = ov5640_try_frame_interval(sensor, &tpf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) fie->width, fie->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) fie->interval = tpf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) static int ov5640_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) struct ov5640_dev *sensor = to_ov5640_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) mutex_lock(&sensor->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) fi->interval = sensor->frame_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) mutex_unlock(&sensor->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) static int ov5640_s_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) struct ov5640_dev *sensor = to_ov5640_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) const struct ov5640_mode_info *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) int frame_rate, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) if (fi->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) mutex_lock(&sensor->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) if (sensor->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) mode = sensor->current_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) frame_rate = ov5640_try_frame_interval(sensor, &fi->interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) mode->hact, mode->vact);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) if (frame_rate < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) /* Always return a valid frame interval value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) fi->interval = sensor->frame_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) mode = ov5640_find_mode(sensor, frame_rate, mode->hact,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) mode->vact, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) if (!mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) if (mode != sensor->current_mode ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) frame_rate != sensor->current_fr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) sensor->current_fr = frame_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) sensor->frame_interval = fi->interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) sensor->current_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) sensor->pending_mode_change = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) __v4l2_ctrl_s_ctrl_int64(sensor->ctrls.pixel_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) ov5640_calc_pixel_rate(sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) mutex_unlock(&sensor->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) static int ov5640_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) if (code->pad != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) if (code->index >= ARRAY_SIZE(ov5640_formats))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) code->code = ov5640_formats[code->index].code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) static int ov5640_s_stream(struct v4l2_subdev *sd, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) struct ov5640_dev *sensor = to_ov5640_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) mutex_lock(&sensor->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) if (sensor->streaming == !enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) if (enable && sensor->pending_mode_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) ret = ov5640_set_mode(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) if (enable && sensor->pending_fmt_change) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) ret = ov5640_set_framefmt(sensor, &sensor->fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) sensor->pending_fmt_change = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) if (sensor->ep.bus_type == V4L2_MBUS_CSI2_DPHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) ret = ov5640_set_stream_mipi(sensor, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) ret = ov5640_set_stream_dvp(sensor, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) sensor->streaming = enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) mutex_unlock(&sensor->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) static const struct v4l2_subdev_core_ops ov5640_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) .s_power = ov5640_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) .log_status = v4l2_ctrl_subdev_log_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) .unsubscribe_event = v4l2_event_subdev_unsubscribe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) static const struct v4l2_subdev_video_ops ov5640_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) .g_frame_interval = ov5640_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) .s_frame_interval = ov5640_s_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) .s_stream = ov5640_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) static const struct v4l2_subdev_pad_ops ov5640_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) .enum_mbus_code = ov5640_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) .get_fmt = ov5640_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) .set_fmt = ov5640_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) .enum_frame_size = ov5640_enum_frame_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) .enum_frame_interval = ov5640_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) static const struct v4l2_subdev_ops ov5640_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) .core = &ov5640_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) .video = &ov5640_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) .pad = &ov5640_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) static int ov5640_get_regulators(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) for (i = 0; i < OV5640_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) sensor->supplies[i].supply = ov5640_supply_name[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) return devm_regulator_bulk_get(&sensor->i2c_client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) OV5640_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) sensor->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) static int ov5640_check_chip_id(struct ov5640_dev *sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) struct i2c_client *client = sensor->i2c_client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) u16 chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) ret = ov5640_set_power_on(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) ret = ov5640_read_reg16(sensor, OV5640_REG_CHIP_ID, &chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) dev_err(&client->dev, "%s: failed to read chip identifier\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) goto power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) if (chip_id != 0x5640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) dev_err(&client->dev, "%s: wrong chip identifier, expected 0x5640, got 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) __func__, chip_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) ret = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) ov5640_set_power_off(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) static int ov5640_probe(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) struct fwnode_handle *endpoint;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) struct ov5640_dev *sensor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) struct v4l2_mbus_framefmt *fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) u32 rotation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) sensor = devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) if (!sensor)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) sensor->i2c_client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) * default init sequence initialize sensor to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) * YUV422 UYVY VGA@30fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) fmt = &sensor->fmt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) fmt->colorspace = V4L2_COLORSPACE_SRGB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) fmt->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt->colorspace);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) fmt->quantization = V4L2_QUANTIZATION_FULL_RANGE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) fmt->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt->colorspace);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) fmt->width = 640;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) fmt->height = 480;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) sensor->frame_interval.numerator = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) sensor->frame_interval.denominator = ov5640_framerates[OV5640_30_FPS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) sensor->current_fr = OV5640_30_FPS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) sensor->current_mode =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) &ov5640_mode_data[OV5640_MODE_VGA_640_480];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) sensor->last_mode = sensor->current_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) sensor->ae_target = 52;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) /* optional indication of physical rotation of sensor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) ret = fwnode_property_read_u32(dev_fwnode(&client->dev), "rotation",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) &rotation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) switch (rotation) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) case 180:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) sensor->upside_down = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) dev_warn(dev, "%u degrees rotation is not supported, ignoring...\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) rotation);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(&client->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) if (!endpoint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) dev_err(dev, "endpoint node not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) ret = v4l2_fwnode_endpoint_parse(endpoint, &sensor->ep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) fwnode_handle_put(endpoint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) dev_err(dev, "Could not parse endpoint\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) if (sensor->ep.bus_type != V4L2_MBUS_PARALLEL &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) sensor->ep.bus_type != V4L2_MBUS_CSI2_DPHY &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) sensor->ep.bus_type != V4L2_MBUS_BT656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) dev_err(dev, "Unsupported bus type %d\n", sensor->ep.bus_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) /* get system clock (xclk) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) sensor->xclk = devm_clk_get(dev, "xclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) if (IS_ERR(sensor->xclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) dev_err(dev, "failed to get xclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) return PTR_ERR(sensor->xclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) sensor->xclk_freq = clk_get_rate(sensor->xclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) if (sensor->xclk_freq < OV5640_XCLK_MIN ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) sensor->xclk_freq > OV5640_XCLK_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) dev_err(dev, "xclk frequency out of range: %d Hz\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) sensor->xclk_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) /* request optional power down pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) sensor->pwdn_gpio = devm_gpiod_get_optional(dev, "powerdown",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) if (IS_ERR(sensor->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) return PTR_ERR(sensor->pwdn_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) /* request optional reset pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) sensor->reset_gpio = devm_gpiod_get_optional(dev, "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) GPIOD_OUT_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) if (IS_ERR(sensor->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) return PTR_ERR(sensor->reset_gpio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) v4l2_i2c_subdev_init(&sensor->sd, client, &ov5640_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) sensor->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) sensor->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) sensor->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) ret = media_entity_pads_init(&sensor->sd.entity, 1, &sensor->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) ret = ov5640_get_regulators(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) mutex_init(&sensor->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) ret = ov5640_check_chip_id(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) goto entity_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) ret = ov5640_init_controls(sensor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) goto entity_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) ret = v4l2_async_register_subdev_sensor_common(&sensor->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) goto free_ctrls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) free_ctrls:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) v4l2_ctrl_handler_free(&sensor->ctrls.handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) entity_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) media_entity_cleanup(&sensor->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) mutex_destroy(&sensor->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) static int ov5640_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) struct ov5640_dev *sensor = to_ov5640_dev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) v4l2_async_unregister_subdev(&sensor->sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) media_entity_cleanup(&sensor->sd.entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) v4l2_ctrl_handler_free(&sensor->ctrls.handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) mutex_destroy(&sensor->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) static const struct i2c_device_id ov5640_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) {"ov5640", 0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) MODULE_DEVICE_TABLE(i2c, ov5640_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) static const struct of_device_id ov5640_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) { .compatible = "ovti,ov5640" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) MODULE_DEVICE_TABLE(of, ov5640_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) static struct i2c_driver ov5640_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) .name = "ov5640",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) .of_match_table = ov5640_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) .id_table = ov5640_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) .probe_new = ov5640_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) .remove = ov5640_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) module_i2c_driver(ov5640_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) MODULE_DESCRIPTION("OV5640 MIPI Camera Subdev Driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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