^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * ov4689 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 add poweron function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * V0.0X01.0X02 fix mclk issue when probe multiple camera.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * V0.0X01.0X03 fix gain range.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * V0.0X01.0X04 add enum_frame_interval function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * V0.0X01.0X05 add hdr config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * V0.0X01.0X06 support enum sensor fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * V0.0X01.0X07 add quick stream on/off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * V0.0X01.0X08 fixed hdr 2 exposure issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) //#define DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define OV4689_LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define OV4689_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OV4689_LINK_FREQ_500MHZ 500000000LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OV4689_PIXEL_RATE (OV4689_LINK_FREQ_500MHZ * 2 * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) OV4689_LANES / OV4689_BITS_PER_SAMPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OV4689_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CHIP_ID 0x004688
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OV4689_REG_CHIP_ID 0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OV4689_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define OV4689_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OV4689_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OV4689_REG_EXPOSURE 0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OV4689_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OV4689_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OV4689_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OV4689_REG_GAIN_H 0x3508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OV4689_REG_GAIN_L 0x3509
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define OV4689_GAIN_H_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OV4689_GAIN_H_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OV4689_GAIN_L_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OV4689_GAIN_MIN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OV4689_GAIN_MAX 0x7f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OV4689_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OV4689_GAIN_DEFAULT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OV4689_REG_L_GAIN 0x3508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OV4689_REG_M_GAIN 0x350e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OV4689_REG_S_GAIN 0x3514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OV4689_REG_L_EXP 0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define OV4689_REG_M_EXP 0x350a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OV4689_REG_S_EXP 0x3510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OV4689_GROUP_UPDATE_ADDRESS 0x3208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define OV4689_GROUP_UPDATE_START_DATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OV4689_GROUP_UPDATE_END_DATA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define OV4689_GROUP_UPDATE_LAUNCH 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OV4689_REG_TEST_PATTERN 0x5040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define OV4689_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define OV4689_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define OV4689_REG_VTS 0x380e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OV4689_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define OV4689_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OV4689_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OV4689_NAME "ov4689"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static const char * const ov4689_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define OV4689_NUM_SUPPLIES ARRAY_SIZE(ov4689_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct ov4689_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct ov4689 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct regulator_bulk_data supplies[OV4689_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const struct ov4689_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 cur_vts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define to_ov4689(sd) container_of(sd, struct ov4689, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static const struct regval ov4689_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * max_framerate 90fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * mipi_datarate per lane 1008Mbps, 4lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct regval ov4689_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x3638, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x0300, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x0302, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x0303, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x0304, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x030b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x030d, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x030e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x030f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x0312, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x031e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x3000, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x3018, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3020, 0x93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x3021, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x3022, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x3031, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x303f, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3305, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3307, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3309, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3501, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3502, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3503, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3504, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3505, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3506, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x3507, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x3508, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x3509, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x350a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x350b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x350c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x350d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x350e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x350f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3510, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3511, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3512, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3513, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3514, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3515, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3516, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x3517, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x3518, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x3519, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x351a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x351b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x351c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x351d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x351e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x351f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3520, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3521, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3522, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x3524, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3526, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3528, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x352a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3602, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3603, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3604, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x3605, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x3606, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x3607, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x3609, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x360a, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x360c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x360f, 0xe5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x3608, 0x8f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x3611, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x3613, 0xf7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x3616, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x3619, 0x99},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x361b, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x361c, 0x7a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x361e, 0x79},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x361f, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3632, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3633, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x3634, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x3635, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3636, 0x15},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3646, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x364a, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x3700, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3701, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3703, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x370a, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x3705, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x3706, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3709, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x370b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x370c, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3710, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3711, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x3716, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x3720, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x3729, 0x7b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x372a, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x372b, 0xbd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x372c, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x372e, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x373c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x373e, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x3743, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x3744, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x3745, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x374a, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x374c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x374e, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x3751, 0x7b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x3752, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x3753, 0xbd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x3754, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x3756, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x375c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x3760, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x3761, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x3762, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3763, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x3764, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x3767, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x3768, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x3769, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x376a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x376b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x376c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x376d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x376e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x3773, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x3774, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x3776, 0xbd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3777, 0xbd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x3781, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3783, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3798, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x3801, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x3803, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x3804, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x3805, 0x97},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x3806, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x3807, 0xfb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x3808, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x380a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x380b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x380c, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x380d, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x380e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x380f, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x3810, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x3811, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x3812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x3813, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x3814, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x3815, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x3819, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x3820, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x3821, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x3829, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x382a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x382b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x382d, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x3830, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x3836, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x3837, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x3841, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x3846, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x3847, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x3d85, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x3d8c, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x3d8d, 0xcb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x3f0a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x4000, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x4001, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x4002, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x4003, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x400e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x4011, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x401a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x401b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x401c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x401d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x401f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x4020, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x4021, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x4022, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x4023, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x4024, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x4025, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x4026, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x4027, 0x6f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x4028, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x4029, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x402a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x402b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x402c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x402d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x402e, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x402f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x4302, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x4303, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x4304, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x4305, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x4306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x4308, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x4500, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x4501, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x4502, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x4503, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x4601, 0xa7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x4800, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x4813, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x481f, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x4829, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x4837, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x4b00, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x4b0d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x4d00, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x4d01, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x4d02, 0xd1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x4d03, 0x93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x4d04, 0xf5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x4d05, 0xc1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x5000, 0xf3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x5001, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x5004, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x500a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x500b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x5032, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x5040, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x5050, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x5500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x5501, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x5502, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x5503, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x8000, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x8001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x8002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x8003, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x8004, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x8005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x8006, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {0x8007, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {0x8008, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {0x3638, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static const struct regval ov4689_linear_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x380c, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x380d, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {0x3841, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {0x4800, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) {0x376e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static const struct regval ov4689_hdr_x2_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x380c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x380d, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x3841, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x3846, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x3847, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x4800, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x376e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x350b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x3511, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) {0x3517, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x351d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {0x3841, 0x03},//HDR_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) {0x3847, 0x06},//HDR_2_ALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static const struct regval ov4689_hdr_x3_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {0x380c, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {0x380d, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {0x3841, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) {0x3846, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {0x3847, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {0x4800, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) {0x376e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) {0x350b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {0x3511, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {0x3517, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) {0x351d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {0x3841, 0x13},//HDR_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {0x3847, 0x07},//HDR_3_ALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static const struct ov4689_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .width = 2688,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .height = 1520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .exp_def = 0x0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .hts_def = 0x0a18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .vts_def = 0x0612,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .reg_list = ov4689_linear_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .width = 2688,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .height = 1520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .exp_def = 0x0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .hts_def = 0x0510,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .vts_def = 0x0612,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .reg_list = ov4689_hdr_x2_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .width = 2688,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .height = 1520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .denominator = 100000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .exp_def = 0x0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .hts_def = 0x0a20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .vts_def = 0x0612,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) .reg_list = ov4689_hdr_x3_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .hdr_mode = HDR_X3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_2,//S->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) OV4689_LINK_FREQ_500MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static const char * const ov4689_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static int ov4689_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) static int ov4689_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ret = ov4689_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) OV4689_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static int ov4689_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static int ov4689_get_reso_dist(const struct ov4689_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static const struct ov4689_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ov4689_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) dist = ov4689_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static int ov4689_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct ov4689 *ov4689 = to_ov4689(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) const struct ov4689_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) mutex_lock(&ov4689->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) mode = ov4689_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) mutex_unlock(&ov4689->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) ov4689->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) __v4l2_ctrl_modify_range(ov4689->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) __v4l2_ctrl_modify_range(ov4689->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) OV4689_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) mutex_unlock(&ov4689->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) static int ov4689_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct ov4689 *ov4689 = to_ov4689(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) const struct ov4689_mode *mode = ov4689->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) mutex_lock(&ov4689->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) mutex_unlock(&ov4689->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* format info: width/height/data type/virctual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) mutex_unlock(&ov4689->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static int ov4689_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) static int ov4689_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) static int ov4689_enable_test_pattern(struct ov4689 *ov4689, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) val = (pattern - 1) | OV4689_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) val = OV4689_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return ov4689_write_reg(ov4689->client, OV4689_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) OV4689_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static int ov4689_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct ov4689 *ov4689 = to_ov4689(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) const struct ov4689_mode *mode = ov4689->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) mutex_lock(&ov4689->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) mutex_unlock(&ov4689->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static int ov4689_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) struct ov4689 *ov4689 = to_ov4689(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) const struct ov4689_mode *mode = ov4689->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) u32 val = 1 << (OV4689_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) val |= V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) if (mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) val |= V4L2_MBUS_CSI2_CHANNEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static void ov4689_get_module_inf(struct ov4689 *ov4689,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) strlcpy(inf->base.sensor, OV4689_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) strlcpy(inf->base.module, ov4689->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) strlcpy(inf->base.lens, ov4689->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static int ov4689_set_hdrae(struct ov4689 *ov4689,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) u32 l_exp = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) u32 m_exp = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) u32 s_exp = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u32 l_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u32 m_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) u32 s_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) if (!ov4689->has_init_exp && !ov4689->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) ov4689->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ov4689->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) dev_dbg(&ov4689->client->dev, "ov4689 don't stream, record exp for hdr!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) dev_dbg(&ov4689->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) l_exp, m_exp, s_exp, l_gain, m_gain, s_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (l_exp < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) l_exp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (m_exp < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) m_exp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (s_exp < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) s_exp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (ov4689->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) l_gain = m_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) l_exp = m_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) m_gain = s_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) m_exp = s_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) if (l_exp <= m_exp ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) l_exp + m_exp >= ov4689->cur_vts - 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) dev_err(&ov4689->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) "exp parameter error, l_exp %d, s_exp %d, cur_vts %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) l_exp, m_exp, ov4689->cur_vts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (l_exp <= m_exp ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) m_exp <= s_exp ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) l_exp + m_exp + s_exp >= ov4689->cur_vts - 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dev_err(&ov4689->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) "exp parameter error, l_exp %d, m_exp %d, s_exp %d, cur_vts %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) l_exp, m_exp, s_exp, ov4689->cur_vts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ret = ov4689_write_reg(ov4689->client, OV4689_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) OV4689_REG_VALUE_08BIT, OV4689_GROUP_UPDATE_START_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ret |= ov4689_write_reg(ov4689->client, OV4689_REG_L_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) OV4689_REG_VALUE_16BIT, l_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ret |= ov4689_write_reg(ov4689->client, OV4689_REG_L_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) OV4689_REG_VALUE_24BIT, l_exp << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ret |= ov4689_write_reg(ov4689->client, OV4689_REG_M_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) OV4689_REG_VALUE_16BIT, m_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) ret |= ov4689_write_reg(ov4689->client, OV4689_REG_M_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) OV4689_REG_VALUE_24BIT, m_exp << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (ov4689->cur_mode->hdr_mode == HDR_X3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ret |= ov4689_write_reg(ov4689->client, OV4689_REG_S_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) OV4689_REG_VALUE_16BIT, s_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) ret |= ov4689_write_reg(ov4689->client, OV4689_REG_S_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) OV4689_REG_VALUE_24BIT, s_exp << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) ret |= ov4689_write_reg(ov4689->client, OV4689_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) OV4689_REG_VALUE_08BIT, OV4689_GROUP_UPDATE_END_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) ret |= ov4689_write_reg(ov4689->client, OV4689_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) OV4689_REG_VALUE_08BIT, OV4689_GROUP_UPDATE_LAUNCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static long ov4689_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct ov4689 *ov4689 = to_ov4689(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ov4689_get_module_inf(ov4689, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) hdr->hdr_mode = ov4689->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) w = ov4689->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) h = ov4689->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ov4689->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (i == ARRAY_SIZE(supported_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) dev_err(&ov4689->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) dev_dbg(&ov4689->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) "set hdr mode:%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ov4689->cur_mode->hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) w = ov4689->cur_mode->hts_def - ov4689->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) h = ov4689->cur_mode->vts_def - ov4689->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) __v4l2_ctrl_modify_range(ov4689->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) __v4l2_ctrl_modify_range(ov4689->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) OV4689_VTS_MAX - ov4689->cur_mode->height, 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) return ov4689_set_hdrae(ov4689, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ret = ov4689_write_reg(ov4689->client, OV4689_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) OV4689_REG_VALUE_08BIT, OV4689_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ret = ov4689_write_reg(ov4689->client, OV4689_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) OV4689_REG_VALUE_08BIT, OV4689_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static long ov4689_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ret = ov4689_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ret = ov4689_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ret = ov4689_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ret = ov4689_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ret = ov4689_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ret = ov4689_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static int __ov4689_start_stream(struct ov4689 *ov4689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ret = ov4689_write_array(ov4689->client, ov4689_2688x1520_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ret |= ov4689_write_array(ov4689->client, ov4689->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) ret = __v4l2_ctrl_handler_setup(&ov4689->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (ov4689->has_init_exp && ov4689->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ret = ov4689_ioctl(&ov4689->subdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) &ov4689->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) dev_err(&ov4689->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) return ov4689_write_reg(ov4689->client, OV4689_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) OV4689_REG_VALUE_08BIT, OV4689_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) static int __ov4689_stop_stream(struct ov4689 *ov4689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) ov4689->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) return ov4689_write_reg(ov4689->client, OV4689_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) OV4689_REG_VALUE_08BIT, OV4689_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static int ov4689_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct ov4689 *ov4689 = to_ov4689(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct i2c_client *client = ov4689->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) mutex_lock(&ov4689->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (on == ov4689->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) ret = __ov4689_start_stream(ov4689);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) __ov4689_stop_stream(ov4689);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) ov4689->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) mutex_unlock(&ov4689->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static int ov4689_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct ov4689 *ov4689 = to_ov4689(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) struct i2c_client *client = ov4689->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) mutex_lock(&ov4689->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (ov4689->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ret = ov4689_write_array(ov4689->client, ov4689_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ov4689->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) ov4689->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) mutex_unlock(&ov4689->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static inline u32 ov4689_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return DIV_ROUND_UP(cycles, OV4689_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static int __ov4689_power_on(struct ov4689 *ov4689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct device *dev = &ov4689->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (!IS_ERR_OR_NULL(ov4689->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) ret = pinctrl_select_state(ov4689->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) ov4689->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ret = clk_set_rate(ov4689->xvclk, OV4689_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) if (clk_get_rate(ov4689->xvclk) != OV4689_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) ret = clk_prepare_enable(ov4689->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (!IS_ERR(ov4689->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) gpiod_set_value_cansleep(ov4689->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) ret = regulator_bulk_enable(OV4689_NUM_SUPPLIES, ov4689->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) if (!IS_ERR(ov4689->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) gpiod_set_value_cansleep(ov4689->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) if (!IS_ERR(ov4689->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) gpiod_set_value_cansleep(ov4689->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) delay_us = ov4689_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) clk_disable_unprepare(ov4689->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) static void __ov4689_power_off(struct ov4689 *ov4689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct device *dev = &ov4689->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (!IS_ERR(ov4689->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) gpiod_set_value_cansleep(ov4689->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) clk_disable_unprepare(ov4689->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (!IS_ERR(ov4689->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) gpiod_set_value_cansleep(ov4689->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (!IS_ERR_OR_NULL(ov4689->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ret = pinctrl_select_state(ov4689->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ov4689->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) regulator_bulk_disable(OV4689_NUM_SUPPLIES, ov4689->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) static int ov4689_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct ov4689 *ov4689 = to_ov4689(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return __ov4689_power_on(ov4689);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) static int ov4689_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) struct ov4689 *ov4689 = to_ov4689(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) __ov4689_power_off(ov4689);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static int ov4689_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) struct ov4689 *ov4689 = to_ov4689(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) const struct ov4689_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) mutex_lock(&ov4689->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) mutex_unlock(&ov4689->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static int ov4689_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) fie->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static const struct dev_pm_ops ov4689_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) SET_RUNTIME_PM_OPS(ov4689_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) ov4689_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) static const struct v4l2_subdev_internal_ops ov4689_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) .open = ov4689_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) static const struct v4l2_subdev_core_ops ov4689_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) .s_power = ov4689_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) .ioctl = ov4689_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) .compat_ioctl32 = ov4689_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static const struct v4l2_subdev_video_ops ov4689_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) .s_stream = ov4689_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) .g_frame_interval = ov4689_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) static const struct v4l2_subdev_pad_ops ov4689_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) .enum_mbus_code = ov4689_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) .enum_frame_size = ov4689_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) .enum_frame_interval = ov4689_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) .get_fmt = ov4689_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) .set_fmt = ov4689_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) .get_mbus_config = ov4689_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) static const struct v4l2_subdev_ops ov4689_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) .core = &ov4689_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) .video = &ov4689_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) .pad = &ov4689_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) static int ov4689_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct ov4689 *ov4689 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) struct ov4689, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct i2c_client *client = ov4689->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) max = ov4689->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) __v4l2_ctrl_modify_range(ov4689->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) ov4689->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) ov4689->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) ov4689->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) ret = ov4689_write_reg(ov4689->client, OV4689_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) OV4689_REG_VALUE_24BIT, ctrl->val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) dev_dbg(&client->dev, "%s set exposure %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) __func__, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) ret = ov4689_write_reg(ov4689->client, OV4689_REG_GAIN_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) OV4689_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) (ctrl->val >> OV4689_GAIN_H_SHIFT) & OV4689_GAIN_H_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) ret |= ov4689_write_reg(ov4689->client, OV4689_REG_GAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) OV4689_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) ctrl->val & OV4689_GAIN_L_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) dev_dbg(&client->dev, "%s set gain %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) __func__, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) ret = ov4689_write_reg(ov4689->client, OV4689_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) OV4689_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) ctrl->val + ov4689->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) ov4689->cur_vts = ctrl->val + ov4689->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) dev_dbg(&client->dev, "%s set vts %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) __func__, ov4689->cur_vts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) ret = ov4689_enable_test_pattern(ov4689, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) static const struct v4l2_ctrl_ops ov4689_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) .s_ctrl = ov4689_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) static int ov4689_initialize_controls(struct ov4689 *ov4689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) const struct ov4689_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) handler = &ov4689->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) mode = ov4689->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) ret = v4l2_ctrl_handler_init(handler, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) handler->lock = &ov4689->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) 0, OV4689_PIXEL_RATE, 1, OV4689_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) ov4689->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (ov4689->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) ov4689->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) ov4689->vblank = v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) OV4689_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) ov4689->cur_vts = mode->vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) ov4689->exposure = v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) V4L2_CID_EXPOSURE, OV4689_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) exposure_max, OV4689_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) ov4689->anal_gain = v4l2_ctrl_new_std(handler, &ov4689_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) V4L2_CID_ANALOGUE_GAIN, OV4689_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) OV4689_GAIN_MAX, OV4689_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) OV4689_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) ov4689->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) &ov4689_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) ARRAY_SIZE(ov4689_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) 0, 0, ov4689_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) dev_err(&ov4689->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) ov4689->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) ov4689->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) static int ov4689_check_sensor_id(struct ov4689 *ov4689,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) struct device *dev = &ov4689->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) ret = ov4689_read_reg(client, OV4689_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) OV4689_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) static int ov4689_configure_regulators(struct ov4689 *ov4689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) for (i = 0; i < OV4689_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) ov4689->supplies[i].supply = ov4689_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) return devm_regulator_bulk_get(&ov4689->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) OV4689_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) ov4689->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) static int ov4689_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) struct ov4689 *ov4689;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) ov4689 = devm_kzalloc(dev, sizeof(*ov4689), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) if (!ov4689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) &ov4689->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) &ov4689->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) &ov4689->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) &ov4689->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) ov4689->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) ov4689->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) if (i == ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) ov4689->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) ov4689->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) if (IS_ERR(ov4689->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) ov4689->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (IS_ERR(ov4689->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) ov4689->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (IS_ERR(ov4689->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) ov4689->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) if (!IS_ERR(ov4689->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) ov4689->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) pinctrl_lookup_state(ov4689->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) if (IS_ERR(ov4689->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) ov4689->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) pinctrl_lookup_state(ov4689->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) if (IS_ERR(ov4689->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) ret = ov4689_configure_regulators(ov4689);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) mutex_init(&ov4689->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) sd = &ov4689->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) v4l2_i2c_subdev_init(sd, client, &ov4689_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) ret = ov4689_initialize_controls(ov4689);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) ret = __ov4689_power_on(ov4689);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) ret = ov4689_check_sensor_id(ov4689, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) sd->internal_ops = &ov4689_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) ov4689->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) ret = media_entity_pads_init(&sd->entity, 1, &ov4689->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) if (strcmp(ov4689->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) ov4689->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) OV4689_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) __ov4689_power_off(ov4689);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) v4l2_ctrl_handler_free(&ov4689->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) mutex_destroy(&ov4689->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) static int ov4689_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) struct ov4689 *ov4689 = to_ov4689(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) v4l2_ctrl_handler_free(&ov4689->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) mutex_destroy(&ov4689->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) __ov4689_power_off(ov4689);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) static const struct of_device_id ov4689_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) { .compatible = "ovti,ov4689" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) MODULE_DEVICE_TABLE(of, ov4689_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) static const struct i2c_device_id ov4689_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) { "ovti,ov4689", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) static struct i2c_driver ov4689_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .name = OV4689_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .pm = &ov4689_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .of_match_table = of_match_ptr(ov4689_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .probe = &ov4689_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .remove = &ov4689_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .id_table = ov4689_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) return i2c_add_driver(&ov4689_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) i2c_del_driver(&ov4689_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) MODULE_DESCRIPTION("OmniVision ov4689 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags