^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * OV4686 driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2020 Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * V0.0X01.0X01 first version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/i2c.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/sysfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/version.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/rk-camera-module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/rk-preisp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <media/media-entity.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <media/v4l2-async.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <media/v4l2-ctrls.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <media/v4l2-subdev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/pinctrl/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRIVER_VERSION KERNEL_VERSION(0, 0x01, 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #ifndef V4L2_CID_DIGITAL_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define V4L2_CID_DIGITAL_GAIN V4L2_CID_GAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define OV4686_LANES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define OV4686_BITS_PER_SAMPLE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define OV4686_LINK_FREQ_500MHZ 500000000LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* pixel rate = link frequency * 2 * lanes / BITS_PER_SAMPLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define OV4686_PIXEL_RATE (OV4686_LINK_FREQ_500MHZ * 2 * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) OV4686_LANES / OV4686_BITS_PER_SAMPLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define OV4686_XVCLK_FREQ 24000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CHIP_ID 0x004688
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define OV4686_REG_CHIP_ID 0x300a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define OV4686_REG_CTRL_MODE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define OV4686_MODE_SW_STANDBY 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define OV4686_MODE_STREAMING BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define OV4686_REG_EXPOSURE 0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define OV4686_EXPOSURE_MIN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define OV4686_EXPOSURE_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define OV4686_VTS_MAX 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define OV4686_REG_GAIN_H 0x3508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define OV4686_REG_GAIN_L 0x3509//low 7bit fraction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define OV4686_GAIN_H_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define OV4686_GAIN_H_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define OV4686_GAIN_L_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define OV4686_GAIN_MIN 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define OV4686_GAIN_MAX 0x7f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define OV4686_GAIN_STEP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define OV4686_GAIN_DEFAULT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define OV4686_REG_L_GAIN 0x3508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define OV4686_REG_M_GAIN 0x350e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define OV4686_REG_S_GAIN 0x3514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define OV4686_REG_L_EXP 0x3500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define OV4686_REG_M_EXP 0x350a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define OV4686_REG_S_EXP 0x3510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define OV4686_GROUP_UPDATE_ADDRESS 0x3208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define OV4686_GROUP_UPDATE_START_DATA 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define OV4686_GROUP_UPDATE_END_DATA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define OV4686_GROUP_UPDATE_LAUNCH 0xA0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define OV4686_REG_TEST_PATTERN 0x5040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define OV4686_TEST_PATTERN_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define OV4686_TEST_PATTERN_DISABLE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define OV4686_REG_VTS 0x380e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define OV4686_VFLIP_REG 0x3820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define OV4686_HFLIP_REG 0x3821
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MIRROR_BIT_MASK (BIT(1) | BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define FLIP_BIT_MASK (BIT(1) | BIT(2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define REG_NULL 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define OV4686_REG_VALUE_08BIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define OV4686_REG_VALUE_16BIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define OV4686_REG_VALUE_24BIT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define OF_CAMERA_PINCTRL_STATE_DEFAULT "rockchip,camera_default"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define OF_CAMERA_PINCTRL_STATE_SLEEP "rockchip,camera_sleep"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define OF_CAMERA_HDR_MODE "rockchip,camera-hdr-mode"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define OV4686_NAME "ov4686"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static const char * const OV4686_supply_names[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) "avdd", /* Analog power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) "dovdd", /* Digital I/O power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) "dvdd", /* Digital core power */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define OV4686_NUM_SUPPLIES ARRAY_SIZE(OV4686_supply_names)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct regval {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u16 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u8 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct OV4686_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct v4l2_fract max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 hts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 vts_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 exp_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) const struct regval *reg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 vc[PAD_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct OV4686 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct i2c_client *client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct clk *xvclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct gpio_desc *pwdn_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct regulator_bulk_data supplies[OV4686_NUM_SUPPLIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct pinctrl *pinctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct pinctrl_state *pins_default;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct pinctrl_state *pins_sleep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct v4l2_subdev subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct media_pad pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct v4l2_ctrl_handler ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct v4l2_ctrl *exposure;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct v4l2_ctrl *anal_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct v4l2_ctrl *digi_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct v4l2_ctrl *hblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct v4l2_ctrl *vblank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct v4l2_ctrl *test_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct mutex mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) bool streaming;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) bool power_on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) const struct OV4686_mode *cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 module_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) const char *module_facing;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) const char *module_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) const char *len_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) bool has_init_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct preisp_hdrae_exp_s init_hdrae_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define to_OV4686(sd) container_of(sd, struct OV4686, subdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const struct regval OV4686_global_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * Xclk 24Mhz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * max_framerate 90fps
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * mipi_datarate per lane 1008Mbps, 4lane
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static const struct regval OV4686_2688x1520_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {0x0103, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {0x3638, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {0x0300, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {0x0302, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {0x0303, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {0x0304, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {0x030b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {0x030d, 0x1e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {0x030e, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {0x030f, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {0x0312, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {0x031e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {0x3000, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {0x3002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {0x3018, 0x72},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {0x3020, 0x93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {0x3021, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {0x3022, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {0x3031, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {0x303f, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {0x3305, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) {0x3307, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {0x3309, 0x29},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {0x3500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {0x3501, 0x5f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) {0x3502, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {0x3503, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {0x3504, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {0x3505, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {0x3506, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) {0x3507, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {0x3508, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {0x3509, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {0x350a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {0x350b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {0x350c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {0x350d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {0x350e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {0x350f, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {0x3510, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {0x3511, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) {0x3512, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {0x3513, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {0x3514, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {0x3515, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {0x3516, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) {0x3517, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {0x3518, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {0x3519, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {0x351a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) {0x351b, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {0x351c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {0x351d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {0x351e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) {0x351f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) {0x3520, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {0x3521, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {0x3522, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) {0x3524, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {0x3526, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {0x3528, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {0x352a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {0x3602, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {0x3603, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) {0x3604, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {0x3605, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {0x3606, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {0x3607, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {0x3609, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {0x360a, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) {0x360c, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {0x360f, 0xe0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {0x3608, 0x8f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {0x3611, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {0x3613, 0xf7},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {0x3616, 0x58},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {0x3619, 0x99},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {0x361b, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) {0x361c, 0x7a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) {0x361e, 0x79},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) {0x361f, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {0x3632, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {0x3633, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {0x3634, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {0x3635, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {0x3636, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {0x3646, 0x86},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {0x364a, 0x0b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {0x3700, 0x17},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {0x3701, 0x22},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {0x3703, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {0x370a, 0x37},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {0x3705, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) {0x3706, 0x63},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {0x3709, 0x3c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {0x370b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {0x370c, 0x30},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {0x3710, 0x24},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) {0x3711, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {0x3716, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {0x3720, 0x28},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {0x3729, 0x7b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {0x372a, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {0x372b, 0xbd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {0x372c, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) {0x372e, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) {0x373c, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {0x373e, 0x33},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) {0x3743, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) {0x3744, 0x88},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {0x3745, 0xc0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {0x374a, 0x43},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {0x374c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) {0x374e, 0x23},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {0x3751, 0x7b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {0x3752, 0x84},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {0x3753, 0xbd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {0x3754, 0xbc},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {0x3756, 0x52},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {0x375c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) {0x3760, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {0x3761, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {0x3762, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {0x3763, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {0x3764, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {0x3767, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {0x3768, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {0x3769, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) {0x376a, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {0x376b, 0x20},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {0x376c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {0x376d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {0x376e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {0x3773, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {0x3774, 0x51},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {0x3776, 0xbd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {0x3777, 0xbd},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {0x3781, 0x18},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {0x3783, 0x25},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) {0x3798, 0x1b},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {0x3800, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {0x3801, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {0x3802, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {0x3803, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {0x3804, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {0x3805, 0x97},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {0x3806, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {0x3807, 0xfb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {0x3808, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {0x3809, 0x80},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {0x380a, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {0x380b, 0xf0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) {0x380c, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {0x380d, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) {0x380e, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {0x380f, 0x12},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {0x3810, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {0x3811, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {0x3812, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {0x3813, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {0x3814, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {0x3815, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {0x3819, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {0x3820, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {0x3821, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {0x3829, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {0x382a, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {0x382b, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) {0x382d, 0x7f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {0x3830, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {0x3836, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {0x3837, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x3841, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x3846, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x3847, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x3d85, 0x36},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0x3d8c, 0x71},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {0x3d8d, 0xcb},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {0x3f0a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {0x4000, 0xf1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x4001, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x4002, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x4003, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {0x400e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {0x4011, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) {0x401a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {0x401b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {0x401c, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {0x401d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {0x401f, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {0x4020, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {0x4021, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {0x4022, 0x07},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {0x4023, 0xcf},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) {0x4024, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) {0x4025, 0x60},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {0x4026, 0x09},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) {0x4027, 0x6f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {0x4028, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {0x4029, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {0x402a, 0x06},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) {0x402b, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {0x402c, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {0x402d, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {0x402e, 0x0e},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {0x402f, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) {0x4302, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {0x4303, 0xff},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {0x4304, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {0x4305, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {0x4306, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {0x4308, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {0x4500, 0x6c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {0x4501, 0xc4},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {0x4502, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {0x4503, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {0x4601, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {0x4800, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {0x4813, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {0x481f, 0x40},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {0x4829, 0x78},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {0x4837, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {0x4b00, 0x2a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {0x4b0d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) {0x4d00, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) {0x4d01, 0x42},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {0x4d02, 0xd1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {0x4d03, 0x93},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {0x4d04, 0xf5},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) {0x4d05, 0xc1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {0x5000, 0xd3},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {0x5001, 0x11},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {0x5004, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {0x500a, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {0x500b, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {0x5032, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {0x5040, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {0x5050, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) {0x5500, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {0x5501, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {0x5502, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) {0x5503, 0x0f},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) {0x8000, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {0x8001, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {0x8002, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) {0x8003, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) {0x8004, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {0x8005, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {0x8006, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) {0x8007, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {0x8008, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {0x3638, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static const struct regval OV4686_linear_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {0x380c, 0x0a},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {0x380d, 0x14},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {0x3841, 0x02},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) {0x4800, 0x04},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {0x376e, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static const struct regval OV4686_hdr_x2_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {0x380c, 0x05},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {0x380d, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {0x3841, 0x03},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) {0x3846, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {0x3847, 0x04},//04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {0x4800, 0x0c},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {0x376e, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {0x3501, 0x10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {0x350b, 0x08},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) {0x3511, 0x01},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) {0x3517, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) {0x351d, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {0x3841, 0x03},//HDR_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {0x3847, 0x06},//HDR_2_ALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {REG_NULL, 0x00},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static const struct OV4686_mode supported_modes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) .width = 2688,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) .height = 1520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .exp_def = 0x0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .hts_def = 0x0a18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .vts_def = 0x0612,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .reg_list = OV4686_linear_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .hdr_mode = NO_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .width = 2688,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .height = 1520,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .max_fps = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .numerator = 10000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .denominator = 300000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .exp_def = 0x0600,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .hts_def = 0x0a20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) .vts_def = 0x0612,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) .reg_list = OV4686_hdr_x2_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) .hdr_mode = HDR_X2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .vc[PAD0] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .vc[PAD1] = V4L2_MBUS_CSI2_CHANNEL_0,//L->csi wr0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .vc[PAD2] = V4L2_MBUS_CSI2_CHANNEL_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .vc[PAD3] = V4L2_MBUS_CSI2_CHANNEL_1,//M->csi wr2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static const s64 link_freq_menu_items[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) OV4686_LINK_FREQ_500MHZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static const char * const OV4686_test_pattern_menu[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) "Disabled",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) "Vertical Color Bar Type 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) "Vertical Color Bar Type 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) "Vertical Color Bar Type 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) "Vertical Color Bar Type 4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Write registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int OV4686_write_reg(struct i2c_client *client, u16 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u32 len, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u32 buf_i, val_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u8 buf[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u8 *val_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) __be32 val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (len > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) buf[0] = reg >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) buf[1] = reg & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) val_be = cpu_to_be32(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) val_p = (u8 *)&val_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) buf_i = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) val_i = 4 - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) while (val_i < 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) buf[buf_i++] = val_p[val_i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (i2c_master_send(client, buf, len + 2) != len + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static int OV4686_write_array(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) const struct regval *regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) for (i = 0; ret == 0 && regs[i].addr != REG_NULL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ret = OV4686_write_reg(client, regs[i].addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) OV4686_REG_VALUE_08BIT, regs[i].val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* Read registers up to 4 at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static int OV4686_read_reg(struct i2c_client *client, u16 reg, unsigned int len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct i2c_msg msgs[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u8 *data_be_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) __be32 data_be = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) __be16 reg_addr_be = cpu_to_be16(reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (len > 4 || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) data_be_p = (u8 *)&data_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Write register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) msgs[0].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) msgs[0].flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) msgs[0].len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) msgs[0].buf = (u8 *)®_addr_be;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Read data from register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) msgs[1].addr = client->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) msgs[1].flags = I2C_M_RD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) msgs[1].len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) msgs[1].buf = &data_be_p[4 - len];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ret = i2c_transfer(client->adapter, msgs, ARRAY_SIZE(msgs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (ret != ARRAY_SIZE(msgs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) *val = be32_to_cpu(data_be);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) static int OV4686_get_reso_dist(const struct OV4686_mode *mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct v4l2_mbus_framefmt *framefmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return abs(mode->width - framefmt->width) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) abs(mode->height - framefmt->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static const struct OV4686_mode *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) OV4686_find_best_fit(struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct v4l2_mbus_framefmt *framefmt = &fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) int dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) int cur_best_fit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int cur_best_fit_dist = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dist = OV4686_get_reso_dist(&supported_modes[i], framefmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (cur_best_fit_dist == -1 || dist < cur_best_fit_dist) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) cur_best_fit_dist = dist;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) cur_best_fit = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) return &supported_modes[cur_best_fit];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static int OV4686_set_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct OV4686 *OV4686 = to_OV4686(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) const struct OV4686_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) s64 h_blank, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) mutex_lock(&OV4686->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) mode = OV4686_find_best_fit(fmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) *v4l2_subdev_get_try_format(sd, cfg, fmt->pad) = fmt->format;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) mutex_unlock(&OV4686->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) OV4686->cur_mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) __v4l2_ctrl_modify_range(OV4686->hblank, h_blank,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) __v4l2_ctrl_modify_range(OV4686->vblank, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) OV4686_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) mutex_unlock(&OV4686->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) static int OV4686_get_fmt(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) struct v4l2_subdev_format *fmt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct OV4686 *OV4686 = to_OV4686(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) const struct OV4686_mode *mode = OV4686->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) mutex_lock(&OV4686->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) fmt->format = *v4l2_subdev_get_try_format(sd, cfg, fmt->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) mutex_unlock(&OV4686->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return -ENOTTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) fmt->format.width = mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) fmt->format.height = mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) fmt->format.code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) fmt->format.field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* format info: width/height/data type/virctual channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (fmt->pad < PAD_MAX && mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) fmt->reserved[0] = mode->vc[fmt->pad];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) fmt->reserved[0] = mode->vc[PAD0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) mutex_unlock(&OV4686->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int OV4686_enum_mbus_code(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct v4l2_subdev_mbus_code_enum *code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (code->index != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) code->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) static int OV4686_enum_frame_sizes(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct v4l2_subdev_frame_size_enum *fse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) if (fse->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (fse->code != MEDIA_BUS_FMT_SBGGR10_1X10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) fse->min_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) fse->max_width = supported_modes[fse->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) fse->max_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) fse->min_height = supported_modes[fse->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) static int OV4686_enable_test_pattern(struct OV4686 *OV4686, u32 pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) val = (pattern - 1) | OV4686_TEST_PATTERN_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) val = OV4686_TEST_PATTERN_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return OV4686_write_reg(OV4686->client, OV4686_REG_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) OV4686_REG_VALUE_08BIT, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static int OV4686_g_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct v4l2_subdev_frame_interval *fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) struct OV4686 *OV4686 = to_OV4686(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) const struct OV4686_mode *mode = OV4686->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) mutex_lock(&OV4686->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) fi->interval = mode->max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) mutex_unlock(&OV4686->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static int OV4686_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct v4l2_mbus_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct OV4686 *OV4686 = to_OV4686(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) const struct OV4686_mode *mode = OV4686->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) u32 val = 1 << (OV4686_LANES - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) V4L2_MBUS_CSI2_CHANNEL_0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (mode->hdr_mode != NO_HDR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) val |= V4L2_MBUS_CSI2_CHANNEL_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (mode->hdr_mode == HDR_X3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) val |= V4L2_MBUS_CSI2_CHANNEL_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) config->type = V4L2_MBUS_CSI2_DPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) config->flags = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) static void OV4686_get_module_inf(struct OV4686 *OV4686,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct rkmodule_inf *inf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) memset(inf, 0, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) strlcpy(inf->base.sensor, OV4686_NAME, sizeof(inf->base.sensor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) strlcpy(inf->base.module, OV4686->module_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) sizeof(inf->base.module));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) strlcpy(inf->base.lens, OV4686->len_name, sizeof(inf->base.lens));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static int OV4686_set_hdrae(struct OV4686 *OV4686,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct preisp_hdrae_exp_s *ae)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) u32 l_exp = ae->long_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) u32 m_exp = ae->middle_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) u32 s_exp = ae->short_exp_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u32 l_gain = ae->long_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) u32 m_gain = ae->middle_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) u32 s_gain = ae->short_gain_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (!OV4686->has_init_exp && !OV4686->streaming) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) OV4686->init_hdrae_exp = *ae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) OV4686->has_init_exp = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) dev_dbg(&OV4686->client->dev, "OV4686 don't stream, record exp for hdr!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dev_dbg(&OV4686->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) "rev exp req: L_exp: 0x%x, 0x%x, M_exp: 0x%x, 0x%x S_exp: 0x%x, 0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) l_exp, l_gain, m_exp, m_gain, s_exp, s_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (l_exp < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) l_exp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) if (m_exp < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) m_exp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (s_exp < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) s_exp = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) if (OV4686->cur_mode->hdr_mode == HDR_X2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) l_gain = m_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) l_exp = m_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) m_gain = s_gain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) m_exp = s_exp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) ret = OV4686_write_reg(OV4686->client, OV4686_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) OV4686_REG_VALUE_08BIT, OV4686_GROUP_UPDATE_START_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) ret |= OV4686_write_reg(OV4686->client, OV4686_REG_L_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) OV4686_REG_VALUE_16BIT, l_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) ret |= OV4686_write_reg(OV4686->client, OV4686_REG_L_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) OV4686_REG_VALUE_24BIT, l_exp << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret |= OV4686_write_reg(OV4686->client, OV4686_REG_M_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) OV4686_REG_VALUE_16BIT, m_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ret |= OV4686_write_reg(OV4686->client, OV4686_REG_M_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) OV4686_REG_VALUE_24BIT, m_exp << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (OV4686->cur_mode->hdr_mode == HDR_X3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ret |= OV4686_write_reg(OV4686->client, OV4686_REG_S_GAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) OV4686_REG_VALUE_16BIT, s_gain);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) ret |= OV4686_write_reg(OV4686->client, OV4686_REG_S_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) OV4686_REG_VALUE_24BIT, s_exp << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) ret |= OV4686_write_reg(OV4686->client, OV4686_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) OV4686_REG_VALUE_08BIT, OV4686_GROUP_UPDATE_END_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) ret |= OV4686_write_reg(OV4686->client, OV4686_GROUP_UPDATE_ADDRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) OV4686_REG_VALUE_08BIT, OV4686_GROUP_UPDATE_LAUNCH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) static long OV4686_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct OV4686 *OV4686 = to_OV4686(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u32 i, h, w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) long ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) OV4686_get_module_inf(OV4686, (struct rkmodule_inf *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) hdr->esp.mode = HDR_NORMAL_VC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) hdr->hdr_mode = OV4686->cur_mode->hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) hdr = (struct rkmodule_hdr_cfg *)arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) w = OV4686->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) h = OV4686->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (w == supported_modes[i].width &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) h == supported_modes[i].height &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) supported_modes[i].hdr_mode == hdr->hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) OV4686->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (i == ARRAY_SIZE(supported_modes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dev_err(&OV4686->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) "not find hdr mode:%d %dx%d config\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) hdr->hdr_mode, w, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) w = OV4686->cur_mode->hts_def - OV4686->cur_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) h = OV4686->cur_mode->vts_def - OV4686->cur_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) __v4l2_ctrl_modify_range(OV4686->hblank, w, w, 1, w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) __v4l2_ctrl_modify_range(OV4686->vblank, h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) OV4686_VTS_MAX - OV4686->cur_mode->height, 1, h);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return OV4686_set_hdrae(OV4686, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) stream = *((u32 *)arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (stream)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) ret = OV4686_write_reg(OV4686->client, OV4686_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) OV4686_REG_VALUE_08BIT, OV4686_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) ret = OV4686_write_reg(OV4686->client, OV4686_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) OV4686_REG_VALUE_08BIT, OV4686_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) static long OV4686_compat_ioctl32(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) unsigned int cmd, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) void __user *up = compat_ptr(arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct rkmodule_inf *inf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct rkmodule_awb_cfg *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct rkmodule_hdr_cfg *hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct preisp_hdrae_exp_s *hdrae;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) long ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) u32 stream = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) switch (cmd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) case RKMODULE_GET_MODULE_INFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) inf = kzalloc(sizeof(*inf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (!inf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) ret = OV4686_ioctl(sd, cmd, inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) ret = copy_to_user(up, inf, sizeof(*inf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) kfree(inf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) case RKMODULE_AWB_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ret = copy_from_user(cfg, up, sizeof(*cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ret = OV4686_ioctl(sd, cmd, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) kfree(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) case RKMODULE_GET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ret = OV4686_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ret = copy_to_user(up, hdr, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) case RKMODULE_SET_HDR_CFG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) hdr = kzalloc(sizeof(*hdr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (!hdr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ret = copy_from_user(hdr, up, sizeof(*hdr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) ret = OV4686_ioctl(sd, cmd, hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) kfree(hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) case PREISP_CMD_SET_HDRAE_EXP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) hdrae = kzalloc(sizeof(*hdrae), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (!hdrae) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ret = copy_from_user(hdrae, up, sizeof(*hdrae));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) ret = OV4686_ioctl(sd, cmd, hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) kfree(hdrae);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) case RKMODULE_SET_QUICK_STREAM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ret = copy_from_user(&stream, up, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) ret = OV4686_ioctl(sd, cmd, &stream);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) ret = -ENOIOCTLCMD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static int __OV4686_start_stream(struct OV4686 *OV4686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) ret = OV4686_write_array(OV4686->client, OV4686_2688x1520_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ret |= OV4686_write_array(OV4686->client, OV4686->cur_mode->reg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* In case these controls are set before streaming */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ret = __v4l2_ctrl_handler_setup(&OV4686->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (OV4686->has_init_exp && OV4686->cur_mode->hdr_mode != NO_HDR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ret = OV4686_ioctl(&OV4686->subdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) PREISP_CMD_SET_HDRAE_EXP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) &OV4686->init_hdrae_exp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) dev_err(&OV4686->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) "init exp fail in hdr mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return OV4686_write_reg(OV4686->client, OV4686_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) OV4686_REG_VALUE_08BIT, OV4686_MODE_STREAMING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static int __OV4686_stop_stream(struct OV4686 *OV4686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) OV4686->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) return OV4686_write_reg(OV4686->client, OV4686_REG_CTRL_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) OV4686_REG_VALUE_08BIT, OV4686_MODE_SW_STANDBY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static int OV4686_s_stream(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) struct OV4686 *OV4686 = to_OV4686(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) struct i2c_client *client = OV4686->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) mutex_lock(&OV4686->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) on = !!on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) if (on == OV4686->streaming)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ret = __OV4686_start_stream(OV4686);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) v4l2_err(sd, "start stream failed while write regs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) __OV4686_stop_stream(OV4686);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) OV4686->streaming = on;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) mutex_unlock(&OV4686->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) static int OV4686_s_power(struct v4l2_subdev *sd, int on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct OV4686 *OV4686 = to_OV4686(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct i2c_client *client = OV4686->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) mutex_lock(&OV4686->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* If the power state is not modified - no work to do. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) if (OV4686->power_on == !!on)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) if (on) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) ret = pm_runtime_get_sync(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ret = OV4686_write_array(OV4686->client, OV4686_global_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) v4l2_err(sd, "could not set init registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) pm_runtime_put_noidle(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) goto unlock_and_return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) OV4686->power_on = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) OV4686->power_on = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) unlock_and_return:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) mutex_unlock(&OV4686->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) /* Calculate the delay in us by clock rate and clock cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) static inline u32 OV4686_cal_delay(u32 cycles)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) return DIV_ROUND_UP(cycles, OV4686_XVCLK_FREQ / 1000 / 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) static int __OV4686_power_on(struct OV4686 *OV4686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) u32 delay_us;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct device *dev = &OV4686->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (!IS_ERR_OR_NULL(OV4686->pins_default)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) ret = pinctrl_select_state(OV4686->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) OV4686->pins_default);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) dev_err(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ret = clk_set_rate(OV4686->xvclk, OV4686_XVCLK_FREQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) dev_warn(dev, "Failed to set xvclk rate (24MHz)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) if (clk_get_rate(OV4686->xvclk) != OV4686_XVCLK_FREQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) ret = clk_prepare_enable(OV4686->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) dev_err(dev, "Failed to enable xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (!IS_ERR(OV4686->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) gpiod_set_value_cansleep(OV4686->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) ret = regulator_bulk_enable(OV4686_NUM_SUPPLIES, OV4686->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) dev_err(dev, "Failed to enable regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (!IS_ERR(OV4686->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) gpiod_set_value_cansleep(OV4686->reset_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) usleep_range(500, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (!IS_ERR(OV4686->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) gpiod_set_value_cansleep(OV4686->pwdn_gpio, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) /* 8192 cycles prior to first SCCB transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) delay_us = OV4686_cal_delay(8192);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) usleep_range(delay_us, delay_us * 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) clk_disable_unprepare(OV4686->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static void __OV4686_power_off(struct OV4686 *OV4686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct device *dev = &OV4686->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (!IS_ERR(OV4686->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) gpiod_set_value_cansleep(OV4686->pwdn_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) clk_disable_unprepare(OV4686->xvclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (!IS_ERR(OV4686->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) gpiod_set_value_cansleep(OV4686->reset_gpio, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (!IS_ERR_OR_NULL(OV4686->pins_sleep)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ret = pinctrl_select_state(OV4686->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) OV4686->pins_sleep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) dev_dbg(dev, "could not set pins\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) regulator_bulk_disable(OV4686_NUM_SUPPLIES, OV4686->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) static int OV4686_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct OV4686 *OV4686 = to_OV4686(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return __OV4686_power_on(OV4686);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) static int OV4686_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) struct i2c_client *client = to_i2c_client(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct OV4686 *OV4686 = to_OV4686(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) __OV4686_power_off(OV4686);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) static int OV4686_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) struct OV4686 *OV4686 = to_OV4686(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct v4l2_mbus_framefmt *try_fmt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) v4l2_subdev_get_try_format(sd, fh->pad, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) const struct OV4686_mode *def_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) mutex_lock(&OV4686->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* Initialize try_fmt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) try_fmt->width = def_mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) try_fmt->height = def_mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) try_fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10;//grbg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) try_fmt->field = V4L2_FIELD_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) mutex_unlock(&OV4686->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /* No crop or compose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) static int OV4686_enum_frame_interval(struct v4l2_subdev *sd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct v4l2_subdev_pad_config *cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) struct v4l2_subdev_frame_interval_enum *fie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) if (fie->index >= ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) fie->code = MEDIA_BUS_FMT_SBGGR10_1X10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) fie->width = supported_modes[fie->index].width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) fie->height = supported_modes[fie->index].height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) fie->interval = supported_modes[fie->index].max_fps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) fie->reserved[0] = supported_modes[fie->index].hdr_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static const struct dev_pm_ops OV4686_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) SET_RUNTIME_PM_OPS(OV4686_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) OV4686_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static const struct v4l2_subdev_internal_ops OV4686_internal_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) .open = OV4686_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static const struct v4l2_subdev_core_ops OV4686_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .s_power = OV4686_s_power,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .ioctl = OV4686_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #ifdef CONFIG_COMPAT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .compat_ioctl32 = OV4686_compat_ioctl32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) static const struct v4l2_subdev_video_ops OV4686_video_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .s_stream = OV4686_s_stream,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .g_frame_interval = OV4686_g_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) static const struct v4l2_subdev_pad_ops OV4686_pad_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .enum_mbus_code = OV4686_enum_mbus_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .enum_frame_size = OV4686_enum_frame_sizes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .enum_frame_interval = OV4686_enum_frame_interval,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .get_fmt = OV4686_get_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .set_fmt = OV4686_set_fmt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .get_mbus_config = OV4686_g_mbus_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) static const struct v4l2_subdev_ops OV4686_subdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .core = &OV4686_core_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .video = &OV4686_video_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .pad = &OV4686_pad_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) static int OV4686_set_ctrl(struct v4l2_ctrl *ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) struct OV4686 *OV4686 = container_of(ctrl->handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) struct OV4686, ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) struct i2c_client *client = OV4686->client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) s64 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) /* Propagate change of current control to all related controls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) /* Update max exposure while meeting expected vblanking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) max = OV4686->cur_mode->height + ctrl->val - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) __v4l2_ctrl_modify_range(OV4686->exposure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) OV4686->exposure->minimum, max,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) OV4686->exposure->step,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) OV4686->exposure->default_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (!pm_runtime_get_if_in_use(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) switch (ctrl->id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) case V4L2_CID_EXPOSURE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /* 4 least significant bits of expsoure are fractional part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ret = OV4686_write_reg(OV4686->client, OV4686_REG_EXPOSURE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) OV4686_REG_VALUE_24BIT, ctrl->val << 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) case V4L2_CID_ANALOGUE_GAIN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) ret = OV4686_write_reg(OV4686->client, OV4686_REG_GAIN_H,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) OV4686_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) (ctrl->val >> OV4686_GAIN_H_SHIFT) & OV4686_GAIN_H_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ret |= OV4686_write_reg(OV4686->client, OV4686_REG_GAIN_L,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) OV4686_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) ctrl->val & OV4686_GAIN_L_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) case V4L2_CID_VBLANK:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) ret = OV4686_write_reg(OV4686->client, OV4686_REG_VTS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) OV4686_REG_VALUE_16BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) ctrl->val + OV4686->cur_mode->height);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) case V4L2_CID_TEST_PATTERN:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) ret = OV4686_enable_test_pattern(OV4686, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) case V4L2_CID_HFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ret = OV4686_read_reg(OV4686->client, OV4686_HFLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) OV4686_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) val |= MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) val &= ~MIRROR_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) ret = OV4686_write_reg(OV4686->client, OV4686_HFLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) OV4686_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) case V4L2_CID_VFLIP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) ret = OV4686_read_reg(OV4686->client, OV4686_VFLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) OV4686_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (ctrl->val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) val |= FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) val &= ~FLIP_BIT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) ret = OV4686_write_reg(OV4686->client, OV4686_VFLIP_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) OV4686_REG_VALUE_08BIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) dev_warn(&client->dev, "%s Unhandled id:0x%x, val:0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) __func__, ctrl->id, ctrl->val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) pm_runtime_put(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) static const struct v4l2_ctrl_ops OV4686_ctrl_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) .s_ctrl = OV4686_set_ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) static int OV4686_initialize_controls(struct OV4686 *OV4686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) const struct OV4686_mode *mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) struct v4l2_ctrl_handler *handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) struct v4l2_ctrl *ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) s64 exposure_max, vblank_def;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) u32 h_blank;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) handler = &OV4686->ctrl_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) mode = OV4686->cur_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) ret = v4l2_ctrl_handler_init(handler, 9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) handler->lock = &OV4686->mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) ctrl = v4l2_ctrl_new_int_menu(handler, NULL, V4L2_CID_LINK_FREQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) 0, 0, link_freq_menu_items);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) v4l2_ctrl_new_std(handler, NULL, V4L2_CID_PIXEL_RATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) 0, OV4686_PIXEL_RATE, 1, OV4686_PIXEL_RATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) h_blank = mode->hts_def - mode->width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) OV4686->hblank = v4l2_ctrl_new_std(handler, NULL, V4L2_CID_HBLANK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) h_blank, h_blank, 1, h_blank);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) if (OV4686->hblank)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) OV4686->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) vblank_def = mode->vts_def - mode->height;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) OV4686->vblank = v4l2_ctrl_new_std(handler, &OV4686_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) V4L2_CID_VBLANK, vblank_def,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) OV4686_VTS_MAX - mode->height,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) 1, vblank_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) exposure_max = mode->vts_def - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) OV4686->exposure = v4l2_ctrl_new_std(handler, &OV4686_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) V4L2_CID_EXPOSURE, OV4686_EXPOSURE_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) exposure_max, OV4686_EXPOSURE_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) mode->exp_def);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) OV4686->anal_gain = v4l2_ctrl_new_std(handler, &OV4686_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) V4L2_CID_ANALOGUE_GAIN, OV4686_GAIN_MIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) OV4686_GAIN_MAX, OV4686_GAIN_STEP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) OV4686_GAIN_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) OV4686->test_pattern = v4l2_ctrl_new_std_menu_items(handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) &OV4686_ctrl_ops, V4L2_CID_TEST_PATTERN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) ARRAY_SIZE(OV4686_test_pattern_menu) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) 0, 0, OV4686_test_pattern_menu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) v4l2_ctrl_new_std(handler, &OV4686_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) V4L2_CID_HFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) v4l2_ctrl_new_std(handler, &OV4686_ctrl_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) V4L2_CID_VFLIP, 0, 1, 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (handler->error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ret = handler->error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) dev_err(&OV4686->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) "Failed to init controls(%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) OV4686->subdev.ctrl_handler = handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) OV4686->has_init_exp = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) v4l2_ctrl_handler_free(handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) static int OV4686_check_sensor_id(struct OV4686 *OV4686,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) struct device *dev = &OV4686->client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) u32 id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) ret = OV4686_read_reg(client, OV4686_REG_CHIP_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) OV4686_REG_VALUE_16BIT, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (id != CHIP_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) dev_err(dev, "Unexpected sensor id(%06x), ret(%d)\n", id, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) dev_info(dev, "Detected OV%06x sensor\n", CHIP_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) static int OV4686_configure_regulators(struct OV4686 *OV4686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) for (i = 0; i < OV4686_NUM_SUPPLIES; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) OV4686->supplies[i].supply = OV4686_supply_names[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) return devm_regulator_bulk_get(&OV4686->client->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) OV4686_NUM_SUPPLIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) OV4686->supplies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) static int OV4686_probe(struct i2c_client *client,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) const struct i2c_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) struct device *dev = &client->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) struct OV4686 *OV4686;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) struct v4l2_subdev *sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) char facing[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) u32 i, hdr_mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) dev_info(dev, "driver version: %02x.%02x.%02x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) DRIVER_VERSION >> 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) (DRIVER_VERSION & 0xff00) >> 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) DRIVER_VERSION & 0x00ff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) OV4686 = devm_kzalloc(dev, sizeof(*OV4686), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (!OV4686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) of_property_read_u32(node, OF_CAMERA_HDR_MODE, &hdr_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) ret = of_property_read_u32(node, RKMODULE_CAMERA_MODULE_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) &OV4686->module_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_FACING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) &OV4686->module_facing);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) ret |= of_property_read_string(node, RKMODULE_CAMERA_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) &OV4686->module_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ret |= of_property_read_string(node, RKMODULE_CAMERA_LENS_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) &OV4686->len_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) dev_err(dev, "could not get module information!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) OV4686->client = client;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) for (i = 0; i < ARRAY_SIZE(supported_modes); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (hdr_mode == supported_modes[i].hdr_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) OV4686->cur_mode = &supported_modes[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (i == ARRAY_SIZE(supported_modes))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) OV4686->cur_mode = &supported_modes[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) OV4686->xvclk = devm_clk_get(dev, "xvclk");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (IS_ERR(OV4686->xvclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) dev_err(dev, "Failed to get xvclk\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) OV4686->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) if (IS_ERR(OV4686->reset_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) dev_warn(dev, "Failed to get reset-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) OV4686->pwdn_gpio = devm_gpiod_get(dev, "pwdn", GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) if (IS_ERR(OV4686->pwdn_gpio))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) dev_warn(dev, "Failed to get pwdn-gpios\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) OV4686->pinctrl = devm_pinctrl_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (!IS_ERR(OV4686->pinctrl)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) OV4686->pins_default =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) pinctrl_lookup_state(OV4686->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) OF_CAMERA_PINCTRL_STATE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (IS_ERR(OV4686->pins_default))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) dev_err(dev, "could not get default pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) OV4686->pins_sleep =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) pinctrl_lookup_state(OV4686->pinctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) OF_CAMERA_PINCTRL_STATE_SLEEP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) if (IS_ERR(OV4686->pins_sleep))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) dev_err(dev, "could not get sleep pinstate\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) dev_err(dev, "no pinctrl\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) ret = OV4686_configure_regulators(OV4686);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) dev_err(dev, "Failed to get power regulators\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) mutex_init(&OV4686->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) sd = &OV4686->subdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) v4l2_i2c_subdev_init(sd, client, &OV4686_subdev_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) ret = OV4686_initialize_controls(OV4686);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) goto err_destroy_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) ret = __OV4686_power_on(OV4686);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) goto err_free_handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) ret = OV4686_check_sensor_id(OV4686, client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) #ifdef CONFIG_VIDEO_V4L2_SUBDEV_API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) sd->internal_ops = &OV4686_internal_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) V4L2_SUBDEV_FL_HAS_EVENTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) OV4686->pad.flags = MEDIA_PAD_FL_SOURCE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) ret = media_entity_pads_init(&sd->entity, 1, &OV4686->pad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) goto err_power_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) memset(facing, 0, sizeof(facing));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (strcmp(OV4686->module_facing, "back") == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) facing[0] = 'b';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) facing[0] = 'f';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) snprintf(sd->name, sizeof(sd->name), "m%02d_%s_%s %s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) OV4686->module_index, facing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) OV4686_NAME, dev_name(sd->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) ret = v4l2_async_register_subdev_sensor_common(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) dev_err(dev, "v4l2 async register subdev failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) goto err_clean_entity;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) pm_runtime_idle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) err_clean_entity:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) err_power_off:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) __OV4686_power_off(OV4686);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) err_free_handler:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) v4l2_ctrl_handler_free(&OV4686->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) err_destroy_mutex:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) mutex_destroy(&OV4686->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) static int OV4686_remove(struct i2c_client *client)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) struct v4l2_subdev *sd = i2c_get_clientdata(client);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) struct OV4686 *OV4686 = to_OV4686(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) v4l2_async_unregister_subdev(sd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) #if defined(CONFIG_MEDIA_CONTROLLER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) media_entity_cleanup(&sd->entity);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) v4l2_ctrl_handler_free(&OV4686->ctrl_handler);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) mutex_destroy(&OV4686->mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) pm_runtime_disable(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) if (!pm_runtime_status_suspended(&client->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) __OV4686_power_off(OV4686);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) pm_runtime_set_suspended(&client->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) #if IS_ENABLED(CONFIG_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) static const struct of_device_id OV4686_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) { .compatible = "ovti,OV4686" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) MODULE_DEVICE_TABLE(of, OV4686_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) static const struct i2c_device_id OV4686_match_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) { "ovti,OV4686", 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) static struct i2c_driver OV4686_i2c_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .name = OV4686_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .pm = &OV4686_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .of_match_table = of_match_ptr(OV4686_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .probe = &OV4686_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .remove = &OV4686_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .id_table = OV4686_match_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) static int __init sensor_mod_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) return i2c_add_driver(&OV4686_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) static void __exit sensor_mod_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) i2c_del_driver(&OV4686_i2c_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) device_initcall_sync(sensor_mod_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) module_exit(sensor_mod_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) MODULE_DESCRIPTION("OmniVision OV4686 sensor driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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